CN113923172B

CN113923172B - FF field bus switch with time certainty

Info

Publication number: CN113923172B
Application number: CN202110853660.4A
Authority: CN
Inventors: 严伟; 王雪迪; 吴鹏飞; 王博
Original assignee: Peking University
Current assignee: Peking University
Priority date: 2021-07-28
Filing date: 2021-07-28
Publication date: 2022-10-21
Anticipated expiration: 2041-07-28
Also published as: CN113923172A

Abstract

The invention relates to the field of field buses and industrial internets, and discloses a switch framework supporting multi-port FF (Foundation Fieldbus) bus data exchange and an implementation method. The invention provides a method for realizing multi-port FF bus data conversion by adopting a hardware circuit, and through the FF field bus switch framework and the realization method, multi-port FF bus data can be accessed into a TSN switch under the condition of ensuring time certainty, so that the multi-port FF bus data can be accessed into an industrial internet. The FF bus data is transmitted to the hardware circuit of the FF field bus switch through the data transceiver module, and after checking, priority (defined in VLANTag) judgment and Ethernet frame packaging operation are carried out in the circuit, the packaged FF bus data is transmitted to the TSN switch through the TSN interface module. The whole transmission process is completely processed by adopting a hardware circuit, the conversion speed is high, the conversion time is short, the multi-port data conversion adopts a parallel mode, and data congestion caused by large data volume can be avoided.

Description

FF field bus switch with time certainty

Technical Field

The invention belongs to the field of field buses and industrial internets, and relates to a switch framework supporting multi-port FF (Foundation Fieldbus) bus data exchange and an implementation method.

Background

The foundation fieldbus system is a low-bandwidth communication network, in which field autonomous devices having communication capability and simultaneously performing control, measurement, and the like are used as network nodes and interconnected as a network by fieldbus. Because it adopts serial data communication, and only the network segment formed from two wires can be hung with several field instruments, so that it can radically change one-to-one wiring mode of original analog instrument, and can save cost, and can bring many conveniences for design, installation and maintenance.

Interconnection and interworking of numerous industrial field devices become a first problem of the industrial internet which needs to be rapidly solved urgently, and a huge amount of connection cost is increased due to more and more heterogeneous devices. However, in the present phase, due to different communication standards used by countries and equipment manufacturing enterprises in the world, the communication protocols between industrial equipment are different, which causes difficulty in interconnection between industrial equipment in the enterprise, mutual independence between systems, and failure in real-time information interaction. Although the industrial gateways on the market are various in types, the functions of the products are not complete, and most of the products cannot support the access and transmission of various types of data and multi-protocol data.

TSN (Time sensitive networking, time sensitive network) is a set of "sub-standards" established based on specific application requirements under the IEEE802.1 standard framework, and is intended to establish a "universal" Time sensitive mechanism for ethernet protocols to ensure real-Time performance, certainty and low latency of network data transmission.

The existing FF field bus gateway supports a few ports, the conversion from field bus data to Ethernet data is generally realized by adopting a method of general processor software, when the number of ports is large and the data volume is large, data congestion is caused, and if the data buffer zone is not reserved enough, data loss is caused, so that the certainty of communication cannot be ensured, and the simultaneous conversion of more FF field bus ports cannot be met. The TSN is an important component of industrial Ethernet, and the existing FF field bus gateway does not support interconnection with the TSN, so that the requirement of industrial Internet cannot be well met.

Disclosure of Invention

Aiming at the problem that the conventional FF field bus gateway can not transmit multi-port data under the condition of meeting communication certainty, the invention provides a method for realizing multi-port FF bus data conversion by adopting a hardware circuit.

The FF bus data is transmitted into a hardware circuit of the FF field bus switch through a data transceiver module, and after checking, priority (defined in VLAN Tag) judgment and Ethernet frame packing operation are carried out in the circuit, the packaged FF bus data is transmitted to the TSN switch through a TSN interface module. The whole transmission process is completely processed by adopting a hardware circuit, the conversion speed is high, the conversion time is short, the multi-port data conversion adopts a parallel mode, and data congestion caused by large data volume can be avoided.

The invention mainly comprises the following modules: the device comprises a data transceiving module, a VID mapping module, a packet unpacking module, a TSN interface module and an AXI4 interface module.

Drawings

Fig. 1FF fieldbus switch architecture system block diagram.

Fig. 2FF fieldbus switch architecture schematic.

Fig. 3 is a schematic diagram of a data transceiver module.

Fig. 4 contains an ethernet frame structure diagram of FF fieldbus data.

Fig. 5 is a flow chart of fieldbus data transmission in the present invention.

Fig. 6 is a state transition diagram of a data reception state machine.

FIG. 7 state transition diagram of data transmission state machine

Detailed Description

The implementation details are as follows:

the embodiment of the invention relates to an FF field bus switch framework with time certainty and an implementation method. The core of the invention is that the deterministic communication of FF bus data in the TSN network is realized by using a TSN switch and VLAN technology through a hardware circuit. Fig. 1 shows the application of the present invention in a TSN network and a FF bus network, and a schematic block diagram of the present invention is shown in fig. 2.

The working principle and the process are as follows:

for uplink data, namely FF bus network- > FF fieldbus switch- > TSN switch, FF bus data enters FF fieldbus switch through data transceiver module, VID mapping module adds VID value and priority field to FF bus data frame according to different transceiver circuit interfaces by comparing VID mapping table and priority mapping table, VID mapping module sends data to packet unpacking module according to configured priority in sequence if multiple ports receive data at the same time, packet unpacking module adds bus data to ethernet frame head and frame tail, ethernet frame structure diagram containing FF bus data please refer to fig. 4. And the packet unpacking module transmits the Ethernet frame containing the FF bus data to the TSN interface module, and the TSN interface module transmits the data to the TSN switch according to the standard time sequence of the Ethernet interface.

For downlink data, namely, a TSN (transmission line network) switch- > FF field bus switch- > FF bus network, an Ethernet frame containing FF bus data enters the FF field bus switch through a TSN interface module, a packet unpacking module removes an Ethernet frame header and a frame tail, only FF bus data and VID (video identifier) values are reserved, a VID mapping module judges which data transceiver module the FF bus data are sent to according to the VID values and a VID mapping table, and the data transceiver module sends the bus data to FF field bus equipment after receiving the FF bus data from the VID mapping module.

The FF bus data transmission flow in the present invention is shown in fig. 5.

On the basis of encapsulating FF bus data into a standard Ethernet frame, the invention adds VLAN Tag conforming to IEEE 802.1Q standard, and the total number of the VLAN Tag is 4 bytes. Containing a TPID of 2 bytes and a TCI of 2 bytes, the TPID value is 0xc8100 for ethernet frames, the TCI includes a priority field of 3 bits, which can represent eight priority levels, a 1-bit representative format indicator, and a VID (VLAN Identifier) of 12bits, wherein the priority field can specify the priority level of each port, and the larger the priority field value, the higher the priority level. When a plurality of ports receive data from the bus at the same time, the TSN switch can determine which port data is switched preferentially according to the priority level; meanwhile, each port is assigned with a VID value, and the FF field switch and the upper computer distinguish which port the transmitted data is according to the VID in the data frame.

VLAN Tag has two important roles: firstly, for the condition that multiple paths of uplink data are generated simultaneously, the sequence of sending the data to the TSN switch can be judged according to the priority domain; and secondly, the TSN switch can determine the transmission priority of the data of each FF bus port in the TSN according to the priority domain.

Detailed description of the modules:

The data transceiver module also comprises a bus receiving module, a bus transmitting module, a receiving FIFO module, a transmitting FIFO module, a gating module, a baud rate calculating module and a clock frequency dividing module. Please refer to fig. 3 for a schematic diagram of the data transceiver module.

The bus receiving module realizes the functions of FF data receiving time sequence and CRC check, and stores the bus data received from the bus receiving interface into a receiving FIFO; and the FF data sending module realizes the functions of sending time sequence and CRC check code calculation and sends the bus data transmitted by the sending FIFO to the FF bus port.

The receiving FIFO module and the sending FIFO module are realized by adopting asynchronous FIFO which is designed based on a double-port RAM. Because the UART transceiving speed is different from the transceiving speed of the TSN interface module, the data is cached by adopting the asynchronous FIFO.

The VID mapping module comprises a VID mapping table, a VID mapping circuit and a multi-path selection circuit, wherein the VID mapping table needs the CPU to be configured into the VID mapping module through the AXI4 interface module.

The VID mapping module receives the bus data from the receiving FIFO, attaches the VID value and the priority field corresponding to the port to the FF bus data according to different ports, the VID mapping table and the priority mapping table, the attaching position is the front end of the bus data, and then sends the bus data with the VID value and the priority field attached to the FF bus data to the packet unpacking module; for downlink data, namely an upper computer-TSN exchanger-FF bus network, the VID mapping module receives bus data from the packet unpacking module, the foremost end of the bus data is provided with 12bits of VID information, and the VID mapping module compares the VID mapping table according to the VID value and transmits the FF bus data with the VID value removed to a corresponding transmission FIFO.

The function that the stated package unpacks the module and finishes is, for the up run data, namely FF bus network- > FF field bus exchanger- > TSN exchanger, after the package unpacks the module and receives the data with VID value from VID mapping module, add the frame head frame end of Ethernet on the basis of this data frame, the Ethernet frame head that needs to add includes: destination address, source address, type/length, and the end of the ethernet frame to be added is the frame check sequence FCS.

In which besides the destination address, the source address, the type/length, and the VLAN Tag value of 4 bytes are added before the bus data, since the VID mapping module has added the VID value before the bus data, the packet unpacking module only needs to add the TPID, the priority field, and the typical format indicator in the VLAN Tag. The priority value of the priority domain needs to be added according to the priority mapping table configured by the CPU through the AXI4 interface module.

For downlink data, namely an upper computer, a switch device and an FF bus network, the packet unpacking module receives an Ethernet frame with VLAN Tag from the TSN interface module, the packet unpacking module removes the information of the head and the tail of the Ethernet frame, and only keeps the VID value of 12bits and bus data.

The AXI4 interface module is to implement an AXI4 lite protocol, and includes 2 AXI4 lite registers with 32 bit widths, which are used for caching configuration information transmitted to an FF fieldbus switch IP by a CPU, where the configuration information is as follows: priority table in VLAN Tag, VID value of each port in VLAN Tag, parity check configuration information and baud rate configuration information needed by port.

The TSN interface module realizes GMII interface time sequence in accordance with IEEE 802.3 standard, and has the function that bus data packaged into Ethernet frame format is transmitted with TSN exchanger through the TSN interface module.

Description of the state machine:

the invention comprises two state machines in total: fig. 6 and fig. 7 are referenced for the state transition diagrams of the data receiving state machine and the data sending state machine.

The data receiving state machine and the data sending state machine are implemented in the data transceiving module.

The data receiving state mainly completes FF bus protocol receiving sequence, after the system is reset for a period of time, the system jumps to an idle state from a reset state, after a data signal on data is detected, jumps to a lead code identification state, jumps back to the idle state if the data signal is identified incorrectly, jumps to a protocol data receiving state if the data signal is identified correctly, and performs CRC check synchronously with data receiving.

The data sending state mainly completes FF bus protocol sending time sequence, the system jumps to an idle state from a reset state after resetting for a period of time, jumps to a lead code sending state after detecting a sending FIFO cache completion signal, jumps to a sending frame front boundary code sending state after the lead code sending is completed, jumps to a sending protocol data sending state, jumps to a sending CRC (cyclic redundancy check) code sending state, finishes CEC (consumer electronics control) code sending, jumps to a sending frame end code sending state, finishes sending frame end codes and jumps back to the idle state.

Claims

1. An FF fieldbus switch with time determinism, comprising the following modules: the system comprises a data transceiving module, a VID mapping module, a packet unpacking module, a TSN interface module and an AXI4 interface module; wherein:

the data transceiver module also comprises a bus receiving module, a bus transmitting module, a receiving FIFO module and a transmitting FIFO module; the bus receiving module realizes the functions of FF data receiving time sequence and CRC check, and stores the bus data received from the bus receiving interface into a receiving FIFO; the FF data transmitting module realizes the functions of transmitting time sequence and CRC check code calculation, and transmits the bus data transmitted by the transmitting FIFO to an FF bus port;

the VID mapping module comprises a VID mapping table, a VID mapping circuit and a multi-path selection circuit, wherein the VID mapping table needs the CPU to be configured in the VID mapping module through an AXI4 interface module; for the uplink data, namely FF field bus network- > FF field bus switch- > TSN switch, the VID mapping module receives the bus data from the receiving FIFO, the VID value and the priority field corresponding to the port are added to the FF bus data according to different ports, the VID mapping table and the priority mapping table, the addition position is the front end of the bus data, and then the bus data with the VID value and the priority field added are sent to the packet unpacking module; for downlink data, namely an upper computer-a TSN exchanger-an FF bus network, a VID mapping module receives bus data from a packet unpacking module, the foremost end of the bus data is provided with 12bits of VID information, and the VID mapping module compares a VID mapping table according to a VID value and transmits the FF bus data with the VID value removed to a corresponding transmission FIFO;

for uplink data, namely FF bus network- > FF field bus switch- > TSN switch, the packet unpacking module receives data with VID value from the VID mapping module and adds an Ethernet frame header and frame tail on the basis of the data frame; for downlink data, namely an upper computer-a switch device-an FF bus network, a packet unpacking module receives an Ethernet frame with a VLAN Tag from a TSN interface module, the packet unpacking module removes information of a frame head and a frame tail of the Ethernet, and only a VID value of 12bits and bus data are reserved;

the AXI4 interface module is used for realizing an AXI4 lite protocol, and comprises 2 AXI4 lite registers with 32 bit widths, wherein the AXI4 lite registers are used for caching configuration information which is transmitted to an FF field bus switch IP by a CPU;

2. The FF fieldbus switch with time certainty of claim 1, wherein the AXI4 interface module configuration information is as follows: priority table in VLAN Tag, VID value of each port in VLAN Tag, parity check configuration information and baud rate configuration information needed by port.

3. The FF fieldbus switch with time determinism of claim 1, wherein the receive FIFO module and the transmit FIFO module are implemented with asynchronous FIFOs, the asynchronous FIFOs being based on a dual port RAM design.

4. The FF fieldbus switch of claim 1, wherein the packet decapsulation module only needs to add the TPID, the priority field, and the canonical format indicator in the VLAN Tag, and the priority value of the priority field needs to be added according to the priority mapping table configured by the CPU through the AXI4 interface module.