CN113923108B - Method, system, equipment and storage medium for automatically configuring time delay parameters - Google Patents
Method, system, equipment and storage medium for automatically configuring time delay parameters Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
- H04L41/08—Configuration management of networks or network elements
- H04L41/0803—Configuration setting
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- H—ELECTRICITY
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- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
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- H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
- H04L41/08—Configuration management of networks or network elements
- H04L41/0803—Configuration setting
- H04L41/0823—Configuration setting characterised by the purposes of a change of settings, e.g. optimising configuration for enhancing reliability
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- H—ELECTRICITY
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- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
- H04L41/08—Configuration management of networks or network elements
- H04L41/0876—Aspects of the degree of configuration automation
- H04L41/0886—Fully automatic configuration
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- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
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Abstract
The invention provides a method, a system, equipment and a storage medium for automatically configuring time delay parameters, which are used for solving the technical problem that the experimental parameters for configuring a network interface cannot be automatically adjusted in the prior art, wherein the method for automatically configuring the time delay parameters comprises the following steps: the method comprises the steps of sequentially sending a plurality of different delay time lengths which can be used by a PHY chip to the PHY chip according to time periods, so that the PHY chip delays a time sequence signal in the PHY chip by using the corresponding delay time length in the corresponding time period; receiving test data transmitted by the PHY chip in each time period, and recording the number of error frames generated by communication between the MAC and the PHY chip in the corresponding time period; and setting the delay time length corresponding to the time period with the least number of error frames generated in all the time periods as the delay time length finally used by the PHY chip.
Description
Technical Field
The present invention relates to the field of network interfaces, and in particular, to a method, system, device, and storage medium for automatically configuring a delay parameter.
Background
Currently, an ethernet link of a network device such as NVR (network hard disk recorder), a network Camera (IP Camera, IPC) is generally composed of three parts, i.e., a central processing unit (central processing unit, CPU), a medium access control Layer (Media Access Control, MAC), and a Physical Layer (PHY). While the MAC is typically a digital circuit, the PHY contains a large number of analog devices, so the MAC is typically integrated inside the CPU, while the PHY remains outside the CPU. Signals are transmitted between the MAC and PHY through interfaces such as a media independent interface (Media Independent interface, MII), a simplified media independent interface (Reduced Media Independant Interface, RMII), a gigabit media independent interface (Gigabit Media Independant Interface, GMII), a simplified gigabit media independent interface (Reduced Gigabit Media Independant Interface, RGMII) and the like.
When designing a product, signals in an interface between the MAC and the PHY need to be configured with clock delay parameters according to the conditions of printed circuit board assembly (Printed Circuit Board Assembly, PCBA) so that the signals meet the time sequence and signal quality required by an interface protocol. However, manual measurement of different parameters requires a lot of manpower and material resources, and some platforms cannot detect signal waveforms through devices such as oscilloscopes.
In view of this, how to automatically adjust the delay parameters of the configured network interface is a technical problem to be solved.
Disclosure of Invention
The invention provides a method, a system, equipment and a storage medium for automatically configuring time delay parameters, which are used for solving the technical problem that experimental parameters configuring a network interface cannot be automatically adjusted in the prior art.
The first aspect of the present invention provides a method for automatically configuring a delay parameter, configured to set a delay duration of a timing signal in the physical layer chip, where the method includes:
sequentially sending a plurality of different delay time lengths which can be used by the physical layer chip to the physical layer chip through time-sharing time periods, so that the physical layer chip delays a time sequence signal in the physical layer chip by using the corresponding delay time length in the corresponding time period;
receiving test data sent by the physical layer chip of the medium access control layer in each time period, and recording the number of error frames generated by communication between the medium access control layer and the physical layer chip in the corresponding time period;
and setting the delay time length corresponding to the time period with the least number of error frames in all the time periods as the delay time length finally used by the physical layer chip.
Optionally, before the plurality of different delay durations usable by the physical layer chip are sequentially sent to the physical layer chip by the time period, the method further includes: and setting the time duration of the time period corresponding to each time delay time duration to be the same.
Optionally, sending the plurality of different delay durations usable by the physical layer chip to the physical layer chip sequentially according to the time period includes:
before each time period starts, the corresponding delay time length is sent to the physical layer chip through the time period until all the delay time lengths are sent; wherein at most one delay time is transmitted within the same time period.
Optionally, in each time period, receiving, by the medium access control layer, test data sent by the physical layer chip, and recording the number of error frames generated by communication between the medium access control layer and the physical layer chip in the corresponding time period, where the method includes:
receiving test data sent by the physical layer chip, and detecting a frame check sequence (a frame check sequence) for each data frame of the test data; the test data are received data when the test data transmitted by the physical layer chip reach the transmission upper limit of an interface;
when the data frame cannot be detected through the frame check sequence, determining that the data frame is an error frame;
and recording the number of all error frames in the test data received in the corresponding time period.
Optionally, performing a frame check sequence (frame check sequence) detection on each data frame of the test data includes:
detecting a frame check sequence field in each data frame, and acquiring a first cyclic redundancy check (cyclic redundancy check) result carried in the frame check sequence field;
performing cyclic redundancy check calculation on the data frame to obtain a second cyclic redundancy check calculation result, and comparing the second cyclic redundancy check calculation result with the first cyclic redundancy check result;
if the plurality of first cyclic redundancy check results are different from the second cyclic redundancy check calculation results, determining that the data frame is not detected by a frame check sequence;
and if the first cyclic redundancy check result is the same as the second cyclic redundancy check calculation result, determining that the data frame passes through the frame check sequence detection.
Optionally, the delay time corresponding to the time period with the least number of error frames in all the time periods is set as the delay time for the final use of the physical layer chip, including:
when a plurality of different delay time lengths which can be used by the physical layer chip are all sent to the physical layer chip, after all test data sent by the physical layer chip in a time period corresponding to all the delay time lengths are received, the number of error frames sent by the physical layer chip in the corresponding time period under the plurality of different delay time lengths is read;
and sequencing the different delay time lengths according to the number of the error frames, acquiring the delay time length used by the physical layer chip when the number of the error frames is minimum, and setting the delay time length as the delay time length finally used by the physical layer chip.
Optionally, the method for automatically configuring the delay parameter further includes: when the number of the error frames generated in any time period is determined to be 0 frames, determining that the corresponding delay time is the optimal delay time, directly setting the optimal delay time as the delay time finally used by the physical layer chip, and stopping sending the delay time to the physical layer chip.
In a second aspect, an embodiment of the present application provides a system for automatically configuring a delay parameter, including:
the parameter adjusting unit is used for sequentially sending a plurality of different delay time lengths which can be used by the physical layer chip to the physical layer chip through the time-sharing period, so that the physical layer chip delays a time sequence signal in the physical layer chip by using the corresponding delay time length in the corresponding time period;
the data processing unit is used for receiving test data sent by the physical layer chip through the medium access control layer in each time period and recording the number of error frames generated by communication between the medium access control layer and the physical layer chip in the corresponding time period;
and the parameter determining unit is used for setting the delay time length corresponding to the time period with the least number of error frames in all the time periods as the delay time length finally used by the physical layer chip.
Optionally, the parameter adjustment unit is further configured to:
and setting the time duration of the time period corresponding to each time delay time duration to be the same.
Optionally, the parameter adjustment unit is further configured to:
before each time period starts, the corresponding delay time length is sent to the physical layer chip through the time period until all the delay time lengths are sent; wherein at most one delay time is transmitted within the same time period.
Optionally, the data processing unit is further configured to:
receiving the transmitted test data of the physical layer chip, and detecting a frame test sequence for each data frame of the test data;
when the data frame cannot be detected through the frame check sequence, determining that the data frame is an error frame;
and recording the number of all error frames in the test data received in the corresponding time period.
Optionally, the data processing unit is further configured to:
detecting a frame check sequence field in each data frame, and acquiring a first cyclic redundancy check result carried in the frame check sequence field;
performing cyclic redundancy check calculation on the data frame to obtain a second cyclic redundancy check calculation result, and comparing the second cyclic redundancy check calculation result with the first cyclic redundancy check result;
if the plurality of first cyclic redundancy check results are different from the second cyclic redundancy check calculation results, determining that the data frame is not detected by a frame check sequence;
and if the first cyclic redundancy check result is the same as the second cyclic redundancy check calculation result, determining that the data frame passes through the frame check sequence detection.
Optionally, the parameter determining unit is further configured to:
when a plurality of different delay time lengths which can be used by the physical layer chip are all sent to the physical layer chip, after all test data sent by the physical layer chip in a time period corresponding to all the delay time lengths are received, the number of error frames sent by the physical layer chip in the corresponding time period under the plurality of different delay time lengths is read;
sequencing the different delay time lengths according to the number of error frames to obtain the delay time length used by the physical layer chip when the number of error frames is minimum;
and setting the delay time length as the delay time length of the final use of the physical layer chip.
Optionally, the parameter determining unit is further configured to:
when the number of the error frames generated in any time period is determined to be 0 frames, determining that the corresponding delay time is the optimal delay time, directly setting the optimal delay time as the delay time finally used by the physical layer chip, and stopping sending the delay time to the physical layer chip.
In a third aspect, an embodiment of the present application provides a system for automatically configuring a delay parameter, including:
a device under test for performing the method as described in the first aspect.
The pressure testing device is connected with the device to be tested through a network cable and is used for providing testing data for the device to be tested and achieving the maximum bandwidth of the current network.
In a fourth aspect, an embodiment of the present application provides an apparatus for automatically configuring a delay parameter, including: a central processor having a medium access control layer chip embodied thereon, the central processor further configured to perform the method of the first aspect;
the medium access control layer chip is connected with the physical layer chip through a first interface and transmits data;
the physical layer chip is used for receiving network data.
The technical scheme in the embodiment of the invention has the following beneficial effects: the CPU of the device to be tested sequentially sends a plurality of different delay time lengths which can be used by the physical layer chip to the physical layer chip through time intervals, so that the physical layer chip delays a time sequence signal in the physical layer chip by using the corresponding delay time length in the corresponding time interval. Then, the CPU of the device under test receives the test data sent by the physical layer chip in each time period, and records the number of error frames generated by communication between the medium access control layer and the physical layer chip in the corresponding time period. And finally, setting the delay time corresponding to the time period with the least number of error frames generated in all the time periods by the CPU of the device to be tested as the delay time finally used by the physical layer chip. The device to be tested can test and select the delay time with the best signal effect sent by the physical layer chip as the delay time for final use. The loss of manpower and material resources required by manually measuring the signal quality under different time delay parameters is reduced, so that the network interface between the medium access control layer and the physical layer can always perform signal transmission with the optimal network effect.
Drawings
FIG. 1 is a flow chart of a method for automatically configuring delay parameters according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a system for automatically configuring delay parameters according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of an automatic configuration of delay parameters provided by the implementation of the present invention;
fig. 4 is a schematic diagram of a structure of a MAC frame according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a record of error frame data according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of an automatic delay parameter configuration system according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of another system for automatically configuring delay parameters according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of an apparatus for automatically configuring delay parameters according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application.
In the prior art, since the printed circuit board assembly (Printed Circuit Board Assembly, PCBA) of different products is often different, in order to ensure that signals in an interface between a medium access control Layer (medium access control, MAC) and a Physical Layer (PHY) meet the requirements of an interface protocol, a technician often manually measures signal quality of signals in an interface between the MAC and the PHY under different parameters through an oscilloscope or other devices, and determines whether the interface protocol is met, but the method needs to consume a lot of manpower and material resources. And on some platforms, such as a CPU platform like hessian, the clock signal and the data signal are sent in alignment, the technician cannot directly measure the delay parameters of the signal through an oscilloscope.
Therefore, the invention provides a method, a system, equipment and a computer storage medium for automatically configuring delay parameters, which are used for solving the technical problem that the delay parameters of a configured network interface cannot be automatically adjusted in the prior art.
The following describes the technical scheme provided by the embodiment of the application with reference to the attached drawings.
Referring to fig. 1, the present invention provides a method for automatically configuring delay parameters, which is applied to a central processing unit (central processing unit, CPU) of a device to be tested, referring to fig. 2, fig. 2 is a schematic structural diagram of a system for automatically configuring delay parameters, and the specific flow of the method is described as follows:
step 101, a plurality of different delay time lengths which can be used by the physical layer chip are sequentially sent to the physical layer chip according to time periods through the second interface, so that the physical layer chip delays a time sequence signal in the physical layer chip by using the corresponding delay time length in the corresponding time period.
Step 102, receiving test data sent by the physical layer chip in each time period, and recording the number of error frames generated by communication between the medium access control layer and the physical layer chip in the corresponding time period.
And 103, setting the delay time length corresponding to the time period with the least number of error frames generated in all the time periods as the delay time length finally used by the physical layer chip.
Wherein, can use a plurality of different time delay duration with physical layer chip, before the time slot is sent to physical layer chip in proper order, still include: and setting the time length of the time period corresponding to each time delay time length to be the same.
Wherein, a plurality of different time delay duration that can use the physical layer chip, the time period of time is sent to the physical layer chip in proper order, includes: before each time period starts, the corresponding delay time is sent to the physical layer chip until all delay time is sent; wherein at most one delay time is transmitted within the same time period.
For example, referring to fig. 3, fig. 3 is a schematic diagram of an automatic configuration of delay parameters according to an embodiment of the present invention. Fig. 3 includes a device under test and a test device, where the device under test and the test device are connected to each other by a network cable, and the device under test further includes a Physical Layer (PHY) chip, where the PHY chip is connected to a medium access control Layer (medium access control, MAC) in a central processing unit (central processing unit, CPU) through a first interface to receive data, and the CPU is connected to the PHY chip through a second interface to enable the CPU to set a delay time of a timing signal in the PHY chip. The device to be tested can be network devices such as network video recorder (Network Video Recorder, NVR), network CAMERA (IP CAMERA), various embedded systems, and the like, and the test deviceThe device may be a personal computer, a server, or other computer device. The device under test comprises a CPU301 and a PHY chip 3021, signals are transmitted between the MAC3011 in the CPU301 and the PHY chip 3021 through a media independent interface (Media Independent interface, MII), and the CPU301 also transmits signals through an integrated circuit bus (Inter-Integrated Circuit, I) 2 C) The delay time length used when the PHT chip 3021 transmits signals through the MII interface is set. The CPU301 further includes an error frame register 3012 for recording the number of error frames generated by communication between the MAC3011 and the PHY chip 3021.
Assuming that the test device continuously transmits test data to the PHY chip 3021 of the device under test through the network cable, the PHY chip 3021 of the device under test transmits the test data to the MAC3011 in the CPU301 through the MII interface, and at this time, the signal transmitted through the MII interface has reached an upper limit, and the duration of the period set by the CPU301 is 10min. Three delay durations are available for the PHY chip, 1ns, 2ns, and 3ns, respectively.
CPU301 goes through I 2 The C-bus transmits the first available delay time of the PHY chip 3021 to the PHY chip 3021 for 1ns, and the PHY chip 3021 transmits data to the MAC3011 for 10 minutes using the delay time of 1 ns. In the corresponding first 10min period, the CPU301 detects that 6 erroneous data frames have occurred in the data transmitted from the PHY chip 3021 to the MAC 3011. When the first 10min ends, CPU301 passes I 2 The C bus transmits the second available delay time of the PHY chip 3021 to the PHY chip 3021 for 2ns, and the PHY chip 3021 transmits 10min of data to the MAC3011 using the delay time of 2 ns. In the corresponding second 10min period, the CPU detects 3 erroneous data frames. When the second 10min ends, CPU301 goes through I 2 The C-bus transmits the third available delay time of the PHY chip 3021 to the PHY chip 3021 for 3ns, and the PHY chip 3021 transmits 10min of data to the MAC3011 using the delay time of 3ns. In the corresponding third 10min period, the CPU detects that 9 error frames are received in the data transmitted from the PHY chip 3021.
When all three delay time periods are transmitted and the number of error frames generated by communication between the MAC3011 and the PHY chip 3021 in the corresponding time period is recorded, the CPU301 detects that the time period in which the generated error frame is minimum is the second time period of 10 minutes, and only 3 error frames are generated. The CPU301 sets the delay time length 2ns used in the second 10min period as the delay time length of the end use of the PHY chip 3021.
In practice, the first interface may include a media independent interface (Media Independent interface, MII), a reduced media independent interface (Reduced Media Independant Interface, RMII), a gigabit media independent interface (Gigabit Media Independant Interface, GMII), a reduced gigabit media independent interface (Reduced Gigabit Media Independant Interface, RGMII), a ten bit interface (Ten Bit Interface, TBI), a XAUI (10Gigabit Attachment Unit Interface,XAUI), and the like, and the second interface may be an integrated circuit bus (Inter-Integrated Circuit, I) 2 C) A serial peripheral interface bus (Serial Peripheral Interface, SPI) bus, etc. for the CPU to send information to the PHY chip.
In the embodiment provided by the invention, the CPU of the device to be tested sequentially transmits a plurality of different delay time lengths which can be used by the PHY chip to the PHY chip in time periods through the second interface, so that the PHY chip delays the time sequence signals in the PHY chip by using the corresponding delay time lengths in the corresponding time periods. Then, the CPU of the device under test receives the test data transmitted from the PHY chip via the MAC in each period, and records the number of error frames generated by communication between the MAC and PHY chips in the corresponding period. And finally, setting the delay time corresponding to the time period with the least number of error frames generated in all the time periods by the CPU of the device to be tested as the delay time finally used by the PHY chip. The device to be tested can automatically test and select the delay time with the best signal effect sent by the PHY chip as the delay time for final use. The loss of manpower and material resources required by manually measuring the signal quality under different time delay parameters is reduced, so that the network interfaces between the MAC layer and the PHY layer can always perform signal transmission with the best network effect.
In one possible implementation manner, in each time period, test data sent by a physical layer chip is received through a medium access control layer, and the number of error frames generated by communication between the medium access control layer and the physical layer chip in the corresponding time period is recorded, including:
receiving test data sent by a physical layer chip through a first interface, and detecting a frame check sequence for each data frame of the test data; the test data is received when the test data transmitted by the physical layer chip reaches the transmission upper limit of the first interface; when the data frame cannot be detected through the frame checking sequence, determining that the data frame is an error frame; and recording the number of all error frames in the test data received in the corresponding time period.
Wherein the frame check sequence (frame check sequence) detection is performed for each data frame of the test data, comprising: detecting a frame check sequence field in each data frame, and acquiring a first cyclic redundancy check result carried in the frame check sequence field; performing cyclic redundancy check calculation on the data frame to obtain a second cyclic redundancy check calculation result, and comparing the second cyclic redundancy check calculation result with the first cyclic redundancy check result; if the first cyclic redundancy check result is different from the second cyclic redundancy check calculation result, determining that the data frame does not pass through the frame check sequence detection; and if the first cyclic redundancy check result is the same as the second cyclic redundancy check calculation result, determining that the data frame passes through the frame check sequence detection.
For example, taking the example in fig. 3 as an example, assume that the preset period is 10min, at this time, the PHY chip 3021 has already reached the transmission upper limit of the MII interface for the test data transmitted through the MII interface, and assume that the CPU301 receives two frames of data in one period. As shown in fig. 4, fig. 4 is a schematic structural diagram of a MAC frame according to an embodiment of the present invention, where a MAC frame includes a frame header portion, a data portion, and a frame trailer portion, and the frame trailer portion includes a frame check sequence (frame check sequence, FCS).
The CPU301 of the device under test receives the test data transmitted to the MAC3011 by the PHY chip 3021 through the MII interface, and performs FCS detection for each data frame. The CPU301 performs cyclic redundancy check (Cyclic Redundancy Check, CRC) calculation on the frame header portion and the data portion in the first data frame to obtain a second CRC calculation result, the calculation result being a. At the same time, the CPU301 reads the end of frame in the data frame, where the frame check sequence is the first CRC result, and the first CRC result is a. The CPU301 compares the first CRC result and the second CRC calculation result, determines that the two results are not identical, determines that the data frame is an error frame, and fails FCS detection.
The CPU301 performs CRC calculation on the frame header portion and the data portion in the second data frame to obtain a second CRC calculation result, the calculation result being B. At the same time, the CPU301 reads the end of frame in the data frame, where the frame check sequence is the first CRC result, and the first CRC result is B. The CPU301 compares the first CRC result and the second CRC calculation result, determines that the two results are identical, and determines that the data frame passes FCS detection.
When both frames of data are subjected to FCS detection, the CPU301 of the device under test records the data of the error frame as 1 frame among the test data received in the period.
In the embodiment provided by the invention, the CPU of the device to be tested searches the error frames in the frame data by performing FCS detection on each frame data, and the number of the error frames is used as a reference for measuring the signal quality, so that the signal quality is quantized into a value which can be compared with each other, and the CPU of the device to be tested is convenient to select the delay parameter with the best signal quality.
In one possible implementation manner, the delay time corresponding to the time period with the least number of error frames generated in all the time periods is set as the delay time of the final use of the physical layer chip, which includes:
when a plurality of different delay time lengths which can be used by the physical layer chip are all sent to the physical layer chip, and all test data sent by the physical layer chip in a time period corresponding to all the delay time lengths are received, the number of error frames sent by the physical layer chip in the corresponding time period under the plurality of different delay time lengths is read; sequencing a plurality of different delay time lengths according to the number of the error frames to obtain the delay time length used by the physical layer chip when the number of the error frames is minimum; and setting the delay time length as the delay time length of the final use of the physical layer chip.
For example, taking the example in fig. 3 as an example, assume that the PHY chip 3021 has a total of 3 available latency durations, including 1ns, 2ns, and 3ns. The duration of the preset period of time set by the CPU301 of the device under test is 10min.
When the CPU301 of the device under test sends all three delay time durations to the PHY chip 3021, and records the number of error frames sent by the PHY chip 3021 in the time periods corresponding to the three delay time durations, the CPU301 of the device under test reads the number of error frames sent in the time periods corresponding to the three delay time durations. Fig. 5 is a schematic diagram of recording error frame data according to an embodiment of the present invention, as shown in fig. 5. When the delay time is set to 1ns, the PHY chip 3021 transmits test data of 10min to the MAC3011, where 6 error frames are detected; when the delay time length is set to 2ns, the PHY chip 3021 transmits test data of 10 minutes to the MAC3011, in which 3 error frames are detected; when the delay time period is set to 3ns, the PHY chip 3021 transmits test data of 10 minutes to the MAC3011, in which 9 error frames are detected. And sequencing the three delay time lengths according to the number of the error frames detected in the corresponding time period, wherein the sequencing result is 2ns (3), 1ns (6) and 3ns (9). Therefore, when the CPU301 of the device under test minimizes the error frame (3 error frames), the delay time length 2ns used by the PHY chip 3021 is set as the delay time length used by the PHY chip 3021 finally.
In the embodiment provided by the invention, the CPU of the device to be tested sets the delay time when the error frame is the least as the delay time finally used by the PHY chip. The PHY chip can transmit data to the MAC by using the delay parameter with the best transmission effect.
In one possible implementation manner, the method for automatically configuring the delay parameter further includes: when the number of error frames generated in any time period is determined to be 0 frames, determining that the corresponding delay time is the optimal delay time, directly setting the optimal delay time as the delay time finally used by the physical layer chip, and stopping sending the delay time to the physical layer chip.
For example, taking the example in fig. 3 as an example, assume that the set period of time is 10min, and the delay time that the phy chip can use is 4, which are 1ns, 2ns, 3ns, and 4ns, respectively. The CPU301 of the device under test transmits a delay time to the PHY chip 3021 every 10 minutes, and detects an error frame in the test data transmitted by the PHY chip 3021 in a period corresponding to the delay time. The PHY chip transmits test data for 10 minutes using a delay period of 1ns in the first period, and the CPU301 records 6 error frames. The PHY chip transmits test data for 10min using a delay period of 2ns in the second period, and the CPU301 records 3 error frames. The PHY chip transmits test data for 10min using a delay period of 3ns in the third period, and the CPU301 records 0 error frames. At this time, the CPU301 determines that 3ns is the optimal delay time of the PHY chip 3021, directly sets the optimal delay time 3ns as the delay time of the PHY chip 3021 for end use, and does not transmit the delay time of 4ns to the PHY chip 3021.
In the embodiment provided by the invention, when the CPU of the device to be tested detects a certain delay time, the quality of the signal sent by the PHY chip is optimal and no error frame exists, the delay time is directly set as the delay time of the final use of the PHY chip, and the test of other delay time is stopped. The time required for testing is reduced and the computational resources are saved.
Based on the same inventive concept, the present application provides a system for automatically configuring a delay parameter, referring to fig. 6, the system for automatically configuring a delay parameter includes:
the parameter adjustment unit 601 is configured to sequentially send a plurality of different delay durations that can be used by the physical layer chip to the physical layer chip in time periods through the second interface, so that the physical layer chip delays a timing signal in the physical layer chip by using the corresponding delay duration in the corresponding time period;
a data processing unit 602, configured to receive, in each time period, test data sent by the physical layer chip via the medium access control layer, and record the number of error frames generated by communication between the medium access control layer and the physical layer chip in the corresponding time period;
the parameter determining unit 603 is configured to set, as a delay duration for the physical layer chip to be finally used, a delay duration corresponding to a time period in which the number of error frames generated is the smallest among all the time periods.
In a possible implementation manner, the parameter adjustment unit 601 is further configured to:
and setting the time length of the time period corresponding to each time delay time length to be the same.
In a possible implementation manner, the parameter adjustment unit 601 is further configured to:
before each time period starts, the corresponding delay time length is sent to the physical layer chip through the second interface until all the delay time lengths are sent; wherein at most one delay time is transmitted within the same time period.
In a possible implementation, the data processing unit 602 is further configured to:
receiving test data sent by a physical layer chip through a first interface, and detecting a frame check sequence for each data frame of the test data; when the data frame cannot be detected through the frame checking sequence, determining that the data frame is an error frame; and recording the number of all error frames in the test data received in the corresponding time period.
In a possible implementation, the data processing unit 602 is further configured to:
detecting a frame check sequence field in each data frame, and acquiring a first cyclic redundancy check result carried in the frame check sequence field; performing cyclic redundancy check calculation on the data frame to obtain a second cyclic redundancy check calculation result, and comparing the second cyclic redundancy check calculation result with the first cyclic redundancy check result; if the plurality of first cyclic redundancy check results are different from the second cyclic redundancy check calculation results, determining that the data frame does not pass the frame check sequence detection; and if the first cyclic redundancy check result is the same as the second cyclic redundancy check calculation result, determining that the data frame passes through the frame check sequence detection.
In a possible implementation manner, the parameter determining unit 603 is further configured to:
when a plurality of different delay time lengths which can be used by the physical layer chip are all sent to the physical layer chip, and all test data sent by the physical layer chip in a time period corresponding to all the delay time lengths are received, the number of error frames sent by the physical layer chip in the corresponding time period under the plurality of different delay time lengths is read; sequencing a plurality of different delay time lengths according to the number of the error frames to obtain the delay time length used by the physical layer chip when the number of the error frames is minimum; and setting the delay time length as the delay time length of the final use of the physical layer chip.
In a possible implementation manner, the parameter determining unit 603 is further configured to:
when the number of error frames generated in any time period is determined to be 0 frames, determining the corresponding delay time length to be the optimal delay time length, directly setting the optimal delay time length to be the delay time length finally used by the physical layer chip, and stopping sending the delay time length to the physical layer chip
Based on the same inventive concept, the present application provides a system for automatically configuring a delay parameter, referring to fig. 7, the system for automatically configuring a delay parameter includes:
the device under test 701 is configured to perform the method for automatically configuring delay parameters as described above.
The pressure testing device 702 is connected with the device to be tested through a network cable, and is used for providing testing data for the device to be tested and achieving the maximum bandwidth of the current network.
Based on the same inventive concept, an embodiment of the present invention provides an apparatus for automatically configuring a delay parameter, referring to fig. 8, the apparatus for automatically configuring a delay parameter includes:
a central processor 801, on which a medium access control layer chip 802 is included, the central processor being further configured to perform the method of automatically configuring latency parameters as described above;
the medium access control layer chip 802 is connected with the physical layer chip 803 through a first interface and transmits data;
the physical layer chip 803 is configured to receive network data.
It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the spirit or scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims and the equivalents thereof, the present application is intended to cover such modifications and variations.
Claims (10)
1. A method for automatically configuring delay parameters, wherein the method is applied to a central processing unit in a device to be tested, the central processing unit comprises a medium access control layer chip, the device to be tested further comprises a physical layer chip, and the method comprises:
sequentially sending a plurality of different delay time lengths which can be used by the physical layer chip to the physical layer chip according to time intervals, so that the physical layer chip configures clock delay parameters in an interface protocol used for communication between the physical layer chip and the media access control layer chip by using the corresponding delay time lengths in the corresponding time intervals;
receiving test data sent to the media access control layer chip by the physical layer chip through an interface protocol based on corresponding delay time in each time period, and recording the number of error frames generated by communication between the media access control layer chip and the physical layer chip in the corresponding time period;
and setting the delay time length corresponding to the time period with the least number of error frames in all the time periods as the delay time length finally used by the clock delay parameters of the interface protocol used by the physical layer chip.
2. The method of claim 1, wherein the plurality of different time delay durations usable by the physical layer chip are provided before the time periods are sequentially sent to the physical layer chip, further comprising:
and setting the time duration of the time period corresponding to each time delay time duration to be the same.
3. The method of claim 1, wherein sending the plurality of different time delay durations usable by the physical layer chip to the physical layer chip sequentially over time periods comprises:
before each time period starts, the corresponding delay time is sent to the physical layer chip until all the delay time is sent; wherein at most one delay time is transmitted within the same time period.
4. The method of claim 1, wherein receiving test data sent to the medium access control layer chip by an interface protocol based on a corresponding delay duration during each time period and recording a number of error frames generated by communication between the medium access control layer chip and the physical layer chip during the corresponding time period, comprises:
receiving test data sent by the physical layer chip based on an interface protocol corresponding to the delay time through the media control layer, and detecting a frame check sequence of each data frame of the test data, wherein the test data is received when the test data transmitted by the physical layer chip reaches the upper transmission limit of an interface;
when the data frame cannot be detected through the frame check sequence, determining that the data frame is an error frame;
and recording the number of all error frames in the test data received in the corresponding time period.
5. The method of claim 4, wherein performing a frame check sequence detection on each data frame of the test data comprises:
detecting a frame check sequence field in each data frame, and acquiring a first cyclic redundancy check result carried in the frame check sequence field;
performing cyclic redundancy check calculation on the data frame to obtain a second cyclic redundancy check calculation result, and comparing the second cyclic redundancy check calculation result with the first cyclic redundancy check result;
if the first cyclic redundancy check result and the second cyclic redundancy check calculation result are different, determining that the data frame is not detected by a frame check sequence;
and if the first cyclic redundancy check result is the same as the second cyclic redundancy check calculation result, determining that the data frame passes through the frame check sequence detection.
6. The method of claim 1, wherein setting a delay time corresponding to a time period in which the least number of error frames is generated among all time periods as a delay time for end use of the physical layer chip comprises:
when a plurality of different delay time lengths which can be used by the physical layer chip are all sent to the physical layer chip, after all test data sent by the physical layer chip in a time period corresponding to all the delay time lengths are received, the number of error frames sent by the physical layer chip in the corresponding time period under the plurality of different delay time lengths is read;
and sequencing the different delay time lengths according to the number of the error frames, acquiring the delay time length used by the physical layer chip when the number of the error frames is minimum, and setting the delay time length corresponding to the minimum number of the error frames as the delay time length finally used by the clock delay parameters of the interface protocol used by the physical layer chip.
7. The method as recited in claim 1, further comprising:
when the number of the error frames generated in any time period is determined to be 0 frames, determining that the corresponding delay time is the optimal delay time, directly setting the optimal delay time as the delay time finally used by the clock delay parameters of the interface protocol used by the physical layer chip, and stopping sending the delay time to the physical layer chip.
8. A system for automatically configuring delay parameters, wherein the system is applied to a central processor in a device under test, the central processor comprises a medium access control layer chip, the device under test further comprises a physical layer chip, and the system comprises:
the parameter adjusting unit is used for sequentially sending a plurality of different delay time lengths which can be used by the physical layer chip to the physical layer chip according to time intervals, so that the physical layer chip configures clock delay parameters in an interface protocol used for communication between the physical layer chip and the media access control layer chip by using the corresponding delay time length in the corresponding time interval;
the data receiving unit is used for receiving test data sent to the media access control layer chip by the physical layer chip through an interface protocol based on corresponding delay time in each time period, and recording the number of error frames generated by communication between the media access control layer chip and the physical layer chip in the corresponding time period;
and the parameter determining unit is used for setting the delay time length corresponding to the time period with the least number of error frames in all the time periods as the delay time length finally used by the clock delay parameter of the interface protocol used by the physical layer chip.
9. A system for automatically configuring delay parameters, comprising:
a device under test for performing the method of any of claims 1-7;
the pressure testing device is connected with the device to be tested through a network cable and is used for providing testing data for the device to be tested and achieving the maximum bandwidth of the current network.
10. An apparatus for automatically configuring delay parameters, comprising:
a central processor comprising a medium access control layer chip thereon, the central processor further configured to perform the method of any of claims 1-7;
the media access control layer chip is connected with the physical layer chip through a first interface and transmits data;
the physical layer chip is configured to receive network data, and transmit the received network data to the media access control layer chip through an interface protocol corresponding to the first interface.
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