CN113886054A - Interrupt processing device, chip and electronic equipment - Google Patents
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- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
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Abstract
The embodiment of the application provides an interrupt processing device, a chip and electronic equipment. The interrupt processing device is in communication connection with the interrupt source and the plurality of processor cores; the interrupt processing device receives occupation information sent by a plurality of processor cores and selects the processor core which passes through a polling arbitration mechanism firstly from the plurality of processor cores as a target processor core; and the interrupt processing device distributes the interrupt signal sent by the interrupt source to the target processor core according to the occupation information of the target processor core under the condition of meeting the configuration condition. By adopting the interrupt processing device, the interrupt signal can be sent to the target processor core through the polling arbitration mechanism and the occupation information, and then the interrupt signal is accurately distributed to the corresponding processor core.
Description
Technical Field
The present application relates to the field of interrupt processing technologies, and in particular, to an interrupt processing apparatus, a chip, and an electronic device.
Background
With the increasing integration of chips, the computing power of chips becomes one of the most important indexes for measuring SoC (System on Chip) systems, so that CPUs (Central Processing units/processors) are formally stepping into the multi-core era, and the integrated IP (Intellectual Property) on the chips is also more and more complex. Generally, the number of interrupts sent by IP is proportional to the complexity of IP, and in this case, the precise distribution between on-chip interrupts and CPU cores becomes a problem to be solved in high-performance SoC design.
Disclosure of Invention
The embodiment of the application provides an interrupt processing device, a chip and electronic equipment, which can realize accurate distribution of interrupt.
According to a first aspect of embodiments of the present application, there is provided an interrupt handling apparatus communicatively coupled to an interrupt source and a plurality of processor cores;
the interrupt processing device is used for receiving occupation information sent by a plurality of processor cores;
the interrupt processing device is also used for selecting a processor core which passes through a polling arbitration mechanism firstly from a plurality of processor cores as a target processor core;
and the interrupt processing device is also used for distributing the interrupt signal sent by the interrupt source to the target processor core according to the occupation information of the target processor core under the condition of meeting the configuration condition.
According to a second aspect of the embodiments of the present application, there is provided a chip including an interrupt source, a processor core, and the interrupt processing apparatus described above.
According to a third aspect of the embodiments of the present application, there is provided an electronic device including the chip described above.
By adopting the interrupt processing device, the chip and the electronic equipment provided by the embodiment of the application, the interrupt processing device receives occupation information sent by a plurality of processor cores and selects the processor core which firstly passes through a polling arbitration mechanism from the plurality of processor cores as a target processor core; and the interrupt processing device distributes the interrupt signal sent by the interrupt source to the target processor core according to the occupation information of the target processor core under the condition of meeting the configuration condition. Therefore, the interrupt processing device can send the interrupt signal to the target processor core through the polling arbitration mechanism and the occupation information, and further realize the accurate distribution of the interrupt signal to the corresponding processor core.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:
fig. 1 is a schematic structural diagram of a chip according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of an interrupt processing apparatus according to an embodiment of the present disclosure;
fig. 3 is a schematic circuit diagram of an interrupt distribution processing module according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Icon:
1-an electronic device; 10-a chip; 100-interrupt handling means; 110-an interrupt distribution processing module; 111-an interrupt distribution processing unit; 112-processing circuitry; 113-a selection circuit; 120-register configuration bus; 130-a distribution register; 140-mask register; 200-an interrupt source; 300-a processor core; U1-OR gate; u2-first and gate; u3-second AND gate; u4-third AND gate; d1-trigger.
Detailed Description
In the process of implementing the present application, the inventors found that, as the degree of integration of a Chip is higher and higher, the computing power of the Chip becomes the most important index for measuring an SoC (System on Chip) System, and therefore, a CPU (Central Processing Unit/Processor) formally steps into a multi-core era and an IP (Intellectual Property) integrated on the Chip is more and more complex. Generally, the number of interrupts sent by IP is proportional to the complexity of IP, and in this case, the precise distribution and real-time processing between on-chip interrupts and CPU cores become a problem to be solved in high-performance SoC design.
For example, in a 4-core SoC system (including cores 0-3, 4 cores), the total number of interrupts is 10 (interrupts 0-9), and if the core2 needs to monopolize the interrupt 5, the interrupt can only be received by the core2, but cannot be sent to the core0, the core1, and the core 3. Then conventional interrupt processing distribution logic cannot guarantee the exclusivity of a core to an interrupt in such a scenario.
In view of the above problems, an embodiment of the present application provides an interrupt processing apparatus, a chip, and an electronic device, where the interrupt processing apparatus receives occupation information sent by a target processor core; the target processor core is the processor core which passes through a polling arbitration mechanism of the interrupt processing device firstly in the plurality of processor cores; and the interrupt processing device distributes the interrupt signal sent by the interrupt source to the target processor core according to the number of the target processor core under the condition of meeting the configuration condition. Therefore, the interrupt processing device can send the interrupt signal to the target processor core through the polling arbitration mechanism and the occupation information, and further realize the accurate distribution of the interrupt signal to the corresponding processor core.
In order to make the technical solutions and advantages of the embodiments of the present application more apparent, the following further detailed description of the exemplary embodiments of the present application with reference to the accompanying drawings makes it clear that the described embodiments are only a part of the embodiments of the present application, and are not exhaustive of all embodiments. It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict.
Referring to fig. 1, a schematic structural diagram of a chip 10 according to an embodiment of the present disclosure is shown, where the chip 10 includes an interrupt source 200, a plurality of processor cores 300, and an interrupt processing apparatus 100, and the interrupt processing apparatus 100 is communicatively connected to both the interrupt source 200 and the plurality of processor cores 300.
The interrupt processing device 100 is used for receiving occupation information sent by a plurality of processor cores; the interrupt processing apparatus 100 is further configured to select the processor core 300 that first passes through the round robin arbitration mechanism from the plurality of processor cores 300 as a target processor core; the interrupt processing apparatus 100 is further configured to distribute an interrupt signal sent by the interrupt source 200 to a target processor core according to occupation information of the target processor core when a configuration condition is satisfied.
It should be understood that the interrupt mechanism is that the processor core 300 suddenly interrupts another request during the sequential execution of the program instruction stream to suspend the current program, and then goes to do something else, waits for it to do something else, and then returns to the point of the previous program interrupt to continue executing the previous program instruction stream. The "other request" that interrupts the execution of the program instruction stream by processor core 300 is referred to as an Interrupt signal, and the Source of the "other request" is referred to as Interrupt Source 200 (Interrupt Source). Interrupt sources 200 typically come from several complex IPs integrated within the SoC. The "other things" that the processor core 300 goes to handle is called an ISR (Interrupt Service Routing).
In this embodiment, the interrupt processing apparatus 100 is further configured to select, as the target processor core, the processor core 300 that first transmits the occupation information to the interrupt processing apparatus 100 from among the plurality of processor cores 300, or select, as the target processor core, the processor core 300 having the highest priority from among the plurality of processor cores 300.
That is, each of the plurality of processor cores 300 transmits the occupation information to the interrupt processing device 100, and the interrupt processing device 100 selects, from the plurality of processor cores 300, the processor core 300 to which the occupation information is transmitted first or the processor core 300 having the highest priority as the target processor core, and responds only to the occupation information of the target processor core.
As shown in fig. 2, the interrupt processing apparatus 100 includes a register configuration bus 120, a distribution register 130, a mask register 140, and an interrupt distribution processing module 110, wherein the register configuration bus 120 is communicatively connected to the distribution register 130, the mask register 140, the interrupt distribution processing module 110, and the processor core 300, and the interrupt distribution processing module 110 is communicatively connected to the mask register 140, the distribution register 130, the processor core 300, and the interrupt source 200.
The number of the distribution registers 130 and the number of the mask registers 140 are the same as the number of the types of the interrupt signals generated by the interrupt sources 200, the distribution registers 130 and the mask registers 140 are respectively arranged in one-to-one correspondence with the types of the interrupt signals generated by the interrupt sources 200, and the bit widths of the distribution registers 130 and the mask registers 140 are consistent with the number of the processor cores 300.
It should be appreciated that if chip 10 has m processor cores 300, interrupt source 200 generates n interrupt signals; then, n distribution registers 130 and n mask registers 140 are correspondingly arranged, the interrupt signal 0 is arranged corresponding to the distribution register 0 and the mask register 0, the interrupt signal 1 is arranged corresponding to the distribution register 1 and the mask register 1, and so on, the interrupt signal n-1 is arranged corresponding to the distribution register n-1 and the mask register n-1, of course, a person skilled in the art can set the corresponding relationship between the interrupt signal and the distribution register 130 according to the actual situation, and the method is not limited herein; the distribution register 130 and the mask register 140, which are correspondingly arranged, are responsible for managing the corresponding interrupt signals, i.e. the distribution register 1 and the mask register 1 determine whether the interrupt signal 1 needs to be distributed to a certain processor core or cores 300.
The bit width of the distribution register 130 and the mask register 140 is consistent with the number of the processor cores 300, that is, the bit width of the distribution register 130 and the mask register 140 is set to m bits, and one bit of the distribution register 130 and the mask register 140 corresponds to one processor core 300; bits 0 of the dispatch register 130 and the mask register 140 correspond to processor core0, bits 1 of the dispatch register 130 and the mask register 140 correspond to processor core1, and so on, bits m-1 of the dispatch register 130 and the mask register 140 correspond to processor core m-1. By setting the bits of the dispatch register 130 and the mask register 140, the dispatch of the interrupt signal to one or more of the processor cores 300 may be controlled. For example, if it is desired to dispatch interrupt signal 1 to processor core2, and to dispatch register 1 and mask register 140 at position 2, then interrupt signal 1 will be dispatched to processor core 2; if it is required to distribute the interrupt signal 1 to the processor cores 1 and 3, the 1 st and 3 rd bits of the distribution register 1 are both set to 1, and the 1 st and 3 rd bits of the mask register 1 are both set to 1, the interrupt signal 1 is distributed to the processor cores 1 and 3.
In this embodiment, the possession information includes configuration information and a number of the target processor core; the register configuration bus 120 is used for writing the number sent by the target processor core into the target mask register and the interrupt distribution processing module 110; the target masker is a mask register 140 correspondingly set for an interrupt signal currently generated by the interrupt source 200; register configuration bus 120 is also used to write configuration information to the target distribution register; wherein, the target distribution register is the distribution register 130 correspondingly set by the interrupt signal currently generated by the interrupt source 200; the target distribution register is configured to generate a distribution signal according to the configuration information, and send the distribution signal to the interrupt distribution processing module 110; the mask register 140 is configured to generate a mask signal according to the number of the target processor core, and send the mask signal to the interrupt distribution processing module 110; the interrupt distribution processing module 110 is configured to distribute the interrupt signal currently generated by the interrupt source 200 to the target processor core according to the distribution signal, the mask signal, and the number of the target processor core.
It should be understood that a certain processor core 300 is preset to obtain a target mask register address and a target dispatch register address according to the attribute information of the interrupt signal, and send the target mask register address and the target dispatch register address to the register configuration bus 120. The register configuration bus 120 writes the number of the target processor core into the target mask register according to the target mask register address, and the register configuration bus 120 also writes the configuration information into the target distribution register according to the target distribution register address. The attribute information of the interrupt signal includes a correspondence relationship between the interrupt signal and the mask register 140 and the distribution register 130.
The mask register 140 is in a configurable state, that is, the mask register 140 is in a state of all 1, and the number of the target processor core can only be written into the mask register 140 at all positions 1 of the mask register 140. After the number of the target processor core is written into the mask register 140, the numbers of the other processor cores 300 cannot be written into the mask register 140; if the mask register 140 is reset or the target processor core releases the mask register 140, the mask register 140 is restored to the state of all 1; the target processor core performs the release operation on the mask register 140, which may be understood as that the target processor core writes release information, which may be information of all the positions 1 of the mask register 140, to the corresponding mask register 140 through the register configuration bus 120.
In this embodiment, the processor core 300 may obtain the status information of the mask register 140 in real time through the register configuration bus 120, when the state that the mask register 140 is not all 1 is obtained, the processor core 300 obtains the number written in the mask register 140 through the register configuration bus 120, the processor core 300 compares the number in the mask register 140 with its own number, if the numbers are different, it is known that the interrupt is already occupied by another processor core 300 at this time, until the mask register 140 recovers to the all 1 state, the other processor cores 300 compete for the ownership of the interrupt signal through the polling arbitration mechanism.
As shown in fig. 3, the interrupt distribution processing module 110 includes interrupt distribution processing units 111, and the number of the interrupt distribution processing units 111 is the product of the number of processor cores 300 and the number of interrupt signals generated by the interrupt source 200.
Each processor core 300 is in communication connection with a preset number of interrupt distribution processing units 111, and the preset number is consistent with the number of interrupt signals generated by the interrupt sources 200; the interrupt distribution processing unit 111 connected to each processor core 300 is in one-to-one communication connection with the distribution register 130 and the mask register 140, and the interrupt distribution processing unit 111 is in communication connection with both the interrupt source 200 and the register configuration bus 120.
It should be understood that if there are n interrupt signals, m processor cores 300, the interrupt distribution processing unit 111 is correspondingly configured with n × m. Wherein, each processor core 300 is correspondingly connected with n interrupt distribution processing units 111, and the interrupt distribution processing units 111 connected with each processor core 300 are different. The n interrupt distribution processing units 111 connected to each processor core 300 are in one-to-one communication connection with the n distribution registers 130 and the n mask registers 140, and the interrupt distribution processing units 111 corresponding to different processor cores 300 correspond to different bits of the n distribution registers 130 and the n mask registers 140.
With continued reference to FIG. 3, each interrupt distribution processing unit 111 includes a processing circuit 112 and a selection circuit 113, the processing circuit 112 being communicatively coupled to each of the register configuration bus 120, the mask register 140, and the selection circuit 113, the selection circuit 113 being communicatively coupled to each of the interrupt source 200, the distribution register 130, and the processor core 300.
As shown in fig. 3, the processing circuit 112 includes an or gate U1, a first and gate U2, and a flip-flop D1, wherein a first input terminal of the or gate U1 is electrically connected to an output terminal of the flip-flop D1, a second input terminal of the or gate U1 is electrically connected to both the register configuration bus 120 and a data terminal of the flip-flop D1, an output terminal of the or gate U1 is electrically connected to a first input terminal of the first and gate U2, a second input terminal of the first and gate U2 is communicatively connected to the mask register 140, an output terminal of the first and gate U2 is electrically connected to an enable terminal of the flip-flop D1, and an output terminal of the flip-flop D1 is electrically connected to the selection circuit 113.
The selection circuit 113 comprises a second and gate U3 and a third and gate U4, a first input of the second and gate U3 being communicatively connected to the distribution register 130, a second input of the second and gate U3 being communicatively connected to the interrupt source 200, an output of the second and gate U3 being electrically connected to a second input of the third and gate U4, a first input of the third and gate U4 being electrically connected to the processing circuit 112, an output of the third and gate U4 being communicatively connected to the processor core 300.
Wherein the processing circuit 112 and the selection circuit 113 of each interrupt distribution processing unit 111 have the same circuit configuration. That is, each processing circuit 112 includes an or gate U1, a first and gate U2, and a flip-flop D1, and each selection circuit 113 includes a second and gate U3 and a third and gate U4.
It should be understood that SoC _ INT 0-SoC _ INTn-1 in FIG. 3 are n interrupt signals generated by interrupt source 200, core 0-core-1 is m processor cores 300, ICB _ BUS is register configuration BUS 120, ICB _ WDATA is the number of a target processor core, and is the m distribution signals generated by n distribution registers 130, and is the output signals of n flip-flops D1, wherein, C _ INT0_ indicator [ m-1:0] to C _ INT-1 _ indicator [ m-1:0] is the m distribution signals generated by n distribution registers 130, ICB _ SEL _ INT0_ MASK [ m-1:0] to ICB _ SEL _ INTn-1_ MASK [ m-1:0] is the m MASK signals generated by n MASK registers 140, and C _ INT0_ MASK [ m-1:0] to SoC _ INTn-1_ MASK [ m-1:0] is the output signals of n flip-flops D38.
In a certain application scenario of the chip 10, if the interrupt source 200 currently generates the interrupt signal 0, i.e. the SoC _ INT 0; if the chip 10 has just been reset at this time, the mask register 140 is in the all-1 state. The m processor cores 300 all send occupation information to the register configuration bus 120, and the register configuration bus 120 determines that the processor core0 is the target processor core according to the priority of the processor cores 300 or the sequence of sending the occupation information by the processor cores 300. The occupation information sent by the processor core0 comprises configuration information and the number thereof, and the configuration information and the number of the processor core0 can be decimal number 0; if the processor core1 is a target processor core, the configuration information and the number of the processor core can be decimal number 1; if processor core 300m is the target processor core, its configuration information and number may be a decimal number m. Meanwhile, one of the processor cores 300 obtains the attribute information of the interrupt signal 0 from the interrupt source 200, obtains a target distribution register address and a target mask register address according to the attribute information of the interrupt signal 0, and sends the target distribution register address and the target mask register address to the register configuration bus 120; since the distribution register 130 and the mask register 140 are set in one-to-one correspondence with the interrupt signal, the distribution register 130 and the mask register 140 set in correspondence with the interrupt signal 0 are the distribution register 0 and the mask register 0; then the dispatch register 0 is the target dispatch register and the mask register 0 is the target mask register. The register configuration bus 120 writes the configuration information of the processor core0 into the distribution register 0, and writes the number of the processor core0 into the mask register 0.
The distribution register 0 generates m distribution signals soc _ int0_ indicator [ m-1:0] based on the configuration information of the processor core0, the distribution information is respectively sent to first input ends of m second and gates U3, second input ends of the m second and gates U3 all receive the interrupt signal 0, output ends of the m second and gates U3 are electrically connected with second input ends of m third and gates U4, output ends of the m third and gates U4 are in one-to-one correspondence communication connection with the m processor cores 300, first input ends of the m third and gates U4 are electrically connected with output ends of m flip-flops D1, data ends of the m flip-flops D1 receive the number of the processor core0, the number of the processor core0 is converted into a binary system, and the data ends of the m flip-flops D1 receive a certain binary system number of the processor core 0; the enable terminals of the m flip-flops D1 are electrically connected to the output terminals of the m first and gates U2.
The MASK register 0 generates m MASK signals ICB _ SEL _ INT0_ MASK [ m-1:0] based on the number of the processor core0, and transmits the MASK signals to second input terminals of the m first and gates U2, respectively.
Since the configuration information and number of processor core0 is decimal 0, then mask register 0 and distribute register 0 to position 0, rest of positions 0. Correspondingly, the distribution signal soc _ INT0_ indicator0 and the MASK signal ICB _ SEL _ INT0_ MASK0 are at high level, and the remaining m-1 distribution signals and MASK signals are at low level. Therefore, the interrupt distribution processing unit 111 connected to the processor core0 distributes the interrupt signal 0 to the processor core0, the output terminal of the or gate U1 in the interrupt distribution processing unit 111 outputs a high level, the first and gate U2, the second and gate U3 and the third and gate U4 all output a high level, and the output terminal of the flip-flop D1 also outputs a high level correspondingly.
In the present embodiment, as shown in fig. 4, the present application further provides an electronic device 1, where the electronic device 1 includes a chip 10. The electronic device 1 may be a mobile phone, a computer, a wearable device, or the like.
In summary, the present application provides an interrupt processing apparatus, a chip, and an electronic device, where the interrupt processing apparatus receives occupation information sent by a plurality of processor cores, and selects a processor core that first passes through a polling arbitration mechanism from the plurality of processor cores as a target processor core; and the interrupt processing device distributes the interrupt signal sent by the interrupt source to the target processor core according to the occupation information of the target processor core under the condition of meeting the configuration condition. Therefore, the interrupt processing device can send the interrupt signal to the target processor core through the polling arbitration mechanism and the occupation information, and further realize the accurate distribution of the interrupt signal to the corresponding processor core.
While the preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all alterations and modifications as fall within the scope of the application.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.
Claims (10)
1. An interrupt handling apparatus, wherein the interrupt handling apparatus is communicatively coupled to an interrupt source and a plurality of processor cores;
the interrupt processing device is used for receiving occupation information sent by a plurality of processor cores;
the interrupt processing device is also used for selecting a processor core which passes through a polling arbitration mechanism firstly from a plurality of processor cores as a target processor core;
and the interrupt processing device is also used for distributing the interrupt signal sent by the interrupt source to the target processor core according to the occupation information of the target processor core under the condition of meeting the configuration condition.
2. The interrupt processing apparatus of claim 1, wherein the occupancy information includes configuration information and a number of the target processor core, the interrupt processing apparatus including a register configuration bus communicatively coupled to the dispatch register, the mask register, the interrupt distribution processing module and the processor core, a dispatch register, a mask register, and an interrupt distribution processing module communicatively coupled to the mask register, the dispatch register, the processor core and the interrupt source;
the number of the distribution registers and the number of the shielding registers are the same as the number of interrupt signal types generated by the interrupt sources, the distribution registers and the shielding registers are respectively arranged in one-to-one correspondence with the interrupt signal types generated by the interrupt sources, and the bit widths of the distribution registers and the shielding registers are consistent with the number of the processor cores;
the register configuration bus is used for writing the number sent by the target processor core into a target shielding register and the interrupt distribution processing module; the target masker is a mask register which is correspondingly arranged for an interrupt signal currently generated by the interrupt source;
the register configuration bus is also used for writing the configuration information into a target distribution register; the target distribution register is a distribution register which is correspondingly set for an interrupt signal currently generated by the interrupt source;
the target distribution register is used for generating a distribution signal according to the configuration information and sending the distribution signal to the interrupt distribution processing module;
the target shielding register is used for generating a shielding signal according to the number of the target processor core and sending the shielding signal to the interrupt distribution processing module;
the interrupt distribution processing module is used for distributing the interrupt signal currently generated by the interrupt source to the target processor core according to the distribution signal, the shielding signal and the number of the target processor core.
3. The interrupt processing apparatus according to claim 2, wherein the interrupt distribution processing module includes interrupt distribution processing units, the number of the interrupt distribution processing units being a product of the number of the processor cores and the number of interrupt signals generated by the interrupt source;
each processor core is in communication connection with a preset number of interrupt distribution processing units, and the preset number is consistent with the number of interrupt signals generated by the interrupt sources; and the interrupt distribution processing unit connected with each processor core is in one-to-one corresponding communication connection with the distribution register and the shielding register, and the interrupt distribution processing unit is in communication connection with the interrupt source and the register configuration bus.
4. The interrupt handling apparatus of claim 3, wherein each of the interrupt distribution processing units comprises a processing circuit communicatively coupled to the register configuration bus, the mask register and the selection circuit, and a selection circuit communicatively coupled to the interrupt source, the distribution register and the processor core.
5. The interrupt processing apparatus of claim 4, wherein the processing circuit comprises an OR gate, a first AND gate, and a flip-flop, wherein a first input of the OR gate is electrically connected to an output of the flip-flop, a second input of the OR gate is electrically connected to both the register configuration bus and a data terminal of the flip-flop, an output of the OR gate is electrically connected to the first input of the first AND gate, a second input of the first AND gate is communicatively connected to the mask register, an output of the first AND gate is electrically connected to an enable terminal of the flip-flop, and an output of the flip-flop is further electrically connected to the selection circuit.
6. The interrupt processing apparatus of claim 4, wherein the selection circuit comprises a second AND gate and a third AND gate, a first input of the second AND gate being communicatively coupled to the dispatch register, a second input of the second AND gate being communicatively coupled to the interrupt source, an output of the second AND gate being electrically coupled to a second input of the third AND gate, a first input of the third AND gate being electrically coupled to the processing circuit, an output of the third AND gate being communicatively coupled to the processor core.
7. The interrupt handling apparatus of claim 2, wherein the configuration condition is the mask register being in a configurable state.
8. The interrupt processing apparatus according to claim 1, wherein the interrupt processing apparatus is further configured to select, as the target processor core, a processor core that first transmits the occupation information to the interrupt processing apparatus from among the plurality of processor cores, or select, as the target processor core, a processor core having a highest priority from among the plurality of processor cores.
9. A chip comprising an interrupt source, a plurality of processor cores and the interrupt handling apparatus of any of claims 1 to 8.
10. An electronic device comprising the chip of claim 9.
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| PCT/CN2022/121645 WO2023098259A1 (en) | 2021-12-03 | 2022-09-27 | Interrupt processing apparatus, chip, and electronic device |
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| WO2023098259A1 (en) * | 2021-12-03 | 2023-06-08 | 芯来科技(武汉)有限公司 | Interrupt processing apparatus, chip, and electronic device |
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| CN110457243A (en) * | 2019-07-30 | 2019-11-15 | 西安理工大学 | A kind of expansible multi output interrupt control unit |
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| CN113886054B (en) * | 2021-12-03 | 2022-04-15 | 芯来科技(武汉)有限公司 | Interrupt processing device, chip and electronic equipment |
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- 2021-12-03 CN CN202111460925.0A patent/CN113886054B/en active Active
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| CN101128807A (en) * | 2005-03-28 | 2008-02-20 | 微软公司 | Systems and methods for an augmented interrupt controller and synthetic interrupt sources |
| CN101236541A (en) * | 2008-03-03 | 2008-08-06 | 北京中星微电子有限公司 | Centralized control interrupt controller and its interrupt control method |
| US20100262742A1 (en) * | 2009-04-14 | 2010-10-14 | Andrew Wolfe | Interrupt Arbitration For Multiprocessors |
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| CN102855156A (en) * | 2011-06-30 | 2013-01-02 | 重庆重邮信科通信技术有限公司 | Interrupt controller and interrupt controlling method |
| US20140013021A1 (en) * | 2012-01-27 | 2014-01-09 | Tops Systems Corporation | Processor core and multi-core processor system |
| CN109376000A (en) * | 2018-10-24 | 2019-02-22 | 胡振波 | Quick-speed interruption control system and method for RISC-V framework |
| CN110457243A (en) * | 2019-07-30 | 2019-11-15 | 西安理工大学 | A kind of expansible multi output interrupt control unit |
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| WO2023098259A1 (en) * | 2021-12-03 | 2023-06-08 | 芯来科技(武汉)有限公司 | Interrupt processing apparatus, chip, and electronic device |
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| WO2023098259A1 (en) | 2023-06-08 |
| CN113886054B (en) | 2022-04-15 |
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