CN113885686B - Power management device, edge computing device, and edge computing system - Google Patents
Power management device, edge computing device, and edge computing system Download PDFInfo
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- CN113885686B CN113885686B CN202110970459.4A CN202110970459A CN113885686B CN 113885686 B CN113885686 B CN 113885686B CN 202110970459 A CN202110970459 A CN 202110970459A CN 113885686 B CN113885686 B CN 113885686B
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- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/266—Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
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Abstract
Embodiments of the present disclosure relate to a power management apparatus, an edge computing apparatus, and an edge computing system, the power management apparatus including: each power management unit comprises a mode change-over switch, a power supply loading circuit, a power receiving and separating circuit, a power line and a network transmission line; the mode change-over switch is used for selectively switching on the power supply loading circuit and the power line or switching on the power receiving power supply separating circuit and the power line according to the working mode; the power supply loading circuit is used for loading direct current transmitted from the power line onto the network transmission line; the power receiving power separation circuit is used for separating direct current transmitted from a network transmission line to a power line, and the network transmission line is connected with the edge computing device. Therefore, the power supply management equipment can be utilized to strip the power supply and power receiving functions from the edge computing equipment, the power supply and power receiving functions are independently deployed and flexibly adapted, and the problems of over-design, poor configuration flexibility and high cost can be solved.
Description
Technical Field
The present disclosure relates to the field of edge computing technologies, and in particular, to a power management device, an edge computing device, and an edge computing system.
Background
The edge calculation, also called distributed calculation, fog calculation or multilateral calculation, has the main advantages that integration, analysis and calculation feedback of mass equipment data can be completed at a data acquisition end or a system edge end. The edge computing can save communication bandwidth, reduce network delay, reduce data traffic, improve system security and confidentiality, rely less on storage and computing power resources, and can improve the reliability and control power of edge devices. The edge calculation may be performed in an edge computing device. Illustratively, edge computing devices include smart sensors, programmable logic controllers, edge smart routers, and information communication technology (Information Communications Technology, ICT) convergence gateways, among other devices that can locally implement data processing.
Active ethernet (Power Over Ethernet, POE) refers to a technology that can provide direct current to edge computing devices while transmitting data signals for some IP-based terminals (e.g., IP phones, wireless local area network access points AP, webcams, etc.) without any modification to the existing ethernet cat.5 wiring infrastructure.
In the prior art, requirements for POE in the deployment process of the edge computing Device are different, and according to deployment scenarios, POE deployment scenarios of non-POE deployment, power supply devices (Power Sourcing Equipment, PSE) and Power Devices (PD) exist, and integrating PSE or PD functions inside the edge computing Device can cause over-design of a system side, poor configuration flexibility of PSE and PD, and additional cost.
Disclosure of Invention
To solve or at least partially solve the above technical problems, embodiments of the present disclosure provide a power management device, an edge computing device, and an edge computing system.
In a first aspect, embodiments of the present disclosure provide a power management apparatus, including at least one power management unit, each of the power management units including a mode switch, a power supply loading circuit, a power receiving power separating circuit, a power line, and a network transmission line;
the mode switching switch is used for selectively conducting the power supply loading circuit and the power line or conducting the power receiving power supply separating circuit and the power line according to a working mode;
the power supply loading circuit is used for loading direct current transmitted from the power line onto the network transmission line;
the power receiving power supply separation circuit is used for separating direct current transmitted from the network transmission line to the power supply line;
the network transmission line is connected with the edge computing device.
In a second aspect, an embodiment of the present disclosure further provides an edge computing device, where the edge computing device is connected to a power management device, and the edge computing device includes a core board and a substrate, where an edge computing function chip is disposed on the core board, and a signal transmission interface is disposed on the substrate, and the edge computing function chip on the core board is connected to the signal transmission interface on the substrate through at least one connector;
The signal transmission interface comprises a network signal interface, and the network signal interface is connected with a network transmission line.
In a third aspect, embodiments of the present disclosure also provide an edge computing system, comprising: the power management device of any one of the embodiments of the present disclosure, and the edge computing device of any one of the embodiments of the present disclosure.
Compared with the prior art, the technical scheme provided by the embodiment of the disclosure has at least the following advantages: in an embodiment of the present disclosure, a power management apparatus includes at least one power management unit, each power management unit including a mode change-over switch, a power supply loading circuit, a power receiving power separating circuit, a power line, and a network transmission line; the power supply loading circuit is used for loading direct current transmitted from the power supply line onto the network transmission line, at the moment, the network transmission line can be used for transmitting the direct current, and the edge computing equipment configuring the power management equipment can be used as PSE at the moment and can supply power for the later-stage equipment connected with the power management equipment; or the mode switching switch can selectively conduct the power receiving power supply separation circuit and the power supply line according to the working mode, and the power receiving power supply separation circuit is used for separating the direct current transmitted from the network transmission line to the power supply line, at the moment, the direct current is separated from the network transmission line and transmitted to the power receiving equipment through the power supply line, so that power supply for the power receiving equipment can be realized. Therefore, through the arrangement of the power management equipment, the coupling and separation of direct current and a network transmission line can be realized, and the power supply and receiving functions can be stripped from the edge computing equipment at the system side, and are independently deployed and flexibly configured, so that PSE or PD functions are not required to be integrated in the edge computing equipment, over-design at the system side is avoided, and the problems of poor configuration flexibility and extra cost of PSE and PD are improved.
Drawings
The above and other features, advantages, and aspects of embodiments of the present disclosure will become more apparent by reference to the following detailed description when taken in conjunction with the accompanying drawings. The same or similar reference numbers will be used throughout the drawings to refer to the same or like elements. It should be understood that the figures are schematic and that elements and components are not necessarily drawn to scale.
Fig. 1 is a schematic structural diagram of a power management device according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of another power management device according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of still another power management device according to an embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of still another power management device according to an embodiment of the present disclosure;
fig. 5 is a schematic structural diagram of a cascade connection of four power management units according to an embodiment of the disclosure;
fig. 6 is a schematic structural diagram of a single power management unit according to an embodiment of the disclosure;
FIG. 7 is a schematic diagram of an edge computing device according to an embodiment of the present disclosure;
fig. 8 is a schematic structural diagram of a core board according to an embodiment of the present disclosure;
FIG. 9 is a schematic structural view of another core board provided by an embodiment of the present disclosure;
Fig. 10 is a schematic diagram of a corresponding connection relationship between a core board and a substrate according to an embodiment of the disclosure;
fig. 11 is a schematic structural view of a connector according to an embodiment of the present disclosure;
fig. 12 is a schematic view of a terminal arrangement of a connector according to an embodiment of the present disclosure;
FIG. 13 is a schematic cross-sectional view of the core plate shown in FIG. 9 taken along line A1-A2;
fig. 14 is a schematic view of a partial planar structure of another core board provided in an embodiment of the present disclosure.
Detailed Description
Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present disclosure have been shown in the accompanying drawings, it is to be understood that the present disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are for illustration purposes only and are not intended to limit the scope of the present disclosure.
It should be understood that the various steps recited in the method embodiments of the present disclosure may be performed in a different order and/or performed in parallel. Furthermore, method embodiments may include additional steps and/or omit performing the illustrated steps. The scope of the present disclosure is not limited in this respect.
The term "including" and variations thereof as used herein are intended to be open-ended, i.e., including, but not limited to. The term "based on" is based at least in part on. The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments. Related definitions of other terms will be given in the description below.
It should be noted that the terms "first," "second," and the like in this disclosure are merely used to distinguish between different devices, modules, or units and are not used to define an order or interdependence of functions performed by the devices, modules, or units.
It should be noted that references to "one", "a plurality" and "a plurality" in this disclosure are intended to be illustrative rather than limiting, and those of ordinary skill in the art will appreciate that "one or more" is intended to be understood as "one or more" unless the context clearly indicates otherwise.
Before explaining the power management device, the edge computing device, and the edge computing system provided by the embodiments of the present disclosure, terms that may be involved in the embodiments of the present disclosure are explained.
POE: power Over Ethernet, active ethernet, refers to a technology that, under existing ethernet infrastructure, is capable of providing dc power to such devices while transmitting data signals (i.e., network signals) for some IP-based terminals.
PSE: power Sourcing Equipment, power supply equipment, equipment for supplying power to other terminal equipment.
PD: power Device, power receiving Device, device that accepts other terminal equipment Power supply.
ECM: edge Computing Module the edge calculation module, the core board is used for providing different calculation forces, supporting the SoC operation core and connecting the substrate through the connector.
EBB: edge Computing Baseboad edge computing substrate, substrate for connecting to the core plate.
The power management device provided by the disclosure can be configured in a system network, for example, can be configured at an edge computing device side to realize power supply/power receiving. The power management device comprises at least one power management unit, wherein each power management unit comprises a mode change-over switch, a power supply loading circuit, a power receiving and separating circuit, a power line and a network transmission line; the power supply loading circuit is used for loading direct current transmitted from the power supply line onto the network transmission line, at the moment, the network transmission line can be used for transmitting the direct current, and the edge computing equipment configuring the power management equipment can be used as PSE at the moment and can supply power for the later-stage equipment connected with the power management equipment; or the mode switching switch can selectively conduct the power receiving power supply separation circuit and the power line according to the working mode, and the power receiving power supply separation circuit is used for separating the direct current transmitted from the network transmission line to the power line, at the moment, the direct current is separated from the network transmission line, and the direct current can be transmitted to the power receiving equipment through the power line, so that power supply for the power receiving equipment connected with the power line can be realized. Therefore, through the arrangement of the power management equipment connected with the edge computing equipment through the network transmission line, the coupling and the separation of direct current and the network transmission line can be realized, and the power supply and receiving functions can be stripped from the edge computing equipment at the system side, are independently deployed and flexibly configured, so that PSE or PD functions are not required to be integrated in the edge computing equipment, over-design at the system side is avoided, and the problems of poor configuration flexibility and extra cost of PSE and PD are improved. Further, the multi-path power management unit is cascaded, so that the high-power supply/receiving requirements can be met.
As shown in fig. 1, a power management apparatus 10 provided by an embodiment of the present disclosure may include: at least one power management unit 20, each power management unit 20 including a mode changeover switch 21, a power supply loading circuit 22, a power receiving power supply separation circuit 23, a power line 24, and a network transmission line 25;
a mode switch 21 for selectively switching on the power supply loading circuit 22 and the power line 24 or switching on the power receiving power supply separating circuit 23 and the power line 24 according to the operation mode;
the power supply loading circuit 22 is used for loading direct current transmitted from the power line 24 onto the network transmission line 25;
the power receiving power supply separation circuit 23 is used for separating the direct current transmitted from the network transmission line 25 to the power supply line 24;
the network transmission line 25 is connected to the edge computing device.
In the embodiment of the present disclosure, the mode changeover switch 21 can select a circuit that is conductive with the power line 24 according to the operation mode. Specifically, when the operation mode is the power supply mode, that is, the terminal device of the power management device is configured as the power supply device, the mode switch 21 selectively turns on the power supply loading circuit 22 and the power line 24, and the power supply loading circuit 22 loads the direct current transmitted from the power line 24 onto the network transmission line 25, so as to supply power to the subsequent device by using the network transmission line 25. When the operation mode is the power receiving mode, that is, when the terminal device of the power management device is configured as the power receiving device, the mode switch 21 selectively turns on the power receiving power separating circuit 23 and the power line 24, the power receiving power separating circuit 23 separates the direct current transmitted from the network transmission line 25 onto the power line 24, and the terminal device can be electrically connected with the power line 24 to realize power receiving.
Therefore, through the mode switch 21 in the power management unit 20, coupling and separation of direct current and network transmission lines can be realized, and power supply and power receiving functions can be stripped from a system side (refer to a system for transmitting network signals, which can be called a network system), and are independently deployed and flexibly configured, so that PSE or PD functions are not required to be integrated inside an edge computing device, over-design of the system side is avoided, and the problems of poor configuration flexibility and extra cost of PSE and PD are improved.
It can be appreciated that when the direct current is applied to the network transmission line, the network transmission line may be used to transmit the direct current only, or the network transmission line may be used to transmit the direct current and the network signal simultaneously; that is, the network signal and the direct current can be transmitted by adopting the same network transmission line, or can be transmitted by adopting different network transmission lines; correspondingly, a signal line power supply mode can be adopted, and an idle line power supply mode can also be adopted. Illustratively, corresponding to the signal line power mode, the PSE transmits direct current while transmitting data to the PD using the wire pairs (1, 2, 3, 6) for transmitting data in the class 3/5 twisted pair; corresponding to the idle line power mode, the PSE uses pairs (4, 5, 7, 8) of the 3/5 twisted pair that are not used for data transmission to transmit dc power to the PD, which may be set based on the transmission requirements of the network signals and dc power, without limitation.
It will be appreciated that the power management device 10 is shown in fig. 1 as including one power management unit 20 by way of example only, and is not limiting of the power management device 10 provided by embodiments of the present disclosure. In other embodiments, the number of the power management units 20 may be two, three or more, which is not limited herein, and will be exemplified hereinafter. Loading direct current transmitted from the power line 24 onto the network transmission line 25
The power management apparatus 10 provided in the embodiment of the present disclosure includes at least one power management unit 20, and the mode switch 21 in the power management unit 20 can select to turn on the power line 24 and the power supply loading circuit 22 or to turn on the power line 24 and the power receiving power separation circuit 23 according to the operation mode; meanwhile, the power supply loading circuit 22 can load the direct current transmitted from the power line 24 onto the network transmission line 25, the power receiving power separating circuit 23 can separate the direct current transmitted from the network transmission line 25 onto the power line 24, and the power receiving power separating circuit can integrate PSE and PD, can be used as power receiving equipment or power supply equipment, and can be switched by using the mode switching switch 21; meanwhile, the PSE and PD design can be stripped from the network system, and the power management device 10 can be deployed independently without being limited by the network system by switching the circuit connected with the power line 24 through the mode switch 21 corresponding to the working mode, and can be flexibly adapted according to POE function requirements and deployment environment based on power supply and power receiving requirements of the network system.
Based on this, in the deployment process of the edge computing device, for example, there are POE deployment scenarios of non-POE deployment, power supply device and powered device, where the PSE and PD functions may be configured and implemented by the power management device 10, instead of integrating the PSE and PD functions in the edge computing device, so as to avoid over-designing the network system and further avoid paying extra cost. That is, the POE function can be stripped from the network system and independently implemented by the power management device 10, and the power management device 10 integrates PSE and PD designs, so as to be suitable for a plurality of different scenarios.
Thus, the embodiments of the present disclosure propose a solution for integrating power supply and power reception for POE power supply and power reception devices, which integrates power supply and power reception in the same power management device 10, and can be deployed in combination with serial products of edge computing devices. For example, the power management device 10 is suitable for a scenario in which a terminal device does not have a POE function or is not certain to be used as a power supply device or a power receiving device, but the associated device depends on POE deployment, and flexible adaptation is performed according to power supply and power receiving requirements.
In an alternative embodiment of the present disclosure, as shown in fig. 2, the power supply loading circuit 22 includes:
A boost sub-circuit 221 for boosting the direct current of the first voltage transmitted on the power line 24 into the direct current of the second voltage, the value of the second voltage being greater than the value of the first voltage;
the loading subcircuit 222 is configured to load the direct current of the second voltage onto the network transmission line 25.
In the disclosed embodiment, the booster sub-circuit 221 can make the output voltage higher than the input voltage. Specifically, the input voltage is a first voltage transmitted on the power line 24, and the output voltage is a second voltage; the first voltage is converted into a second voltage after being boosted by the boosting sub-circuit 221; the value of the second voltage is greater than the value of the first voltage.
Illustratively, the boost sub-circuit 221 is capable of boosting 12V dc power to 48V dc power; correspondingly, and the loading subcircuit 222 is used to load 48 vdc onto the network transmission line 25.
It will be appreciated that the foregoing is only exemplified by the first voltage being 12V and the second voltage being 48V, i.e. the boost sub-circuit 221 may boost the output voltage by 4 times the input voltage, but is not limited to the embodiments of the present disclosure. In other embodiments, the boosting capability of the boosting sub-circuit 221 may be set based on the power supply demand and the first voltage transmitted on the power line 24, which is not limited herein.
Illustratively, the boost sub-circuit 221 may be a switch dc boost circuit such as a boost circuit or other dc boost circuits, which are not described herein in detail.
Similarly, any loading circuit capable of loading direct current onto the network transmission line 25 may be used as the loading sub-circuit 222, and the description is omitted herein.
In the embodiment of the disclosure, the power supply loading circuit 22 includes a boost sub-circuit 221 and a loading sub-circuit 222, where the boost sub-circuit is configured to boost the direct current of the first voltage transmitted on the power line 24 into the direct current of the second voltage, and the loading sub-circuit is configured to load the direct current of the second voltage onto the network transmission line 25, so that the direct current transmitted on the power line 24 can be boosted based on the power supply requirement of the power supply device, that is, the power requirement of the electric equipment connected with the power supply device, based on the power requirement, so that the direct current loaded on the network transmission line 25 is the direct current with the second voltage, and the second voltage is greater than the first voltage, thereby being beneficial to meeting the power requirement of the electric equipment with larger power.
In an alternative embodiment of the present disclosure, as shown in fig. 3, the power receiving source separation circuit 23 includes:
A separation sub-circuit 231 for separating the direct current of the third voltage from the network transmission line 25;
the step-down sub-circuit 232 is configured to step down the dc power of the third voltage to the dc power of a fourth voltage, where the value of the fourth voltage is smaller than the value of the third voltage.
In the disclosed embodiment, the dc current is a dc current signal with a fixed voltage value, and the data signal is usually an analog signal or a digital signal, which is a regular, programmed, information-bearing electrical signal. Based on this, the dc power can be distinguished from the data signal, for which the separation circuit 231 is designed to separate the dc power of the third voltage from the network transmission line 25.
In the disclosed embodiment, the buck sub-circuit 232 is capable of making the output voltage lower than the input voltage. Specifically, the input voltage is a third voltage, the output voltage is a fourth voltage, and the dc power of the third voltage is converted into the fourth voltage after passing through the step-down sub-circuit 232, where the value of the fourth voltage is smaller than the value of the third voltage.
Illustratively, the step-down subcircuit 232 is capable of step-down the dc power of the other value of the third voltage separated from the power transmission line 25 by the separation subcircuit 231 to 12V dc power and powering a terminal device, such as an edge computing device, through the power line 24.
It will be appreciated that the foregoing is merely illustrative of the fourth voltage of 12V, and is not meant to limit the embodiments of the present disclosure. In other embodiments, the step-down capability of the step-down subcircuit 232 may be set based on the power requirements and the third voltage of the direct current separated from the network transmission line 24, which is not limited herein.
Illustratively, the step-down subcircuit 232 may employ a switched dc step-down circuit or other dc step-down circuits, which are not described in detail herein.
Similarly, any separation circuit capable of separating dc power from the network transmission line 25 may be used as the separation sub-circuit 231, and the description is omitted herein.
In the embodiment of the present disclosure, the power receiving source separation circuit 23 includes a separation sub-circuit 231 and a step-down sub-circuit 232 by being provided; the separation sub-circuit 231 is used for separating the direct current of the third voltage from the network transmission line 25; the step-down sub-circuit 232 is configured to step down the dc power of the third voltage to the dc power of the fourth voltage, where the value of the fourth voltage is smaller than the value of the third voltage, and on the basis that the dc power can be separated from the network transmission line 25 by the power receiving power separation circuit 23, the separated dc power can be step down based on the power consumption requirement of the power receiving device, so that the voltage of the dc power is reduced from the third voltage to the fourth voltage, thereby being beneficial to meeting the power consumption requirement of a terminal device with smaller power, such as an edge computing device.
In an alternative embodiment of the present disclosure, as shown in fig. 4 or 5, the number of the power management units 20 is at least two, and the power lines 24 of the at least two power management units 20 are electrically connected to serve as a common power output terminal, each power management unit 20 further includes:
the load balancing circuit 26 is arranged in series with the power receiving supply separation circuit 23;
and, the load balancing circuit 26 between the different power management units 20 is electrically connected to balance the load between at least two power management units 20.
In the embodiment of the present disclosure, the power lines 24 of at least two power management units 20 are electrically connected in a sequential plugging manner, and the connection ends of the power lines 24 are shown in fig. 5. The power cord 24 may be a dc power cord, and the connection ends may include a male head 241 and a female head 242, where when the connection ends are sequentially plugged, the male head 241 is sequentially inserted into the female head 242 forward, and fig. 5 shows the male head 241 with a broken line, which is not visible outside after plugging; wherein each female 242 implements a cascade connection between the power management units 20, and the male 241 supplies power to the powered device. The male head 241 may also be referred to as a DC output terminal, i.e., DC Jack output; the female 242 may also be referred to as a direct current input terminal, i.e., a DC Jack input, the male 241 and female 242 forming a set of DC Jack terminals. Wherein, DC jack all stands for direct current jack, or is called direct current jack.
In the embodiment of the disclosure, the load balancing circuit 26 is disposed in the power management unit 20 and is disposed in series with the power receiving power separating circuit 23, and is used for accessing the direct current separated by the power receiving power separating circuit 23 from the network transmission line 25; and the load balancing circuit 26 between the different power management units 20 is electrically connected to balance the load between the power management units 20, so that the common power output end can output stable direct current which meets the power consumption requirement. Illustratively, in FIG. 4, load balancing circuit 26 is required to balance two paths of direct current in parallel; in fig. 6, the load balancing circuit 26 needs to balance four paths of direct currents in parallel, for example, to adjust output currents corresponding to different direct currents.
Illustratively, the load balancing circuit 26 may include a power converter, a regulating amplifier, and a PWM controller connected in a cyclic sequence, with the non-inverting inputs of the regulating amplifiers of the load balancing circuit 26 connected between different power management units 20 and connected to a shared bus; the adjusting amplifier is used for adjusting current amplification factor, the PWM controller is used for controlling the duty ratio of the voltage signal, the power converter is used for realizing conversion of voltage, current and corresponding power, and based on parameters transmitted on the shared bus, more accurate load balancing is realized; the direct current is input by the power converter and finally output by the power converter after load balancing.
It can be appreciated that the load balancing circuit 26 may also adopt other circuit structures capable of implementing load balancing, which are not described herein in detail and are not limited thereto.
In the embodiment of the present disclosure, by setting the number of the power management units 20 to at least two, the power lines 24 of at least two power management units 20 are electrically connected to serve as the common power output terminal, each power management unit 20 further includes: the load balancing circuit 26 is arranged in series with the power receiving supply separation circuit 23; and, the load balancing circuit 26 between the different power management units 20 is electrically connected to balance the load between at least two power management units 20; while the power supply and power receiving functions can be integrated by using the power management apparatus 10, two or more power management units 20 can be set according to different power supply/power consumption requirements, and load balancing between the power management units 20 is achieved by using the load balancing circuit 26 in the power management units 20, so that the common power supply output end of at least two power management units 20 can output stable direct current which meets the power consumption requirements.
It can be understood that the data of the power management unit 20 is only exemplarily shown as two in fig. 4, and the number of the power management units 20 is only exemplarily shown as four in fig. 6. In other embodiments, the number of power management units 20 may also be three, five, or more; the load balancing circuits between the different power management units 20 are electrically connected in sequence to correspondingly achieve balancing between three or more power management units 20.
In an alternative embodiment of the present disclosure, as shown in fig. 5 or 6, each power management unit 20 is encapsulated in a housing 200, and a first opening 201 through which a network transmission line 25 passes, a second opening 202 through which a power line 24 passes, and a third opening 203 through which a cascading probe is passed are provided on the housing 200, and the cascading probe is used to electrically connect load balancing circuits 26 between different power management units 20.
In the embodiment of the disclosure, the housing 200 can encapsulate the power management unit 20, so as to facilitate a better overall structural stability of the power management device 10. In fig. 5 and 6, the dashed lines within the housing 200 represent the external non-integral circuits and connections built into the housing 200.
In the embodiment of the disclosure, a first opening 201, a second opening 202 and a third opening 203 are provided on the housing 200; the first openings 201 are disposed on opposite sides of the housing 200 for allowing the network transmission line 25 to be connected in and out; the second opening 202 may be disposed on the same side of the housing 200 as one of the first openings 201, and the second opening 202 is used for passing the power cord 24; the third openings 203 are disposed on two adjacent sides of the housing 200, and the two adjacent sides can be used for connecting the two opposite sides where the first openings 201 are disposed, and the third openings 203 are used for passing through the cascade probes, so as to facilitate the connection between the different power management units 20.
It will be appreciated that the third openings 203 are shown in fig. 6 by way of example only as comprising two rows of four openings each, i.e. a total of 8 openings. In other embodiments, the number and arrangement of the openings of the third openings 203 may also be set based on the requirements of the power management apparatus 10, which is not limited herein.
In the embodiment of the disclosure, when the mode switch 21 is implemented by adopting a hardware structure, it may be disposed at the other side of the housing 200 and connected to the power line 24 in the housing 200, and selectively connected to the power supply loading circuit 22 or the power receiving power separating circuit 23, so as to correspondingly conduct the power line 24 and the power supply loading circuit 22, or conduct the power line 24 and the power receiving power separating circuit 23. The power supply loading circuit 22 and the power receiving power separating circuit 23 are also connected with the network transmission line 25, the power supply loading circuit 22 can load direct current onto the network transmission line 25, the power receiving power separating circuit 23 can separate direct current transmitted from the network transmission line 25 onto the power line 24, and accordingly the power management unit 20 can couple or separate direct current with the network transmission line 25.
The network transmission line 25 is also illustratively connected to a network output 252 for accessing or outputting data signals, as shown in fig. 5 or 6.
Illustratively, taking the orientation shown in fig. 5 and 6 as an example, the power management device is configured into a network system, and when the power management device operates as a PSE device, a terminal device of the network system, such as an edge computing device, may be connected to the first opening 201 on the right side of the power management device through the network signal transmission line 25, and 12V dc power is connected to the power management device through the connection terminals (including the male head 241 and the female head 242) and the power line 24. Referring to fig. 2, the 12V dc power is boosted to 48V dc power by the boost sub-circuit 221, and the load sub-circuit 222 is loaded on the network transmission line 25, and the network signal transmission line 25 electrically connected to the first opening 201 on the right side outputs the dc power to an external PD device, which may be, for example, a POE camera, a POE gate, a POE curtain, a POE charging fee collector, or a POE lighting device. At this time, the power receiving supply separation circuit 23, the load balancing circuit 26, and the cascade probe are all in an inactive state.
When the power management device is used as a PD power separation device, a terminal device of the network system, for example, an edge computing device, may be connected to the first opening 201 on the left side of the power management device, where the first opening 201 on the right side may be connected to a POE power network of the switch, that is, to a switch having a POE function; the power network of the switch POE can be connected to the power management device via a network transmission line 25, in which case the network signal transmission line 25 carries direct current. Referring to fig. 3, the dc electrical signal of the dc on the network transmission line can be separated by the separating sub-circuit 231 and converted into 12V dc by the step-down sub-circuit 232, and the 12V dc can be transmitted to the male head 241 of the connection end by the power line 24 and further connected to the edge computing device, so as to implement power receiving of the edge computing device. At this time, the power supply loading circuit 22 is in an inactive state; the cascade probes are also in an inactive state; when the power consumption of the powered edge computing equipment is large, the cascade probes are in a working state, and cascade of different power management units is realized.
Specifically, when the power management device is cascaded as a PD power separation device, as shown in fig. 6, four power management units are combined into one power management device through cascading probes, 4 DC Jack terminals are also connected through male and female connection terminals, four POE power networks are respectively and correspondingly connected to four first openings 201 on the right side, power conversion from 48V to 12V is provided through a power receiving power separation circuit and a load balancing circuit, and 12V DC output voltage is output to an edge computing device through cascading probes as load balancing.
In the embodiment of the disclosure, through cascading of four power management units, the power supply capability of the 4-path POE power supply network can be provided. Illustratively, the 8023.At standard is capable of supporting power up to 102W, which can meet the power requirements of higher power edge computing devices or other terminal devices.
In other embodiments, when the power consumption of the edge computing device is greater, a greater number of power management units may be cascaded in the power management device, which is not described herein in detail and is not limited thereto. Therefore, the power management device can be suitable for power supply/electric field scene which cannot be met by POE standards, and flexible adaptation under different electric field scenes can be realized.
In an alternative embodiment of the present disclosure, as shown in fig. 5 or 6, a network transmission line 25 connected to the edge computing device is used to transmit network signals and direct current; or a network transmission line 25 connected to the edge computing device for transmitting network signals.
In embodiments of the present disclosure, the edge computing device may integrate power on/off functionality internally, where the corresponding network transmission line 25 may transmit both network signals and direct current. Illustratively, at this point, the direct current and network signals are coupled or decoupled internally to the edge computing device; optionally, a separation circuit for separating the direct current and the network signal is arranged inside the edge computing device, and the circuit structure of the separation circuit can be the same as that of a power receiving power supply separation circuit in the power management device, or other circuit structures known to those skilled in the art are adopted, so that the separation circuit is not limited herein; optionally, a loading circuit for coupling direct current and network signals is disposed inside the edge computing device, and the circuit structure of the loading circuit may be the same as that of the power supply loading circuit in the power management device, or other circuit structures known to those skilled in the art may be adopted, which is not limited herein.
Alternatively, when the power receiving function is integrated in the edge computing device and the network transmission line 25 only transmits the network signal, the power management device 10 may be used to load the local direct current onto the network signal transmission line 25, and then connect the network transmission line 25 with the edge computing device. Thus, by configuring the power management device 10, the need for an edge computing device to receive both network signals and direct current power simultaneously using only one signal transmission port can be met.
Alternatively, when the power receiving function is not integrated in the edge computing device, but the network transmission line 25 transmits the network signal and the direct current at the same time, the power management device 10 may be used to separate the network signal and the power signal, and transmit the network signal to the edge computing device through the network transmission line 25 connected to the edge computing device, and power the edge computing device through another power line connected to the edge computing device, where two transmission ports for receiving the network signal and the direct current respectively are provided corresponding to the edge computing device.
Alternatively, when the power supply function is not integrated in the edge computing device, but the network transmission line 25 transmits the network signal and the direct current at the same time, the power management device 10 may be used to couple the direct current to the network transmission line 25, and then the synchronous transmission of the network signal and the direct current is continued.
In the embodiment of the disclosure, by setting to separate or couple the network signal and the direct current by using the power management device, the PSE and the PD can be integrated, so that the PSE and the PD can be used as power receiving devices or power supply devices, and only the mode change-over switch 21 in the power management device 10 is required to switch the working modes; meanwhile, the PSE and PD design can be stripped from the network system, and the power management device 10 can be deployed independently without being limited by the network system by switching the circuit connected with the power line 24 through the mode switch 21 corresponding to the working mode, and can be flexibly adapted according to POE function requirements and deployment environment based on power supply and power receiving requirements of the network system.
The embodiment of the disclosure also provides edge computing equipment, which comprises a signal transmission interface through arranging a substrate, wherein an edge computing functional chip on a core board is connected with the signal transmission interface on the substrate through at least one connector, so that the core board connected with the substrate can be replaced, the edge computing equipment can meet the diversified demands of various service lines on demands of CPU computing force, AI computing force, low-delay network interconnection, industrial interfaces and the like in an edge computing scene, and the solution provided for meeting the demands of computing force elastic upgrade and the like. Namely, the edge computing equipment provided by the embodiment of the disclosure can be transversely compatible with various solutions by arranging the peelable connection between the core board and the substrate, meets the diversified requirements of business on computing force and configuration, and can optimize the cost; the method can meet the calculation force lifting requirement longitudinally, and is convenient for upgrading and iterating the solution.
As shown in fig. 7, the edge computing device provided in the embodiment of the disclosure includes a core board 40 and a substrate 30, where an edge computing function chip 41 is disposed on the core board 40, a signal transmission interface 300 is disposed on the substrate 30, and the edge computing function chip 41 on the core board 40 is connected with the signal transmission interface 300 on the substrate 30 through at least one connector 42; the signal transmission interface 300 includes a network signal interface that interfaces with a network transmission line to enable connection of an edge computing device and a power management device.
In the embodiment of the present disclosure, the edge calculation function chip 41 can implement an edge calculation function, such as a billing function, an image recognition function, a lighting function, a temperature control function, or other functions in an edge scene, which is not limited herein.
By way of example, the edge computation function Chip 41 may include at least one of Intel Keemmbay, cambricon NPU, rockwell Chip RK family, high pass, xilinx, flat Widget, and X86 CPU System on Chip (SoC). Correspondingly, the core board 40 may be compatible to support implementation of a variety of different edge computing functions.
In the embodiment of the present disclosure, at least one connector 42 is further disposed on the core board 40 provided with the edge computing function chip 41, for implementing connection with the signal transmission interface 300 of the substrate 30. Thus, the modular core board 40 in the edge computing device corresponds to a modular design, with the modular core board 40 achieving a releasable connection to the substrate 30 through standardized terminals (also referred to as "interfaces") in the connector 42.
The demands for the edge computing function chip 41 on the core board 40 are greatly different due to the different computing forces required in different edge computing scenarios. In view of this, by connecting the connector 42 on the core board 40 with the signal transmission interface 300 on the substrate 30 in a pluggable manner, the core board 40 meeting the calculation force requirements can be connected with the substrate 30, thereby meeting the calculation force requirements in different edge calculation scenarios.
In the embodiment of the disclosure, the substrate 30 is directly connected to an external device, such as at least one of a camera, an audio acquisition device and other data acquisition devices, in addition to the core board 40, and may be configured based on a scene suitable for the edge computing device, which is not limited herein.
In an alternative embodiment of the present disclosure, at least one connector 42 may include a main connector 421, as shown in fig. 7, the main connector 421 being fixed to an edge of the core board 40; further, the at least one connector 42 may further include an auxiliary connector 422, as shown in fig. 8, the auxiliary connector 422 being fixed to an edge of the core board 40; also, the auxiliary connector 422 and the main connector 421 may be fixed at two different edges of the core board 40.
In other embodiments, at least one connector 42 may also include only auxiliary connectors 422, with the auxiliary connectors 422 being secured to the edges of the core board 40.
In the embodiment of the present disclosure, only the main connector 421 may be disposed at the edge of the core board 40, and the number and functions of the terminals thereof are provided, as will be described later; when the terminals of the main connector 421 are not used enough, the auxiliary connector 422 may be further added. For example, terminals corresponding to functions of primary interest may be provided in the main connector 421 and terminals corresponding to other extended functions or auxiliary functions may be provided in the auxiliary connector 422. Alternatively, the main connector 421 and the auxiliary connector 422 may be different from each other, and may be used for example, for nursing object status, related module information identification, health status, connection status, and the like.
In an alternative embodiment of the present disclosure, as shown in fig. 10, the core functions of the core board 40 are to support the SOC operation core, and the built-in main functions may include:
1) A display output function, correspondingly, a general man-machine interface can be provided;
2) Network functions, such as providing 2-way network connectivity;
3) A high-speed serial computer expansion bus standard (Peripheral Component Interconnect express, PCIe) bus, for example, a PCIe3.0 x 4 channel bus, may support connection of components such as a 5G network, storage, AI acceleration, etc.;
4) Universal serial bus (Universal Serial Bus, USB) functions, such as providing a universal human-machine interface;
5) Other IO functions, correspondingly, provide audio input/output interfaces;
6) The bus interface is controlled to support controller area network (Controller Area Network, CAN), RS232 and RS485 functions.
In an alternative embodiment of the present disclosure, as shown in fig. 10 and 11, each of the signal transmission interfaces may be provided corresponding to each of the terminals in the connector 42; as shown in fig. 11, the connector 42 includes at least one of a USB signal terminal, a CAN bus signal terminal, a high definition multimedia (High Definition Multimedia Interface, HDMI) interface signal terminal, a camera serial interface (Camera Serial Interface, CSI) signal terminal, a joint test effort group (Joint Test Action Group, JTAG) signal terminal, an ethernet signal terminal, an audio signal terminal, an artificial intelligence (Artificial Intelligence, AI) module signal terminal, a memory signal terminal (i.e., a memory card signal terminal), a mobile communication signal terminal, a serial peripheral interface (Serial Peripheral Interface, SPI) signal terminal, a serial communication bus signal terminal, and a power supply terminal.
Correspondingly, the interfaces in the signal transmission interface may include at least one of a USB signal interface, a CAN bus signal interface, an HDMI interface signal interface, a CSI signal interface, a JTAG signal interface, an ethernet signal interface, an audio signal interface, an AI module signal interface, a memory card signal interface, a mobile communication signal interface, an SPI signal interface, a serial communication bus signal interface, and a power interface. Referring to fig. 9 and 11, the connector 42 may be the main connector 421 or the auxiliary connector 422.
In an embodiment of the disclosure, referring to fig. 10, the USB signal interface may include a USB3.0 signal interface and a USB2.0 signal interface for transmitting a universal serial signal; the CAN bus signal interface CAN be simply called as a CAN interface, and CAN also comprise a CAN interface 2 for transmitting CAN bus signals; the HDMI interface signal interface can be called as HDMI interface for transmitting HDMI signal; the CSI signal interface is used for transmitting CSI signals, the JTAG signal interface is used for transmitting JTAG signals, the Ethernet signal interface may include a Gigabit Ethernet (GE) network interface 1 and a GE network interface 2 for transmitting Ethernet signals, and the audio signal interface may also be referred to as an audio input output interface for transmitting audio signals; the AI module signal interface comprises a first M.2AI module slot and a second M.2AI module slot, the memory signal interface can be a Micro SD card slot, the mobile communication signal interface is used for transmitting mobile communication signals, the SPI signal interface is used for transmitting SPI signals, the serial communication bus signal interface can comprise an RS485 interface and an RS232 interface, and the power interface can be a direct current interface.
Therefore, the core board 40 and the substrate 30 may be interconnected by using an interconnection interface with standardized design, the substrate 30 supports power access, video input/output, audio input/output, network access, USB access, 4G/5G module (e.g. m.2 interface), global navigation satellite system (Global Navigation Satellite System, GNSS) (e.g. beidou system is designed on the substrate), network processor (Neural-network Processing Units, NPU) accelerator card (e.g. Dual m.2), and the like, and may support Single m.2 x 2, solid State Disk (Solid State Disk or Solid State Drive, SSD) storage (e.g. m.2), debug interface (e.g. JTAG), and other functions related to edge computation.
Exemplary, the signal terminals of the main connector 421 and the outgoing signals thereof are shown in table 1.
TABLE 1A terminal signal meter of main connector
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Exemplary, signal terminals and their outgoing signals for the auxiliary connector 422 are shown in table 2.
Table 2A terminal signal meter of auxiliary connector
In an alternative embodiment of the present disclosure, the core board may support two sizes, and in particular, only the main connector is provided, i.e. the core board with a single connector has a size of 76mmx50mm; simultaneously arranging a main connector and an auxiliary connector, namely, the size of a core board with double connectors is 76mmx110mm; the core plate may have a thickness of 1.05mm and a weight of 300g.
In an alternative embodiment of the present disclosure, the core board supports two high speed connectors to connect signals to the substrate, the connectors may employ a Molex Mirror Mezz series 2063060537, with a bond height of 5mm high, with the specifications shown in table 3.
Table 3 high speed connector specification
| Project | Description of the invention |
| Model number | 2063060537 |
| Pin count | 169 |
| Rate of speed | 56GNRZ/112GPAM4 |
| Single pin through-current capability | 1A |
| Weight of (E) | TBD g |
In an alternative embodiment of the present disclosure, as shown in fig. 12, each pin (i.e., terminal) in the connector 42 is shown at 420, and the connector 42 includes 169 defined terminals 420 in total, and is arranged in 5 columns, with the number of terminals 420 in the middle row being 37, and the number of terminals 420 in each of the remaining 4 rows being 33 (i.e., 37-4), so that there are 169 terminals in total, i.e., 37 x 5-4 x 4 = 169.
Based on this arrangement, the pin definitions of the main connector are shown in table 4, by way of example.
TABLE 4 Pin definition of Main connector
The definition of the pins shown in the table 4 can cover the requirements of the edge service interface, and can realize the functions of automatic identification and in-place detection; specifically, the pin design may employ a mode of a primary connector in combination with a secondary connector, the primary connector pins satisfying the capability of independent use.
The definition of each pin in table 4 is described as follows according to the sequence of "signal name signal meaning, functional description signal flow (I/O/IO) ||channel voltage (Pwr Rail) |ecm pull-down and whether other processing|remarks are required for processing a condition|load (Carrier)":
P3V 3I ECM board 3.3V power supply I3.3V NA I not;
P5V I5V NA I does not exist for power supply of the ECM board 5V;
p3v3_stby|ecm panel 3.3Vstandby power i|3.3 v|na|na|none;
GND I/NA is zero with reference to the ground;
USB2_# 0_DN|micro USB2 port 0, and data negative electrode|I/O|3.3V|NA|NA| is distributed to an external Micro USB OTG port;
USB 2_0_DP|micro USB2 port 0, and data positive electrode|I/O|3.3V|NA|NA| is distributed to an external Micro USB OTG port;
USB2_ # 2_DN|USB 2 port 2, data negative electrode|I/O|3.3V|NA|NA| is reserved, and if the carrier plate is directly connected with an external USB port, a protection device is required to be added according to the port requirement;
USB2_ # 2_DP|USB 2 port 2, data positive electrode|I/O|3.3V|NA|is reserved, and if the carrier plate is directly connected with an external USB port, a protection device is required to be added according to port requirements;
USB2_# 3_DN|USB 2 port 3, data negative electrode|I/O|3.3V|NA|NA| is reserved, and if the carrier plate is directly connected with an external USB port, a protection device is required to be added according to the port requirement;
USB 2_3_DP|USB 2 port 3, data positive electrode|I/O|3.3V|NA|is reserved, and if the carrier plate is directly connected with an external USB port, a protection device is required to be added according to port requirements;
USB3_ #3_RX_DN||USB3 port 3, superSpeed receiving negative pole the AC coupling capacitance of the AC coupled NA is reserved, if the carrier plate is directly connected with the external USB port, a protection device is required to be added according to the port requirement;
USB 3- #3_RX_DP I USB3 port 3, superSpeed receives the positive pole I AC coupled NA I AC coupling capacitance reservation, if the carrier plate is directly connected with the external USB port, a protection device is required to be added according to the port requirement;
USB3_ # 3_TX_DN|USB 3 port 3, superSpeed sends negative pole|O|AC coupled|AC coupling capacitance|NA||reservation, if the carrier plate is directly connected to an external USB port, a protection device is required to be added according to port requirements;
The method comprises the steps that a transmitting end of a CAN0 controller with the level of CAN0 is provided with a carrier CAN transceiver with the level of CAN 0O 3.3V NA, and reservation termination matching is recommended between the controller and the transceiver, and 120 omega matching is suggested between the rear ends of the transceiver and CANH;
the method comprises the steps that a receiving end of a CAN0 controller with the value of CAN 0I 3.3V NA I is given to a carrier CAN transceiver, reservation termination matching is recommended between the controller and the transceiver, and 120 omega matching is recommended between the rear end of the transceiver and CANH and CANL;
ecm_watchdog WATCHDOG feeding signal O3.3V NA reservation;
USB2_ #0_VBUS Micro-USB VBUS voltage detection 5V NA no;
the reserved end of the HDMI_CLK_DN is matched with the end of the HDMI CLK signal differential signal negative electrode O1.8V and NA is not;
the reserved end of the HDMI_CLK_DP I HDMI CLK signal differential signal anode O1.8V I is matched with NA I;
the reserved end of the HDMI_DATA1_DP I HDMI signal differential signal 1 is matched with the negative electrode O1.8V I, and the NA I does not exist;
the reserved end of the HDMI_DATA1_DN I HDMI signal differential signal 1 is matched with the I NA I;
the reserved end of the HDMI_DATA2_DP I HDMI signal differential signal 2 is matched with the end of the HDMI signal, and the end of the HDMI signal differential signal 2 is matched with the end of the HDMI signal, namely the end of the HDMI signal differential signal is matched with the end of the HDMI signal;
the reserved end of the HDMI_DATA2_DN I HDMI signal differential signal 2 is matched with the NA I;
the reserved end of the differential signal 0 negative pole O1.8V of the HDMI_DATA0_DP I HDMI signal is matched with NA I;
The reserved end of the HDMI_DATA0_DN I HDMI signal differential signal 0 is matched with the NA I;
the negative electrode of the MDI 0-1 differential pair 0 can negotiate 10/100/1000M I/O3.3V NA to connect an isolation transformer to the gigabit network port 1 of the carrier plate;
MDI 0-1 MDI1 differential pair 0 positive pole, can consult 10/100/1000M I/O3.3V NA to connect isolation transformer to carrier plate giga net port 1;
the negative electrode of the MDI1 differential pair 1 is 1 +_1MI/O3.3V and NA can be negotiated to connect the isolation transformer to the gigabit network port 1 of the carrier plate;
MDI 1-1 MDI1 differential pair 1 positive pole, can consult 10/100/1000M I/O3.3V NA to connect isolation transformer to carrier plate giga net port 1;
MDI2+ 1 MDI1 differential pair 2 negative, the method can negotiate 10/100/1000M I/O3.3V NA isolation transformer and give the isolation transformer to the carrier plate gigabit network port 1;
MDI 2-1 MDI1 differential pair 2 positive electrode, can negotiate 10/100/1000M I/O3.3V NA to connect isolation transformer to carrier plate giga net port 1;
the negative electrode of the MDI3+ 1 differential pair 3 can negotiate 10/100/1000M I/O3.3V NA to connect an isolation transformer to the gigabit network port 1 of the carrier plate;
MDI 3-1 MDI1 differential pair 3 positive electrode, can negotiate 10/100/1000M I/O3.3V NA to connect isolation transformer to carrier plate giga net port 1;
USB3_ #2_RX_DN I USB3 port 2, superSpeed receives negative pole I AC coupled I AC coupling capacitor reservation, if the carrier plate is directly connected to an external USB port, a protection device is required to be added according to the port requirement;
USB3_ #2_RX_DP I USB3 port 2, superSpeed receives positive electrode I AC coupled AC coupling capacitance reservation, if the carrier plate is directly connected to an external USB port, a protection device is required to be added according to port requirements;
GND I/NA is zero with reference to the ground;
USB3_ # 2_TX_DN|USB 3 port 2, superSpeed sends negative pole|O|AC coupled|AC coupling capacitance|NA||reservation, if the carrier plate is directly connected to an external USB port, a protection device is required to be added according to port requirements;
USB3_ #2_TX_DP I USB3 port 2, superSpeed sends positive electrode I O I AC coupled I AC coupling capacitance NA I reservation, if the carrier plate is directly connected to an external USB port, a protection device is required to be added according to port requirements;
BOARD_Id0|carrier plates Id0|/|no| are distributed to be pulled up and pulled down according to the version, and the pulling up is distributed according to an ECM power supply;
BOARD_ID1I/I is not provided, and the pull-up I carrier plate is distributed according to the version and only pulled down, and the pull-up is distributed according to the ECM power supply;
M.2_5G_CLK_100M_DN|| PCIe devices reference the 100M clock differential negative at this time, the PCIE NA is given to the M.2G slot position;
M.2_5G_CLK_100M_DP I PCIe devices refer to the 100M clock differential positive pole I O I PCIE I NA I this clock to the M.2G slot;
ecm_present_n| is placed at the connector corner for connector insertion stability detection|i|3.3V/1.8 v|ground|| and present0# loop back| none;
the reserved termination of the HDMI_DDC_SDA is matched with the HDMI IIC data, namely the HDMI IIC data is O1.8V, and the HDMI_DDC_SDA is matched with the HDMI IIC data;
HDMI_DDC_SCL HDMI IIC clock O1.8V reservation termination match NA none;
HDMI_CBL_HPD I HDMI hot plug detection I1.8V reservation termination match NA I none;
MCU_UART_TX I MCU UART serial port transmits I O I3.3V I NA I not;
MCU_UART_RX I MCU UART serial port receives I3V NA none;
PerST_M.2_5G_PCIE_N is active low from the device reset signal O3.3V NA, the carrier plate upward pulling I is distributed to the carrier plate acceleration card 5G module slot position;
perst_2m.2_pcie0_n is active low from the device reset signal O3.3V NA, the carrier plate upward drawing I is distributed to the carrier plate acceleration card 2M.2MAIN slot position;
the ECM_RESETBTN_N system reset button signal is pulled up to 3V3stby no at 3.3V NA 4.7K;
the ECM_POWERBTNIN_N system switch button signal I3.3V NA 4.7K is pulled up to 3V3stby no;
M.2_5G_RESET# |PCIe slave device reset signal O3.3V NA is distributed to the 5G module slot of the carrier board accelerator card;
Ecm_alert_n|whole-plate health green light control|o|3.3v|na||mos control, high level lighting|none;
ecm_HEALTH_N whole board fault red light control of 3.3V NA MOS control, high level lighting is not present;
MCU_I2C_SCL I2C clock output I O3V I Carrier pull-up reservation I Carrier pull-up I not;
MCU_I2C_SDA I2C data input/output I/O I3V I Carrier pull-up reservation I Carrier pull-up I not.
Clkreq_m.2_ssd_pcie_n||pcie device reference to the 100M clock request signal I3.3V I ECM pull-up I carrier plate pull-up I are distributed to carrier plate acceleration card M.2SSD slot positions;
the PEWAKE_M.2_SSD_PCIE_N_PCIe wake-up signal is 3.3V ECM pull-up reservation is distributed to the carrier acceleration card M2 SSD slot.
PERST m.2SSD PCIE N PCIE slave device reset signal O3.3V NA is active low, the carrier plate upward pulling I is distributed to the carrier plate acceleration card M.2SSD slot position;
FRU_I2C_SDA I2C clock outputs O3. V||carrier pull-up reservation||carrier pull-up|none;
FRU_I2C_SCL I2C data input/output I/O3.3V Carrier pull-up reservation Carrier pull-up nothing;
m2_i2c_sda_m.2device I2C clock output O3.3V Carrier pull-up reservation Carrier pull-up none;
m2_i2c_scl|m2device I2C data input/output|i/o|3, 3 v|carrier pull-up reservation|carrier pull-up|none.
Clkreq_m.2_5g_pcie_n|| PCIe device reference the 100M clock requires the signal I3V. The ECM is pulled up and the carrier plate is pulled up and distributed to the carrier plate acceleration card 5G module slot;
the PEWAKE_M.2_5G_PCIE_N is a PCIe wake-up signal I3.3V ECM pull-up reservation I is distributed to a carrier acceleration card 5G module slot;
the FULL_CARD_POWER_OFF# ||5G module POWERs down|| powering down an O3.3V 5G module without I;
W_DISABLE1# |5G module flight mode control|O|3.3V/1.8V|ECM pull-up|NA|5G module flight mode control;
W_DISABL2# |5G module flight mode control|O|3.3V/1.8V|ECM pull-up|NA|5G module flight mode control;
TPM_SPI0_CS# |SPI0 chip selection|O||3.3V|ECM pull-up reservation|carrier plate pull-up|reserved for TPM functions;
TPM_SPI0_MIS0_SPI0 master-slave-transmission I3, 3V NA is reserved for the TPM function, and termination matching is reserved according to actual link simulation;
emergency event I3V of tpm_irq# ||tcpm. The support plate is pulled up and reserved for the TPM function;
TPM_SPI0_CLK_SPI0 clock O3.3V NA is reserved for TPM functions, and termination matching is reserved according to actual link simulation;
TPM_SPI0_MOSI SPI0 master-slave receiving 3.3V NA is reserved for TPM functions, and end-to-end matching is reserved according to actual link simulation;
Clkreq_2m.2_pcie0_n_n_pcie device refers to the 100M clock request signal I3.3V ECM pull-up carrier pull-up is allocated to carrier accelerator card 2m.2main slot;
pewake_2m.2_pcie0_n_n PCIe wake signal I3.3V ECM pull-up reservation I is allocated to carrier acceleration card 2m 2main slot;
2M.2_PCIE_RXN3| PCIe Lane3 receives the differential signal negative electrode I| AC coupled the NA AC coupling capacitance is distributed to the 2M.2MAIN slot of the carrier plate acceleration card;
2M.2_PCIE_RXP3I PCIe Lane3 receives the differential signal positive electrode I AC coupled and NA AC coupling capacitance I to be distributed to a carrier acceleration card 2M.2MAIN slot;
2M.2_PCIE_RXN2| PCIe Lane2 receives the differential signal negative electrode I| AC coupled the NA AC coupling capacitance is distributed to the 2M.2MAIN slot of the carrier plate acceleration card;
2M.2_PCIE_RXP2I PCIe Lane2 receives the differential signal positive electrode I AC coupled and NA AC coupling capacitance I to be distributed to a carrier acceleration card 2M.2MAIN slot;
2M.2_PCIE_RXN1| PCIe Lane1 receives the differential signal negative electrode I| AC coupled the NA AC coupling capacitance is distributed to the 2M.2MAIN slot of the carrier plate acceleration card;
2 M.2_PCIE_RXP1I PCIe Lane1 receives the differential signal positive electrode I AC coupled and NA AC coupling capacitance I to be distributed to a carrier acceleration card 2M.2MAIN slot;
2M.2_PCIE_RXN0|PCIe Lane0 receives the differential signal negative electrode I|AC coupled the NA AC coupling capacitance is distributed to the 2M.2MAIN slot of the carrier plate acceleration card;
2M.2_PCIE_RXP0I PCIe Lane0 receives the differential signal positive electrode I AC coupled and NA AC coupling capacitance I to be distributed to a carrier acceleration card 2M.2MAIN slot;
2M.2_CLK0_100M_DN|| PCIe devices reference a 100M clock differential negative electrode the PCIE NA clock is given to the 2M.2MAIN slot;
2M.2_CLK0_100M_DP|| PCIe devices reference the 100M clock differential positive electrode the PCIE NA clock is given to the 2M.2MAIN slot;
2M.2_PCIE_TXN3||PCIe Lane3 Send differential signal negative pole O AC coupled the AC coupling capacitance NA is distributed to the 2M.2MAIN slot of the carrier plate acceleration card;
2M.2_PCIE_TXP3| PCIe Lane3 sends a differential signal positive electrode|O|AC coupled|AC coupling capacitance|NA| to be distributed to a carrier acceleration card 2M.2MAIN slot;
2M.2_PCIE_TXN2| PCIe Lane2 sends differential signal negative pole O| AC coupled the AC coupling capacitance NA is distributed to the 2M.2MAIN slot of the carrier plate acceleration card;
2M.2_PCIE_TXP2||PCIe Lane2 Send differential signal positive electrode O AC coupled the AC coupling capacitance NA is distributed to the 2M.2MAIN slot of the carrier plate acceleration card;
2M.2_PCIE_TXN1||PCIe Lane1 Send differential signal negative pole O AC coupled the AC coupling capacitance NA is distributed to the 2M.2MAIN slot of the carrier plate acceleration card;
2 M.2_PCIE_TXP1I PCIe Lane1 sends a differential signal positive electrode I O I AC coupled I AC coupling capacitance I NA I to be distributed to a carrier acceleration card 2M.2MAIN slot;
2M.2_PCIE_TXN0||PCIe Lane0 Send differential signal negative pole O AC coupled the AC coupling capacitance NA is distributed to the 2M.2MAIN slot of the carrier plate acceleration card;
2M.2_PCIE_TXP0| PCIe Lane0 transmits a differential signal positive electrode|O|AC coupled|AC coupling capacitance|NA| to be distributed to a carrier acceleration card 2M.2MAIN slot;
M2_5G_PCIE_RXN0||PCIe Lane0 receives differential signal negative pole I AC coupled the NA AC coupling capacitance is distributed to the 5G module slot of the carrier plate acceleration card;
M.2_5G_PCIE_RXP0_PCIe Lane0 receives the differential signal positive electrode I AC coupled and NA AC coupling capacitance I to be distributed to the module slot position of the carrier board accelerator card 5G;
BOARD_ID2|carrier plates ID 2|I|/|none| are distributed to be pulled up and pulled down according to the version, and the pulling up is distributed according to an ECM power supply;
the power state of the ECM_PG is used for lighting a power lamp of the bottom plate and is not equal to the power timing control of O3.3V NA;
M.2_SSD_PCIE_RXN3| PCIe Lane3 receives the differential signal negative I| AC the coupled NA AC coupling capacitance is distributed to the slot position of the carrier acceleration card M.2SSD;
M.2_SSD_PCIE_RXP3I PCIe Lane3 receives the differential signal positive pole I AC the coupled NA AC coupling capacitance is distributed to the slot position of the carrier acceleration card M.2SSD;
M.2_SSD_PCIE_RXN2| PCIe Lane2 receives the differential signal negative I| AC the coupled NA AC coupling capacitance is distributed to the slot position of the carrier acceleration card M.2SSD;
M.2_SSD_PCIE_RXP2|PCIe Lane 2|the differential signal positive pole|I||AC is received the coupled NA AC coupling capacitance is distributed to the slot position of the carrier acceleration card M.2SSD;
M.2_SSD_PCIE_RXN1 is used for receiving a differential signal negative electrode I AC coupled and NA AC coupling capacitance I to be distributed to a carrier acceleration card M2 SSD slot position;
M.2_SSD_PCIE_RXP1I PCIe Lane1 receives the differential signal positive pole I AC the coupled NA AC coupling capacitance is distributed to the slot position of the carrier acceleration card M.2SSD;
M.2_SSD_PCIE_RXN0||PCIe Lane0 receiving negative pole I AC of differential signal the coupled NA AC coupling capacitance is distributed to the slot position of the carrier acceleration card M.2SSD;
M.2_SSD_PCIE_RXP0||PCIe Lane0 receiving positive electrode I AC of differential signals the coupled NA AC coupling capacitance is distributed to the slot position of the carrier acceleration card M.2SSD;
the M.2_SSD_CLK_100M_DN|| PCIe device refers to the 100M clock differential negative O PCIE NA|| and gives the same to the M.2SSD slot;
M.2_SSD_CLK_100M_DP I PCIe devices refer to 100M clock differential positive pole O PCIE NA is given to the M.2SSD slot at this time;
M.2_SSD_PCIE_TXN3||PCIe Lane3 transmitting a differential signal negative pole O AC the coupled AC coupling capacitance NA is distributed to the slot position of the carrier acceleration card M.2SSD;
M.2_SSD_PCIE_TXP3||PCIe Lane3 transmitting differential signal positive electrode O AC the coupled AC coupling capacitance NA is distributed to the slot position of the carrier acceleration card M.2SSD;
M.2_SSD_PCIE_TXN2| the PCIe Lane2 sends a differential signal negative electrode|O|AC coupled|AC coupling capacitance|NA| to the carrier acceleration card M2 SSD slot.
And M.2_SSD_PCIE_TXP2| PCIe Lane2 transmits a differential signal positive electrode|O||AC coupled|AC coupling capacitance|NA| to a carrier acceleration card M2 SSD slot.
M.2_SSD_PCIE_TXN1||PCIe Lane1 transmitting a differential signal negative pole O AC the coupled AC coupling capacitance NA is distributed to the slot position of the carrier acceleration card M.2SSD;
M.2_SSD_PCIE_TXP1| PCIe Lane1 transmits a differential signal positive electrode|O|| AC coupled| AC coupling capacitance|NA| to be distributed to a carrier acceleration card M2 SSD slot.
M.2_SSD_PCIE_TXN0| PCIe Lane0 transmits a differential signal negative electrode|O|AC coupled|AC coupling capacitance|NA| to be distributed to a carrier acceleration card M2 SSD slot.
M.2_SSD_PCIE_TXP0| PCIe Lane0 transmits a differential signal positive electrode|O|AC coupled|AC coupling capacitance|NA| to a carrier acceleration card M2 SSD slot.
M.2_5G_PCIE_TXN0| PCIe Lane0 sends a differential signal negative electrode|O|AC coupled|NA||AC coupling capacitance| to be distributed to a slot position of a module of the carrier board acceleration card 5G;
M.2_5G_PCIE_TXP0_PCIe Lane0 transmits a differential signal positive electrode O AC coupled and NA AC coupling capacitance to be distributed to a module slot of the carrier board accelerator card 5G;
wake_on_wan# |5g module WAKEs up host signal|i|3.3V/1.8 v|ecm pull-up|na||5g module WAKE up signal to host, 5G module port OC;
the VCCRTC_3P3| real-time clock, the carrier plate button battery supplies power to the ECM board RTC, the NA| RTC battery interface, when the RTC chip is on the ECM board, the interface provides a battery power supply for the RTC, a diode is connected to the ECM to prevent current from flowing backward to the battery, and when the RTC chip is arranged on the bottom plate, the I2C1 interface is directly used.
In the description herein, the double vertical line "||" is used to separate adjacent two descriptions without other meaning.
Thus, in an alternative embodiment of the present disclosure, with reference to fig. 12, the main connector includes 5 columns of signal terminals, in order, a first column (i.e., a column) of signal terminals, a second column (i.e., B column) of signal terminals, a third column (i.e., C column) of signal terminals, a fourth column (i.e., D column) of signal terminals, and a fifth column (i.e., E column) of signal terminals; the first column signal terminal comprises a power supply terminal, a first USB signal terminal and a first CAN bus signal terminal; the second column signal terminals comprise a first HDMI interface signal terminal, a first Ethernet signal terminal and a second USB signal terminal; the third column signal terminal comprises a first mobile communication signal terminal, a second HDMI interface signal terminal, a first memory signal terminal and a first SPI signal terminal; the fourth column signal terminals include a first AI module signal terminal and a second mobile communication signal terminal; the fifth column signal terminal includes a second memory signal terminal and a third mobile communication signal terminal.
The arrangement is beneficial to avoiding signal interference among different types of signal terminals and improving the stability of signal transmission; meanwhile, the arrangement regularity of the signal terminals is strong, and the signal terminals in adjacent rows are staggered, so that the arrangement space of the main connector is saved, the processing is convenient, and the stability of the whole structure is improved.
In an alternative embodiment of the present disclosure, in a similar arrangement, in conjunction with fig. 12, the 5-column signal terminals of the auxiliary connector are a sixth-column (i.e., a-column) signal terminal, a seventh-column (i.e., B-column) signal terminal, an eighth-column (i.e., C-column) signal terminal, a ninth-column (i.e., D-column) signal terminal, and a tenth-column (i.e., E-column) signal terminal, respectively; wherein the sixth column signal terminal includes a CSI signal terminal and a third USB signal terminal; the seventh column of signal terminals includes a JTAG signal terminal, a fourth USB signal terminal, and a second Ethernet signal terminal; the eighth column signal terminal comprises a fourth mobile communication signal terminal, a third HDMI interface signal terminal and a second SPI signal terminal; the ninth column signal terminal includes an audio signal terminal, a serial communication bus signal terminal, and a memory card signal terminal; the tenth column signal terminal includes a second AI module signal terminal and a second CAN bus signal terminal.
The arrangement is beneficial to avoiding signal interference among different types of signal terminals and improving the stability of signal transmission; meanwhile, the arrangement regularity of the signal terminals is strong, and the signal terminals in adjacent rows are staggered, so that the arrangement space of the main connector is saved, the processing is convenient, and the stability of the whole structure is improved.
That is, in an alternative embodiment of the present disclosure, the pin definition of the auxiliary connector may also be implemented based on the pin arrangement shown in fig. 12 described above.
Exemplary, the pin definitions of the auxiliary connector are shown in table 5.
TABLE 5 Pin definition of auxiliary connector
The definition of each pin in table 5 is described as follows according to the sequence of "signal name signal meaning, functional description signal flow direction (I/O/IO) |channel voltage (expressed in Pwr Rail) |ecm pull-down and whether other processing|remarks are required for processing a condition|load (Carrier)":
GND I/NA is zero with reference to the ground;
the CSI_LANE3+ | camera inputs the positive electrode|I|1.8V|NA|NA| of the differential pair 3 to the carrier board for connecting with the FPC connector of the camera;
the CSI_LANE 3-I camera inputs the negative electrode I1.8V NA I of the differential pair 3 to the carrier board for connecting with the FPC connector of the camera;
The CSI_LANE2+ |camera inputs the positive electrode|I|1.8V|NA|NA| of the differential pair 2 to the carrier board for connecting with the FPC connector of the camera;
the CSI_LANE 2-I camera inputs the negative electrode I1.8V NA I of the differential pair 2 to the carrier board for connecting with the FPC connector of the camera;
the CSI_LANE1+ | camera inputs positive electrode|I| 1.8 V|NA| of the differential pair 1 to the carrier board for connecting with an FPC connector of the camera;
the CSI_LANE1-I camera inputs negative electrode I1.8V NA I of the differential pair 1 to the carrier board for connecting with the FPC connector of the camera;
CSI_LANE0+|camera input the differential pair 0 positive pole I1V 8V. The NA is given to the FPC connector of the carrier plate for connecting the camera;
the CSI_LANE 0-I camera inputs a negative electrode I1.8V NA I of the differential pair 0 to the carrier board for connecting with an FPC connector of the camera;
CSI_CLK++ is the positive electrode of the differential clock pair of the camera O1.8V NA for the FPC connector of the carrier plate for connecting the camera;
the CSI_CLK-camera differential clock pair negative electrode is 1.8V NA for the FPC connector of the carrier plate for connecting the camera;
the CSI_RST is reset to 1.8V NA for the FPC connector of the camera;
the CSI_MCLK system clock outputs 1.8V NA to the FPC connector of the carrier board for connecting the camera;
The CSI_I2C_SCL is used for outputting 3.3V I Carrier upward pulling reservation I Carrier upward pulling I to the FPC connector of the camera for connecting the Carrier;
the CSI_I2C_SDA is I/O3V 3 Carrier is pulled up to reserve the Carrier and pull up the Carrier to be used for connecting with an FPC connector of a camera;
USB3_ #5_RX_DN||USB3 port 5, superSpeed receiving negative pole the AC coupling capacitance of the AC coupled NA is reserved, the carrier board accelerator card 5G module slot is allocated, and a protection device is required to be added according to the port requirement;
USB3_#5_RX_DP||USB3 port 5, superSpeed receives the positive pole the AC coupling capacitance of the AC coupled NA is reserved, the carrier board accelerator card 5G module slot is allocated, and a protection device is required to be added according to the port requirement;
USB3_ # 5_TX_DN|USB 3 port 5, superSpeed sends negative pole|O|AC coupled|AC coupling capacitance|NA||reservation, and the reserved negative pole|O|AC coupling capacitance|NA|AC coupling capacitance|AC coupled with the support board acceleration card 5G module slot is allocated to the support board acceleration card 5G module slot, and a protection device is required to be added according to port requirements;
USB3_ # 5_TX_DP|USB 3 port 5, superSpeed sends positive electrode|O|AC coupled|AC coupling capacitance|NA|reservation, and the reserved port is allocated to a module slot of the carrier board acceleration card 5G, and a protection device is required to be added according to the port requirement;
UART_FT231_TXD Micro-USB to UART TX interface O3V NA none.
UART_FT231_RXD Micro-USB to UART RX interface I3V NA none.
JTAG_TDI JTAG data input I3.3V I NA is pulled up to the carrier plate to convert USB, for debug;
JTAG_TDO and JTAG data output and 3.3V and NA are pulled up and converted into USB for the carrier for debug;
JTAG_TCK and JTAG clock output and 3.3V and NA are downwards pulled to convert USB for the carrier for debug;
JTAG_TMS and JTAG mode selection, 3.3V and NA, and a carrier plate is pulled up to convert USB for the carrier plate for debug;
JTAG_TRST I JTAG reset input I3.3V NA I carrier plate pull-up I to convert USB for the carrier plate for debug;
JTAG_SRST_N|JTAG system reset input||3.3V|NA|carrier plate pull-up| convert USB to the carrier plate for debug;
USB3_ #4_RX_DN||USB3 port 4, superSpeed receiving negative pole the AC coupling capacitance of the AC coupled NA is reserved, if the carrier plate is directly connected with the external USB port, a protection device is required to be added according to the port requirement;
USB3_ #4_RX_DP I USB3 port 4, superSpeed receives positive electrode I AC coupled AC coupling capacitance reservation, if the carrier plate is directly connected to an external USB port, a protection device is required to be added according to port requirements;
USB3_ # 4_TX_DN|USB 3 port 4, superSpeed sends negative pole|O|AC coupled|AC coupling capacitance|NA||reservation, if the carrier plate is directly connected to an external USB port, a protection device is required to be added according to port requirements;
USB3_ #4_TX_DP I USB3 port 4, superSpeed sends positive electrode I O I AC coupled capacitor I NA I reserved, if the carrier plate is directly connected with an external USB port, a protection device is required to be added according to port requirements;
USB 2_4_DN|USB 2 port 4, data negative electrode|I/O|3.3V|NA|NA| is reserved, and if the carrier plate is directly connected with an external USB port, a protection device is required to be added according to the port requirement;
USB 2_4_DP|USB 2 port 4, data positive electrode|I/O|3.3V|NA|is reserved, and if the carrier plate is directly connected with an external USB port, a protection device is required to be added according to port requirements;
the negative electrode of the MDI 0-2 differential pair 0 can negotiate 10/100/1000M I/O3.3V NA to connect an isolation transformer to the gigabit network port 2 of the carrier plate;
MDI 0-2 MDI2 differential pair 0 positive pole, can consult 10/100/1000M I/O3.3V NA to connect isolation transformer to carrier plate giga net port 2;
the negative electrode of the MDI 1-2 differential pair 1 can negotiate 10/100/1000M I/O3.3V NA to connect an isolation transformer to a carrier plate gigabit network port 2;
MDI 1-2 MDI2 differential pair 1 positive pole, can consult 10/100/1000M I/O3.3V NA to connect isolation transformer to carrier plate giga net mouth 2;
the negative electrode of the MDI2 differential pair 2 is 2 plus_2, 10/100/1000M I/O3.3V NA is connected with an isolation transformer and is given to the gigabit network port 2 of the carrier plate;
MDI 2-2I MDI2 differential pair 2 positive pole, can consult 10/100/1000M I/O3.3V I NA I connect isolation transformer I to carrier plate giga net mouth 2;
the negative electrode of the MDI3 < + > 2 < + > MDI2 < + > differential pair 3 can negotiate 10/100/1000M </I/O </I > < 3.3V </I > < NA </I > and connect an isolation transformer </I > to the gigabit network port 2 of the carrier plate;
MDI 3-2 MDI2 differential pair 3 positive electrode, can negotiate 10/100/1000M I/O3.3V NA to connect isolation transformer to carrier plate giga net mouth 2;
USB2_ # 5_DN|USB 2 port 5, reserved data negative electrode|I/O|3.3V|NA|NA| and allocated to a carrier plate acceleration card 5G module slot, and a protection device is required to be added according to port requirements;
USB2_ # 5_DP|USB 2 port 5, reserving data positive electrode|I/O|3.3V|NA|NA| and distributing the reserved data to a carrier board acceleration card 5G module slot, and adding a protection device according to port requirements;
FT232_RESET# |RS232 RESET signal|O|3.3V|NA|NA|none;
lan_sw1_100m_led_n|net port 1, signal of lamp|o|3.3v|na|to the carrier plate giga net port signal of lamp|o|3.3v|na|;
lan_sw1_active_led_n|net port 1, and signal of lamp|o|3.3v|na|na| to the carrier plate gigabit net port signal;
the FAN controls the ALERT signal to reserve with 3.3V NA;
FAN control THERM signal I3.3V NA reservation;
Lan_sw1_1000m_led_n|net port 1, signal of lamp|o|3.3v|na|to the carrier plate giga net port signal of lamp|o|3.3v|na|;
lan_sw2_100m_led_n|net port 2, beacon signal|o|3.3v|na|to carrier plate gigabit net port beacon signal;
lan_sw2_active_led_n|net port 2, signal of lamp|o|3.3v|na|to the carrier plate gigabit net port signal of lamp|o|3.3v|na|;
lan_sw2_1000m_led_n|net port 2, beacon signal|o|3.3v|na|to carrier plate gigabit net port beacon signal;
GPS_ANTOFF I GPS antenna control number O I3.3V I NA I reservation;
GPS_RESETn is reserved with GPS reset signal of 3.3V NA;
GPS_WAKEUP and GPS wake signal are reserved with I3.3V NA;
GPS_PPS I GPS Time Plus signal I3V NA reservation;
the GPS_I2C_DATA I2C clock outputs I/O I3V ECM pull-up reservation I carrier plate pull-up I none.
The GPS_I2C_CLK I2C clock outputs 3.3V ECM pull-up reservation carrier plate pull-up nothing;
GPS_UART_TX I GPS UART TX interface O I3V I NA I not;
GPS_UART_RX I3V NA none of the GPS UART RX interface;
W_DPR M.2G Module DPR signal O3V NA reservation.
HDMI_CEC control 1.8V reservation termination match NA nothing;
TPM_I2C_SDA indicates that TPM module I2C DATA signals are not present.
TPM_I2C_CLK| TPM module I2C CLK signal| none| none.
TPM_SPI0_CS# |SPI0 chip selection|O||3.3V|ECM pull-up reservation|carrier plate pull-up|reserved for TPM functions;
TPM_SPI0_MIS0||SPI0 master-slave transmission and slave-reception there is no there nor there is any there.
TPM_SPI1_WP# |SPI1 write protection there is no there nor there is any there.
TPM_Present# | TPM module Present signal there is no there nor there is any there.
TPM_SPI1_CS# |SPI1 chip selection|O||3.3V|ECM pull-up reservation|carrier plate pull-up|reservation to TPM function;
TPM_Reset# | TPM Reset signal || none| none;
TPM_SPI1_HOLD_SPI1 BUS Hold_I there is no there is no there nor there is no there.
TPM_SPI0_CLK_SPI0 clock is not shown nor shown;
TPM_SPI0_MOSI||SPI0 master-slave transmission and reception there is no there nor there is any there.
Csi_io0|csi Camera IO 0|none|none|none|none|none|none|none|;
csi_io1|csi Camera IO 1|none|none|none|none|none|none|none|none.
TPM_SPI0_CS# |SPI0 chip selection|O||3.3V|ECM pull-up reservation|carrier plate pull-up|reserved for TPM functions;
TPM_SPI0_MIS0_SPI0 master-slave-transmission I3, 3V NA is reserved for the TPM function, and termination matching is reserved according to actual link simulation;
Emergency event I3V of tpm_irq# ||tcpm. The support plate is pulled up and reserved for the TPM function;
TPM_SPI0_CLK_SPI0 clock O3.3V NA is reserved for TPM functions, and termination matching is reserved according to actual link simulation;
TPM_SPI0_MOSI SPI0 master-slave receiving 3.3V NA is reserved for TPM functions, and end-to-end matching is reserved according to actual link simulation;
the audio_HPH_L is provided with a protective device according to port requirements, wherein the left channel O is Analog NA of the earphone;
the audio_HPH_R is the right channel of the earphone, O is Analog, NA is the protective device is added according to the port requirement;
the audio_HPH_DET earphone insertion detection is 1.8V and NA, and a protection device is added according to port requirements;
MIC_BIAS I microphone reference I Analog NA I adds a protection device according to port requirements;
MIC_IN_P I microphone input I1.8V NA I according to port requirements, adding a protection device;
MIC_IN_M microphone input 1.8V NA according to port requirements, adding a protection device;
the method comprises the steps that an audio_MIC_DET microphone is inserted and detected, 1.8V NA is detected, and a protection device is added according to port requirements;
qtm1_therm|mmwave antenna temperature detection resistor|i|/|na|na|no;
qtm2_therm|mmwave antenna temperature detection resistor|i|/|na|na|no;
Qtm3_therm|mmwave antenna temperature detection resistor|i|/|na|na|no;
the RS485_UART_RX I RS485 UART TX interface I O I3.3V I NA I not;
the RS485_UART_TX I3.3V NA I none of the RS485 UART RX interface;
RS 485_rtsa_n|rs 232 UART RTS interface|o|3.3 v|na|na|none;
RS 232_uart_tx|rs 232 UART TX interface|o|3.3 v|na|na|none;
the RS232_UART_RX I RS232 UART RX interface I3.3V NA I none;
SDCARD_ESD_D0I/O data 0I/O3V/1.8V NA I carrier plate pull-up reservation I to MicroSD interface of the carrier plate;
SDCARD_ESD_D1I/O3V/1.8V NA carrier board pull-up reservation I to MicroSD interface of the carrier board;
SDCARD_ESD_D2I/O data 2I/O3V/1.8V NA I carrier plate pull-up reservation I to MicroSD interface of the carrier plate;
SDCARD_ESD_D3I/O3V/1.8V NA I carrier board pull-up reservation I to MicroSD interface of carrier board;
SDCARD_ESD_CLK_SDIO clock 3.3V/1.8V NA carrier plate is pulled up to the MicroSD interface of the carrier plate;
SDCARD_ESD_CMD is pulled up to the MicroSD interface of the carrier plate by SDIO command 3.3V/1.8V NA;
the SDCARD_ESD_CD_N SD card performs in-place detection on 3.3V/1.8V NA carrier board and pulls up the carrier board to a MicroSD interface of the carrier board;
SDCAD_V2P9|SD power supply|O|3.3V/1.8V|NA|NA| to the MicroSD interface of the carrier plate;
M.2_SSD_I2C_ALERT# | PCIe, SMBUS ALERT signal|I| 1.8V| NA| assigned to carrier board accelerator card M2 SSD slot.
2m.2_i2c_main_alert# |pcie, the SMBUS Alert signal I1.8V NA is distributed to the carrier board acceleration card 2M.2MAIN slot;
2m.2_i2c_2nd_alert# |pcie, the SMBUS Alert signal I1.8V NA is distributed to the carrier board acceleration card 2M.2second slot;
the audio_hph_ref_l Audio Codec signal references ground-left channel I/NA
The Audio Codec signal is referenced to ground;
the audio_hph_ref_r Audio Codec signal references ground-left channel I/NA
The Audio Codec signal is referenced to ground;
2M.2_PCIE_RXN7| PCIe Lane7 receives the differential signal negative electrode I| AC coupled| the NA AC coupling capacitance is distributed to the 2M.2second slot of the carrier plate acceleration card;
2M.2_PCIE_RXP7I PCIe Lane7 receives the differential signal positive electrode I AC coupled and NA AC coupling capacitance I to be distributed to a carrier acceleration card 2M.2second slot;
2M.2_PCIE_RXN6 is used for receiving the differential signal negative electrode I AC coupled and NA AC coupling capacitance I to be distributed to a carrier acceleration card 2M.2second slot;
2M.2_PCIE_RXP6I PCIe Lane6 receives the differential signal positive electrode I AC coupled and NA AC coupling capacitance I to be distributed to a carrier acceleration card 2M.2second slot;
2M.2_PCIE_RXN5| PCIe Lane5 receives the differential signal negative electrode I| AC coupled| NA| AC coupling capacitance| and distributes the differential signal negative electrode I| AC coupling capacitance| to a carrier plate acceleration card 2M.2second slot position;
2M.2_PCIE_RXP5I PCIe Lane5 receives the differential signal positive electrode I AC coupled and NA AC coupling capacitance I to be distributed to a carrier acceleration card 2M.2second slot;
2M.2_PCIE_RXN4| PCIe Lane4 receives the differential signal negative electrode I| AC coupled| the NA AC coupling capacitance is distributed to the 2M.2second slot of the carrier plate acceleration card;
2M.2_PCIE_RXP4I PCIe Lane4 receives the differential signal positive electrode I AC coupled and NA AC coupling capacitance I to be distributed to a carrier acceleration card 2M.2second slot;
2M.2_CLK1_100M_DN||PCIe device reference 100M clock differential negative the PCIENA NA clock is given to the 2M.2second slot;
2M.2_CLK1_100M_DP||PCIe device reference 100M clock differential negative the PCIENA NA clock is given to the 2M.2second slot;
2M.2_PCIE_TXN7| PCIe Lane7 sends differential signals negative pole O| AC coupled| the AC coupling capacitance NA is distributed to the 2M.2second slot of the carrier plate acceleration card;
2M.2_PCIE_TXP7I PCIe Lane7 sends differential signal positive pole O AC coupled the AC coupling capacitance NA is distributed to the 2M.2second slot of the carrier plate acceleration card;
2M.2_PCIE_TXN6| PCIe Lane6 sends differential signal negative pole O| AC coupled| the AC coupling capacitance NA is distributed to the 2M.2second slot of the carrier plate acceleration card;
2M.2_PCIE_TXP6| PCIe Lane6 sends differential signal positive pole O| AC coupled| the AC coupling capacitance NA is distributed to the 2M.2second slot of the carrier plate acceleration card;
2M.2_PCIE_TXN5| PCIe Lane5 sends differential signal negative pole O| AC coupled| the AC coupling capacitance NA is distributed to the 2M.2second slot of the carrier plate acceleration card;
2M.2_PCIE_TXP5||PCIe Lane5 transmit differential signal positive pole O AC coupled the AC coupling capacitance NA is distributed to the 2M.2second slot of the carrier plate acceleration card;
2M.2_PCIE_TXN4| PCIe Lane4 sends differential signal negative pole O| AC coupled| the AC coupling capacitance NA is distributed to the 2M.2second slot of the carrier plate acceleration card;
2M.2_PCIE_TXP4I PCIe Lane4 sends differential signal positive pole O AC coupled the AC coupling capacitance NA is distributed to the 2M.2second slot of the carrier plate acceleration card;
the method comprises the steps that a transmitting end of a CAN1 controller with the level of CAN1 is provided with a carrier CAN transceiver with the level of CAN 1O 3.3V NA, and reservation termination matching is recommended between the controller and the transceiver, and 120 omega matching is suggested between the rear ends of the transceiver and CANH;
the method comprises the steps that a receiving end of a CAN1 controller with the value of CAN 1I 3.3V NA I is given to a carrier CAN transceiver, reservation termination matching is recommended between the controller and the transceiver, and 120 omega matching is recommended between the rear end of the transceiver and CANH and CANL;
clkreq_2m.2_pcie1_n_n_pcie device refers to the 100M clock request signal I3.3V ECM pull-up carrier pull-up assigned to carrier acceleration card 2m.2second slot;
Pewake_2m.2_pcie1_n_n PCIe wake-up signal I3.3V ECM pull-up reservation I is assigned to carrier acceleration card 2m 2second slot.
In the context of the pin definitions in tables 4 and 5, the ECM is the core board and the carrier board is the carrier board of the ECM, which is the substrate above.
In an alternative embodiment of the present disclosure, when a dual connector architecture is employed, in one achievable structural specification of the edge computing device, the edge computing functional chip may employ a high-pass QSM8250 processor, and the memory specification of the processor may employ LPDDR5 12gb,64bit,2750mhz; the edge computing device is also compatible with video processing functions, graphics processing functions, and security processing functions; for example, the video processing functions may be implemented using an Adreno VPU 665-fifth generation UHD video processing unit, the graphics processing functions may be implemented using an Adreno GPU 650, in conjunction with OpenGL and OpenCL techniques, the security processing functions may be implemented using a processor security engine, in conjunction with a mobile payment security processing unit, biometric (e.g., fingerprint, iris, voice, facial, etc. feature recognition, etc.).
Illustratively, in the edge computing device, an AI acceleration module is optionally provided. Correspondingly, 1 double-wide m.2ai module slot may be provided, or 2 single-wide m.2ai module slots may be provided, to support artificial intelligence and machine learning. Illustratively, the AI acceleration module is supportable by the substrate system.
Illustratively, in the edge computing device, for storage functions, an on-board 256GB UFS may be provided, which may be used to store OS and application software; 1 Micro SD card slot can be provided to extend the Micro SD card by itself, the maximum of the Micro SD card can support SD3.0 rate SDR104, the maximum capacity can be 2TB, and the Micro SD card can be supported by a substrate system; 1 M.2SSD slot can be set, which can support 2280 specification PCIE interface, and can support through the base plate system.
For example, in the edge computing device, 2 wired network interfaces, such as gigabit ethernet interfaces and optical interfaces (i.e., optical-to-electrical multiplexing) may be provided for the wired network, and may be supported through the substrate system.
Illustratively, in the edge computing device, a wireless network interface may be configured for a wireless network to support m.2G communication module installation and support 5G mobile communication.
In the edge computing device, 4 SMA antenna interfaces, 1 SIM card slot, and optionally a 5G millimeter wave antenna module, which is required to be mounted on the substrate system, may be provided; a display interface can be further arranged to support the HDMI to penetrate through the substrate system interface; audio interfaces, such as 1 audio input interface and 1 audio output interface, can be arranged, the interface plane is circular, and the diameter can be 3.5mm; an acoustic interface may also be provided, supported by the substrate system; USB interfaces can also be provided, such as 2 USB2.0 interfaces (panels) and 1 USB2.0 interface (internal, for expanding USB dongles), the interface form can be Type-A; an alarm interface, such as 1 RS232 and 1 RS485, can be arranged for connecting with systems such as an external cradle head and access control; 4 alarm outputs can be set for connecting with external alarm output equipment such as smoke sensing system; 4 alarm inputs may also be provided for connection to external alarm input devices, such as an access control system.
In other embodiments, the edge processing apparatus may also adopt other specification structures, which are not described herein in detail and are not limited thereto.
In an alternative embodiment of the present disclosure, the core board 40 or the edge computing device as a whole may be powered on/off based on the power management device of any of the above embodiments.
In an alternative embodiment of the present disclosure, as shown in fig. 13 and 14, an opening area 400 is formed on the core board 40, and the opening area 400 is disposed corresponding to the edge calculation function chip 41.
In the embodiment of the disclosure, by setting the opening area 400 at the position corresponding to the edge computing function chip 41, the opening area 400 can be utilized to realize that the edge computing function chip 41 can also rapidly dissipate heat towards one side of the core board 41, thereby achieving the effects of double-sided heat dissipation and improving heat dissipation efficiency.
Further, the hole area 400 is further provided for a heat dissipation and conduction column to pass through, and the heat dissipation and conduction column passes through the hole area 400 and contacts a surface of the edge computing function chip 41 facing the core board 41, such as a surface of a memory chip, so as to achieve double-sided heat dissipation and achieve a good heat dissipation purpose.
In an alternative embodiment of the present disclosure, components such as the edge computing function chip 41 on the core board 40 may be designed according to an industrial specification, and the storage temperature range may be: the standard range of the working temperature is between 40 ℃ below zero and 85 ℃ below zero: -25 ℃ to +65 ℃, the wide temperature range is: -40 to +65 ℃; the storage humidity and the working humidity are: 5% RH to 95% RH, no condensation; the protection grade is IP40, and the heat dissipation mode is natural heat dissipation without a fan; and the device has the performances of high/low temperature resistance, dust prevention, shock resistance, strong electromagnetic interference resistance and the like, and can adapt to a severe working environment.
In an alternative embodiment of the present disclosure, the core board may support temperature monitoring of the temperature sensor, and two temperature monitoring points may be disposed around the edge calculation function chip 41 on the core board, so as to implement temperature monitoring based on the principle that the resistance value of the thermistor changes in response to temperature change.
Furthermore, the overall power consumption of the edge computing device needs to meet the requirements of different SoC computing platforms and functional chips, and the heat dissipation needs to meet the requirements of a threshold operating temperature range.
Taking a system-on-chip as an example, using a QSM8250 platform, the chip power consumption may include:
the QSM8250 is adopted to realize the SoC function, and the corresponding power consumption can be 12.5Watt, wherein the UFS flash memory is included, for example, the power consumption of a 125GB memory chip; the LT9611UXC video conversion chip is adopted to realize the display function, for example, the mipi of the mobile phone is converted into HDMI so as to adapt to the display of a liquid crystal display, and the corresponding power consumption can be 0.013Watt; LAN7800 is adopted to realize the function of LAN card, and the corresponding power consumption can be 1.7Watt; the function of the HUBUSB concentrator is realized by adopting USB5807CT-I/KD, and the corresponding power consumption can be 0.508Watt or 1.226Watt; ASM2812I is adopted to realize the function of a PCIe switch, and the corresponding power consumption can be 1.405Watt or 2.163Watt; WCD-9385 is adopted as an audio codec, and corresponding power consumption is derived from SoC; MCP25625 as CAN controller with corresponding power consumption of 0.35Watt; XR33202 is used as an RS485 serial communication interface chip, and the corresponding power consumption can be 0.003Watt; MAX3221 is used as an RS232 serial communication interface chip, and the corresponding power consumption may be 0.003Watt.
It can be appreciated that each of the above power consumption is related to an operating state, an operating environment, and other operating factors of the corresponding functional component, which are not described in detail herein.
It can be understood that the interface of the corresponding part of the chip is from the connector to the substrate, and the UFS and the memory are only in the SOM. That is, these functional chips may be provided on the substrate or the core board as needed, and the terminals of the main connector are adaptively adjusted based on the signal transmission relationship of the substrate and the core board.
In an alternative embodiment of the present disclosure, the core board may be powered from the main high speed connector to power the entire core board, which consumes less than 30W.
For example, the power pin supply may be as follows:
pins P3V3 are 3.3V power input, corresponding to 3.3V voltage sources, the number of pins is 8, and the power consumption can be supported to be 26.4 Watts; pins P5V are 5V power input and correspond to 5V voltage sources, the number of the pins is 2, and the power consumption can be supported to be 10Watt; pins P3V3_STBY are 3.3V Stby power input and correspond to 3.3V Stby voltage sources, the number of the pins is 2, and the power consumption can be supported to be 6.6Watt; pins VCCRTC_3P3 are 3V RTC power supply input and correspond to 3.3V RTC voltage sources, the number of the pins is 1, and the power consumption can be supported to be 3.3 Watts; pin GND, power ground, has 67 pins.
Illustratively, in connection with the electrical characteristics of the edge computing device, each set of absolute minimum ratings (abbreviated as "minimum"), maximum ratings (abbreviated as "maximum") and suggested operating ranges for each set of voltages based thereon are as follows (shown in "pin name minimum maximum suggested range V, voltage unit V):
P3V3||-0.5||3.6||3.135～3.465；
P5V||-0.3||6||4.75～5.25；
P3V3_STBY||-0.5||3.6||3.135～3.465；
VCCRTC_3P3||-0.3||3.3||2.79～3.21；
GND||0||0||0～0。
the edge computing equipment provided by the embodiment of the disclosure adopts a modularized design, can be independently evolved, has expansibility and compatibility, and is beneficial to ensuring that the edge computing equipment and a system comprising the equipment have compatibility of various solutions and the system upgrading iteration requirement after the future computing power is improved; meanwhile, the core board adopts two structural size forms, and provides more elastic configuration aiming at the whole EBB+ECM solution; the interface definition fully considers the functional requirements of the edge computing industry on the universal interface, and can meet the requirements of various different edge computing scenes; finally, through setting up the opening area, realize two-sided heat dissipation to the heat dissipation of two-sided chip module, improve radiating efficiency.
The embodiment of the disclosure also provides an edge computing system, which may include the power management device of any one of the above embodiments, or include the edge computing device of any one of the above embodiments, with corresponding technical effects.
In the embodiment of the disclosure, the edge computing device is disposed in the edge computing system, and other terminal devices are not necessarily capable of supplying power, so that in one edge computing system, a possible device supports POE function, and a possible device does not support POE function, and needs to be powered on or powered off, i.e., direct current can be coupled or separated from a network transmission line by using a power management device, and the separated direct current can be used by other electric devices, and when in use, direct current reprocessing, such as boosting, reducing, balancing, etc., is needed. The consumer may be, for example, an edge computing device or a data acquisition device, without limitation.
Meanwhile, in the edge computing equipment, the core boards and the base boards are connected in a strippable manner, the core boards with different computing forces can be combined with different base boards to form various different edge computing equipment, the edge computing platform which meets the flexibility of optional matching is realized, and the requirements of various different edge computing scenes are met.
The foregoing description is only of the preferred embodiments of the present disclosure and description of the principles of the technology being employed. It will be appreciated by persons skilled in the art that the scope of the disclosure referred to in this disclosure is not limited to the specific combinations of features described above, but also covers other embodiments which may be formed by any combination of features described above or equivalents thereof without departing from the spirit of the disclosure. Such as those described above, are mutually substituted with the technical features having similar functions disclosed in the present disclosure (but not limited thereto).
Moreover, although operations are depicted in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order. In certain circumstances, multitasking and parallel processing may be advantageous. Likewise, while several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of the present disclosure. Certain features that are described in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination.
Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are example forms of implementing the claims.
Claims (15)
1. A power management apparatus comprising at least one power management unit, each of said power management units comprising a mode changeover switch, a power supply loading circuit, a power receiving power separation circuit, a power line and a network transmission line;
The mode switching switch is used for selectively conducting the power supply loading circuit and the power line or conducting the power receiving power supply separating circuit and the power line according to a working mode;
the power supply loading circuit is used for loading direct current transmitted from the power line onto the network transmission line;
the power receiving power supply separation circuit is used for separating direct current transmitted from the network transmission line to the power supply line;
the network transmission line is connected with the edge computing device.
2. The power management apparatus according to claim 1, wherein the power supply loading circuit includes:
a boost sub-circuit for boosting a direct current of a first voltage transmitted on a power line into a direct current of a second voltage, the value of the second voltage being greater than the value of the first voltage;
and the loading sub-circuit is used for loading direct current of a second voltage onto the network transmission line.
3. The power management apparatus according to claim 2, wherein the power-receiving power supply separation circuit includes:
a separation sub-circuit for separating the direct current of the third voltage from the network transmission line;
and the voltage reducing sub-circuit is used for reducing the direct current of the third voltage into the direct current of a fourth voltage, and the value of the fourth voltage is smaller than that of the third voltage.
4. The power management apparatus according to claim 1, wherein the number of the power management units is at least two, power lines of the at least two power management units are electrically connected as a common power output terminal, each of the power management units further comprising:
the load balancing circuit is connected with the power receiving power supply separation circuit in series;
and the load balancing circuits among the different power management units are electrically connected to balance the load among the at least two power management units.
5. The power management apparatus of claim 4, wherein each of the power management units is enclosed in a housing, the housing being provided with a first opening through which a network transmission line passes, a second opening through which a power line passes, and a third opening through which a cascading probe for achieving load balancing circuit electrical connection between different power management units.
6. The power management device of claim 1, wherein the network transmission line connected to the edge computing device is configured to transmit network signals and direct current; or alternatively
The network transmission line connected with the edge computing device is used for transmitting network signals.
7. The power management device of claim 1, wherein the edge computing device connected to the network transmission line comprises a core board and a substrate, the core board is provided with an edge computing function chip, the substrate is provided with a signal transmission interface, and the edge computing function chip on the core board is connected to the signal transmission interface on the substrate through at least one connector.
8. The edge computing equipment is characterized by comprising a core board and a substrate, wherein an edge computing function chip is arranged on the core board, a signal transmission interface is arranged on the substrate, and the edge computing function chip on the core board is connected with the signal transmission interface on the substrate through at least one connector;
the signal transmission interface is connected to the power management device according to claims 1-7 via a network transmission line.
9. The edge computing device of claim 8, wherein the at least one connector comprises a main connector secured to an edge of the core board.
10. The edge computing device of claim 9, wherein the main connector comprises a first column signal terminal, a second column signal terminal, a third column signal terminal, a fourth column signal terminal, and a fifth column signal terminal;
The first column signal terminal comprises a power supply terminal, a first USB signal terminal and a first CAN bus signal terminal;
the second column signal terminal comprises a first HDMI interface signal terminal, a first Ethernet signal terminal and a second USB signal terminal;
the third column signal terminal comprises a first mobile communication signal terminal, a second HDMI interface signal terminal, a first memory signal terminal and a first SPI signal terminal;
the fourth column signal terminals include a first AI module signal terminal and a second mobile communication signal terminal;
the fifth column signal terminal includes a second memory signal terminal and a third mobile communication signal terminal.
11. The edge computing device of claim 8, wherein the at least one connector comprises an auxiliary connector secured to an edge of the core board.
12. The edge computing device of claim 11, wherein the auxiliary connector comprises a sixth column signal terminal, a seventh column signal terminal, an eighth column signal terminal, a ninth column signal terminal, and a tenth column signal terminal;
the sixth column signal terminal comprises a CSI signal terminal and a third USB signal terminal;
The seventh column signal terminal comprises a JTAG signal terminal, a fourth USB signal terminal and a second Ethernet signal terminal;
the eighth column signal terminal comprises a fourth mobile communication signal terminal, a third HDMI interface signal terminal and a second SPI signal terminal;
the ninth column signal terminal comprises an audio signal terminal, a serial communication bus signal terminal and a memory card signal terminal;
the tenth column signal terminal includes a second AI module signal terminal and a second CAN bus signal terminal.
13. The edge computing device of claim 8, wherein an opening area is formed on the core board, the opening area being disposed corresponding to the edge computing function chip.
14. The edge computing device of claim 8, wherein a power management device connected to the network transmission line comprises at least one power management unit, each power management unit comprising a mode switch, a power supply loading circuit, a power supply splitting circuit, a power line, and a network transmission line;
the mode switching switch is used for selectively conducting the power supply loading circuit and the power line or conducting the power receiving power supply separating circuit and the power line according to a working mode;
The power supply loading circuit is used for loading direct current transmitted from the power line onto the network transmission line;
the power receiving power supply separation circuit is used for separating direct current transmitted from the network transmission line to the power line.
15. An edge computing system comprising the power management device of any of claims 1-7, and the edge computing device of any of claims 8-14.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1708409A2 (en) * | 2005-03-28 | 2006-10-04 | Akros Silicon, Inc. | Systems and methods operable to allow loop powering of networked devices |
| CN101043341A (en) * | 2006-03-24 | 2007-09-26 | 美国博通公司 | Inband management for power over Ethernet midspans using an embedded switch |
| CN103703429A (en) * | 2011-07-18 | 2014-04-02 | 惠普发展公司，有限责任合伙企业 | Power consumption limit associated with power over ethernet (POE) computing system |
| CN203522773U (en) * | 2013-09-16 | 2014-04-02 | 上海斐讯数据通信技术有限公司 | POE power supply splitter and POE system |
| CN107786345A (en) * | 2016-08-26 | 2018-03-09 | 北京安拓伟业科技发展有限公司 | Large power long criterion distance POE separators, POE system and POE system control method |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070288771A1 (en) * | 2006-06-08 | 2007-12-13 | Steven Andrew Robbins | Source Separator for Power over Ethernet Systems |
| US7873844B2 (en) * | 2006-06-28 | 2011-01-18 | Broadcom Corporation | Physical separation and recognition mechanism for a switch and a power supply for power over Ethernet (PoE) in enterprise environments |
| US9363091B2 (en) * | 2013-12-23 | 2016-06-07 | Louroe Electronics | Power over Ethernet devices, systems and methods |
-
2021
- 2021-08-23 CN CN202110970459.4A patent/CN113885686B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1708409A2 (en) * | 2005-03-28 | 2006-10-04 | Akros Silicon, Inc. | Systems and methods operable to allow loop powering of networked devices |
| CN101043341A (en) * | 2006-03-24 | 2007-09-26 | 美国博通公司 | Inband management for power over Ethernet midspans using an embedded switch |
| CN103703429A (en) * | 2011-07-18 | 2014-04-02 | 惠普发展公司，有限责任合伙企业 | Power consumption limit associated with power over ethernet (POE) computing system |
| CN203522773U (en) * | 2013-09-16 | 2014-04-02 | 上海斐讯数据通信技术有限公司 | POE power supply splitter and POE system |
| CN107786345A (en) * | 2016-08-26 | 2018-03-09 | 北京安拓伟业科技发展有限公司 | Large power long criterion distance POE separators, POE system and POE system control method |
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