CN113866798A - Method, device, system and medium for testing 1PPS signal time precision - Google Patents
Method, device, system and medium for testing 1PPS signal time precision Download PDFInfo
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- CN113866798A CN113866798A CN202111154601.4A CN202111154601A CN113866798A CN 113866798 A CN113866798 A CN 113866798A CN 202111154601 A CN202111154601 A CN 202111154601A CN 113866798 A CN113866798 A CN 113866798A
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- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S19/00—Satellite radio beacon positioning systems; Determining position, velocity or attitude using signals transmitted by such systems
- G01S19/01—Satellite radio beacon positioning systems transmitting time-stamped messages, e.g. GPS [Global Positioning System], GLONASS [Global Orbiting Navigation Satellite System] or GALILEO
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Abstract
The invention discloses a method, a device, a system and a medium for testing the time precision of a 1PPS signal, wherein the method comprises the following steps: acquiring M to-be-detected 1PPS signals and M reference 1PPS signals; wherein the M reference 1PPS signals are output by a reference unit through a multi-stage buffer; comparing the M to-be-detected 1PPS signals with the M reference 1PPS signals to obtain a comparison result; and acquiring the time precision of each to-be-detected 1PPS signal according to the comparison result. By adopting the embodiment of the invention, a plurality of signals can be tested at one time under the condition of reducing the testing cost, the testing efficiency is greatly improved, and the method is convenient and quick.
Description
Technical Field
The invention belongs to the technical field of frequency calibration, and particularly relates to a method, a device, a system and a medium for testing 1PPS signal time precision.
Background
At present, the time requirements of various terminal devices are more and more accurate, and satellite time service becomes terminal devices or an indispensable part in the market; after the GNSS chip captures a satellite to realize 3D positioning, a second pulse with more accurate error ns relative to a world clock can be output, and the terminal equipment can acquire accurate time by capturing the second pulse; because the 1PPS signal output by each GNSS chip has a certain error, the GNSS chips with relatively small errors of the output 1PSS signals need to be screened out through testing; however, the clock output of the 1PPS signal of the GNSS chip is an error of ns level, which brings great difficulty to screening, and the most effective method at present is to compare the 1PPS signal with the second pulse output by the atomic clock;
however, because the atomic clock is expensive, the second pulse amplitude output by the atomic clock changes along with the change of the external load impedance, the load impedance is debugged once for each tested load, and the second pulse signal of the atomic clock and the 1PPS signal output by the GNSS capture the relative error of the signals through an oscilloscope, so that the method is only suitable for the research and development debugging stage and cannot be used for testing the product production end;
if the atomic clock and the 1PPS signal are captured simultaneously through the oscilloscope, the 1PPS signal time precision data are printed on the upper computer through a tool carried by the oscilloscope, however, the number of channels of the oscilloscope is limited (generally, only 4 channels are provided), at most 3 terminal devices are tested simultaneously, and the test environment is complex to set up.
Disclosure of Invention
The present invention is directed to solving, at least to some extent, one of the technical problems in the related art. Therefore, an object of the present invention is to provide a method, apparatus, system and medium for testing the time accuracy of 1PPS signals.
In order to solve the above technical problem, an embodiment of the present invention provides the following technical solutions:
a method of testing the time accuracy of a 1PPS signal, comprising:
acquiring M to-be-detected 1PPS signals and M reference 1PPS signals; wherein the M reference 1PPS signals are output by a reference unit through a multi-stage buffer;
comparing the M to-be-detected 1PPS signals with the M reference 1PPS signals to obtain a comparison result;
and acquiring the time precision of each to-be-detected 1PPS signal according to the comparison result.
Optionally, the multiple buffers at least include a first buffer, a second buffer, a third buffer, and a fourth buffer, and the first buffer, the second buffer, the third buffer, and the fourth buffer are connected in cascade;
and the reference unit outputs one path of reference 1PPS signals through the multistage buffers, sequentially passes through the first-stage buffer, the second-stage buffer, the third-stage buffer and the fourth-stage buffer, and outputs sixteen paths of reference 1PPS signals.
Optionally, the reference unit outputs sixteen paths of reference 1PPS signals through one path of reference 1PPS signals output by the multi-stage buffers, sequentially passing through the first-stage buffer, the second-stage buffer, the third-stage buffer, and the fourth-stage buffer, and includes:
the first-stage buffer receives one path of the reference 1PPS signals input by the reference unit and outputs two paths of the reference 1PPS signals to the second-stage buffer;
the second-stage buffer receives the two paths of reference 1PPS signals and outputs four paths of reference 1PPS signals to a third-stage buffer;
the third stage buffer receives four paths of the reference 1PPS signals and outputs eight paths of the reference 1PPS signals to a fourth stage buffer;
the fourth stage buffer receives eight of the reference 1PPS signals and outputs sixteen of the reference 1PPS signals.
Optionally, the comparing M to-be-detected 1PPS signals and M reference 1PPS signals to obtain a comparison result includes:
matching the M to-be-detected 1PPS signals with the M reference 1PPS signals, so that each to-be-detected 1PPS signal corresponds to each reference 1PPS signal;
and comparing the phase of the to-be-detected 1PPS signal with the phase of the corresponding reference 1PPS signal to obtain a comparison result.
Optionally, the comparing the phase of the to-be-detected 1PPS signal with the phase of the reference 1PPS signal to obtain a comparison result includes:
when the first phase difference is smaller than or equal to a preset first threshold value, acquiring a first comparison result; the first phase difference is a time difference of rising edges of the to-be-measured 1PPS signal and the corresponding reference 1PPS signal;
and when the first phase difference is larger than the preset first threshold value, acquiring a second comparison result.
Optionally, when the first phase difference is smaller than or equal to a preset first threshold value, and a first comparison result is obtained, obtaining the time precision of each to-be-measured 1PPS signal according to the comparison result includes:
performing a first compensation on the first phase difference based on the first comparison result;
and acquiring the time precision of the 1PPS signal to be detected according to the 1PPS signal to be detected subjected to the first compensation and the corresponding reference 1PPS signal.
Optionally, when the first phase difference is greater than the first preset threshold and a second comparison result is obtained, obtaining the time precision of each to-be-measured 1PPS signal according to the comparison result includes:
performing a second compensation on the first phase difference based on the second comparison result;
acquiring a phase difference between the to-be-detected 1PPS signal subjected to second compensation and the corresponding reference 1PPS signal, and taking the phase difference as a second phase difference;
performing third compensation on the second phase difference;
and acquiring the time precision of the 1PPS signal to be detected according to the 1PPS signal to be detected subjected to the third compensation and the corresponding reference 1PPS signal.
The embodiment of the invention also provides a device for testing the time precision of the 1PPS signal, which comprises:
the device comprises an acquisition module, a processing module and a processing module, wherein the acquisition module is used for acquiring M to-be-detected 1PPS signals and M reference 1PPS signals; wherein the M reference 1PPS signals are output by a reference unit through a multi-stage buffer;
the comparison module is used for comparing the M to-be-detected 1PPS signals with the M reference 1PPS signals to obtain a comparison result;
and the determining module is used for acquiring the time precision of each to-be-detected 1PPS signal according to the comparison result.
The embodiment of the invention also provides a system for testing the time accuracy of the 1PPS signal, which comprises:
the first processing unit is used for acquiring M reference 1PPS signals and M to-be-detected 1PPS signals; the device is also used for comparing the M to-be-detected 1PPS signals with the M reference 1PPS signals to obtain a comparison result; the device is also used for acquiring the time precision of each to-be-detected 1PPS signal according to the comparison result;
the reference unit is respectively connected with the first processing unit and a multi-stage buffer, the M reference 1PPS signals are output by the reference unit through the multi-stage buffer, and the multi-stage buffers are connected in a cascade manner;
the unit to be tested is connected with the first processing unit and comprises M terminals and is used for outputting the M1 PPS signals to be tested;
and the second processing unit is connected with the first processing unit and is used for compensating the phase differences of the M to-be-detected 1PPS signals and the M reference 1PPS signals.
Optionally, the reference unit at least includes a first-stage buffer, a second-stage buffer, a third-stage buffer, and a fourth-stage buffer connected in cascade;
the first stage buffer comprises a buffer;
the second-stage buffer comprises two buffers connected;
the third-stage buffer comprises four connected buffers;
the fourth stage buffer includes eight buffers connected.
Optionally, the reference unit is connected to the first-stage buffer through a voltage divider circuit, the voltage divider circuit includes a first resistor and a second resistor, a first end of the first resistor is connected to the reference unit, a second end of the first resistor is connected to the first end of the second resistor and the first-stage buffer, and a second end of the second resistor is grounded.
An embodiment of the present invention also provides a computer storage medium having a computer program stored thereon, wherein the computer program is configured to implement the above-mentioned method when executed by a processor.
The embodiment of the invention has the following technical effects:
according to the technical scheme, 1) the reference unit only needs 1 atomic clock, and can test at least 16 to-be-tested 1PPS signals sent by 16 terminals at one time, so that the test efficiency is greatly improved, the test cost is reduced, and the mass production line test is realized.
2) The reference unit is connected with the first-stage buffer through a voltage division circuit, so that the reference pulse amplitude of the output of the atomic clock can not change along with the change of load impedance.
3) By using the STM32H743 series single chip microcomputer with the high-precision timer to replace an oscilloscope, batch testing can be realized, the cost of the oscilloscope is saved, and the test environment is simple to build.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
FIG. 1 is a schematic flow chart of a method for testing the time accuracy of a 1PPS signal according to an embodiment of the invention;
FIG. 2 is a block flow diagram of a method for testing the time accuracy of a 1PPS signal according to an embodiment of the invention;
FIG. 3 is a schematic diagram of the output paths of M reference 1PPS signals according to an embodiment of the invention;
FIG. 4 is a schematic diagram of a path of a buffer receiving signals and outputting signals according to an embodiment of the present invention;
fig. 5 is a schematic flow chart of compensating for a phase difference according to an embodiment of the present invention.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are illustrative and intended to be illustrative of the invention and are not to be construed as limiting the invention.
The 1PPS (pulse Per second) mentioned in the invention refers to pulse Per second, UART/USB is a universal serial data bus, STM32H743 is a type of a singlechip; HRTIM refers to a high precision timer; TIMERA refers to a timer; TIM3 refers to a first universal timer; TIM4 refers to a second universal timer.
The embodiment of the invention provides a system for testing the time precision of a 1PPS signal, which comprises: the device comprises a first processing unit, a reference unit, a unit to be tested and a second processing unit, wherein the reference unit is respectively connected with the first processing unit and the multi-stage buffer; in conjunction with the present system, as shown in fig. 1, an embodiment of the present invention provides a method for testing the time accuracy of a 1PPS signal, comprising:
step S1: acquiring M to-be-detected 1PPS signals and M reference 1PPS signals; wherein the M reference 1PPS signals are output by a reference unit through a multi-stage buffer;
specifically, the reference unit comprises an atomic clock, wherein the atomic clock outputs a reference 1PPS signal, and outputs M reference 1PPS signals through a multi-stage buffer; the unit to be tested comprises M terminals, and the M terminals output M signals of 1PPS to be tested; the first processing unit obtains M signals of 1PPS to be measured and M signals of reference 1 PPS.
Wherein M is a positive integer of 16 or more, and M may be 32, 64, or the like.
Step S2: comparing the M to-be-detected 1PPS signals with the M reference 1PPS signals to obtain a comparison result;
specifically, the first processing unit may match M to-be-detected 1PPS signals and M to-be-referred 1PPS signals one by one at random, and compare the to-be-detected 1PPS signal with the corresponding reference signal to obtain a phase difference between the two signals (which may be understood as a time difference occurring at a rising edge of the to-be-detected 1PPS signal and the corresponding to-be-referred 1PPS signal) as a comparison result; obtaining M phase differences as M comparison results; wherein, first processing unit can be STM32H743 singlechip, uses STM32H743 series to take the singlechip of high accuracy timer to replace oscilloscope, can practice thrift the cost, realizes that test in batches and test environment build simply.
Step S3: and acquiring the time precision of each to-be-detected 1PPS signal according to the comparison result.
Specifically, the first processing unit may compare the comparison result of each to-be-measured 1PPS signal with a preset accuracy standard, and further determine the time accuracy (e.g., good accuracy, general accuracy, poor accuracy, etc.) of each to-be-measured 1PPS signal.
According to the embodiment of the invention, the reference unit can test at least 16 to-be-tested 1PPS signals sent by 16 terminals at one time only by 1 atomic clock, so that the test efficiency and the accuracy of the time precision of the to-be-tested 1PPS signals are greatly improved, the test cost is reduced, and the mass production line test is realized.
Referring to fig. 2, in an alternative embodiment of the present invention, in step S1:
step S11: the multi-stage buffers at least comprise a first-stage buffer, a second-stage buffer, a third-stage buffer and a fourth-stage buffer, and the first-stage buffer, the second-stage buffer, the third-stage buffer and the fourth-stage buffer are connected in a cascade manner;
step S12: and the reference unit outputs one path of the reference 1PPS signals through the multistage buffers, sequentially passes through the first-stage buffer, the second-stage buffer, the third-stage buffer and the fourth-stage buffer, and outputs sixteen paths of the reference 1PPS signals to the first processing unit.
In the embodiment of the invention, the multi-stage buffers are arranged for cascade connection, so that the atomic clock inputs one path of reference 1PPS signals to the multi-stage buffers and outputs sixteen paths of reference 1PPS signals to the first processing unit, thereby greatly saving the testing efficiency.
As shown in fig. 3 and 4, in an optional embodiment of the present invention, in step S12, the outputting of the reference 1PPS signal by the reference unit sequentially passes through the first stage buffer, the second stage buffer, the third stage buffer, and the fourth stage buffer, and outputs sixteen reference 1PPS signals to the first processing unit includes:
step S121: the first-stage buffer receives one path of the reference 1PPS signals input by the reference unit and outputs two paths of the reference 1PPS signals to the second-stage buffer;
step S122: the second-stage buffer receives the two paths of reference 1PPS signals and outputs four paths of reference 1PPS signals to a third-stage buffer;
step S123: the third stage buffer receives four paths of the reference 1PPS signals and outputs eight paths of the reference 1PPS signals to a fourth stage buffer;
step S124: the fourth stage buffer receives eight paths of the reference 1PPS signals and outputs sixteen paths of the reference 1PPS signals to the first processing unit.
In the embodiment of the invention, the buffers in each stage of buffer are connected in series or in parallel, so that the buffers in each stage of buffer can simultaneously transmit and receive signals, and further, the input of one path of reference 1PPS signals and the output of sixteen paths of reference 1PPS signals are realized through the cascade frequency division of a plurality of buffers.
In an optional embodiment of the present invention, in step S2, the comparing M to-be-measured 1PPS signals and M reference 1PPS signals to obtain a comparison result includes:
step S21: the first processing unit may match the M to-be-measured 1PPS signals with the M reference 1PPS signals, so that each of the to-be-measured 1PPS signals corresponds to each of the reference 1PPS signals;
step S22: and the first processing unit compares the phase of each to-be-detected 1PPS signal with the phase of the corresponding reference 1PPS signal to obtain a comparison result.
Specifically, the first processing unit may include M STM32H743 singlechips, each of which compares, by using a high-precision timer, phases of a set of signals (it is understood that a set of signals includes a 1PPS signal to be measured and a reference 1PPS signal corresponding to the signal), and obtains a phase difference between the two signals (it is understood that a time difference between rising edges of the 1PPS signal to be measured and the corresponding reference 1PPS signal occurs) as a first phase difference of the set. For example, when M is 16, each of the 16 singlechips acquires a phase difference of a group of signals as a first phase difference, and acquires 16 first phase differences in total.
When the first phase difference is smaller than or equal to a preset first threshold value, the first processing unit acquires a first comparison result, namely the first comparison result is that the first phase difference is smaller than or equal to the preset first threshold value;
when the first phase difference is larger than the preset first threshold value, the first processing unit acquires a second comparison result, namely the second comparison result is that the first phase difference is larger than the preset first threshold value; in an example, the first threshold value may be preset to be 1000ns corresponding to the accuracy level of the high accuracy timer.
In an optional embodiment of the present invention, in step S3, when the first phase difference is smaller than or equal to a preset first threshold value and a first comparison result is obtained, the obtaining, according to the comparison result, the time precision of each to-be-measured 1PPS signal includes:
step S31: performing a first compensation on the first phase difference based on the first comparison result;
step S32: and acquiring the time precision of the 1PPS signal to be detected according to the 1PPS signal to be detected subjected to the first compensation and the corresponding reference 1PPS signal.
Specifically, based on the first comparison result, the first processing unit sends the 1PPS signal to be measured, the reference 1PPS signal corresponding to the signal and the first phase difference corresponding to the signal to be measured to the second processing unit, the second processing unit performs first compensation on the 1PPS signal to be measured based on the first phase difference, and feeds back the 1PPS signal to be measured after the first compensation to the first processing unit; the first processing unit acquires the time precision of the to-be-detected 1PPS signal according to the to-be-detected 1PPS signal subjected to the first compensation and the corresponding reference 1PPS signal; the second processing unit can be an upper computer.
In an optional embodiment of the present invention, in step S3, when the first phase difference is greater than the first preset threshold and a second comparison result is obtained, the obtaining the time precision of each to-be-measured 1PPS signal according to the comparison result includes:
step S33: performing a second compensation on the first phase difference based on the second comparison result;
step S34: and acquiring the phase difference between the to-be-detected 1PPS signal and the corresponding reference 1PPS signal after second compensation to serve as a second phase difference.
Specifically, based on the second comparison result, the first processing unit sends the 1PPS signal to be measured, the reference 1PPS signal corresponding to the signal and the first phase difference corresponding to the signal to be measured to the second processing unit, the second processing unit performs second compensation on the 1PPS signal to be measured based on the first phase difference, and feeds back the 1PPS signal to be measured after the second compensation to the first processing unit;
more specifically, based on the second comparison result, the first processing unit may be switched from the high-precision timer to the ordinary timer, and the phase difference between the to-be-measured 1PPS signal and the corresponding reference 1PPS signal is obtained again, and sent to the second processing unit as the updated first phase difference; the second processing unit carries out second compensation on the to-be-detected 1PPS signal based on the updated first phase difference, and feeds the to-be-detected 1PPS signal subjected to the second compensation back to the first processing unit;
the first processing unit obtains the phase difference between the to-be-detected 1PPS signal subjected to the second compensation and the corresponding reference 1PPS signal through a high-precision timer to serve as a second phase difference;
step S35: performing third compensation on the second phase difference;
step S36: and acquiring the time precision of the 1PPS signal to be detected according to the 1PPS signal to be detected subjected to the third compensation and the corresponding reference 1PPS signal.
Specifically, the first processing unit sends the second phase difference to the second processing unit, the second processing unit performs third compensation on the to-be-measured 1PPS signal based on the second phase difference, and feeds the to-be-measured 1PPS signal subjected to the third compensation back to the first processing unit;
and the first processing unit acquires the time precision of the to-be-detected 1PPS signal according to the to-be-detected 1PPS signal subjected to the third compensation and the corresponding reference 1PPS signal.
The single chip microcomputer captures a group of signals through the high-precision timer, calculates a first phase difference of the group of signals, judges whether the first phase difference is within 1000ns of a preset first threshold value, if not, the single chip microcomputer captures the signals, the high-precision timer is switched into a common timer, the first phase difference of the two signals is obtained again, then the group of signals is input into the second processing unit, the second processing unit carries out compensation correction on the obtained first phase difference again, and M to-be-measured 1PPS signals and M corresponding reference 1PPS signals after second compensation are obtained.
The single chip microcomputer recaptures the M to-be-detected 1PPS signals and the corresponding M reference 1PPS signals after second compensation through the high-precision timer, calculates a second phase difference, sends the M to-be-detected 1PPS signals and the corresponding M reference 1PPS signals to the second processing unit after the second compensation, compensates the second phase difference through the second processing unit, obtains the M to-be-detected 1PPS signals and the corresponding M reference 1PPS signals after the third compensation, sends the signals to the single chip microcomputer, and obtains the time precision of the to-be-detected 1PPS signals through the single chip microcomputer.
According to the embodiment of the invention, the phase difference is acquired by the timers with different accuracies and is compensated for multiple times, so that the detection accuracy is increased.
As shown in fig. 5, the above technical solution of the embodiment of the present invention can be implemented as follows:
whether detection terminal and atomic clock phase difference time are greater than 1000ns, if first phase difference is less than or equal to 1000ns, HRTIM's first TIMERA passageway detects atomic clock 1PPS signal rising edge, HRTIM's second TIMERA passageway detects 1PPS signal rising edge (precision can be 2.5ns) that awaits measuring, upload to computer host computer through UART or USB with first phase difference, carry out first compensation to the time difference that the rising edge appears by computer host computer, computer host computer obtains 1PPS signal rising edge and atomic clock 1PPS signal rising edge that awaits measuring after the first compensation, and send to the singlechip, print out 1PPS signal time precision that awaits measuring through the singlechip.
2) On the contrary, if the first phase difference is greater than 1000ns, the TIM3 detects the rising edge of the atomic clock 1PPS signal and the TIM4 detects the rising edge of the to-be-detected 1PPS signal, and calculates the first phase difference (the precision may be 1 μ s) between the rising edge of the atomic clock 1PPS signal and the rising edge of the to-be-detected 1PPS signal; and carrying out second compensation on the time difference of the rising edge by the upper computer, acquiring the rising edge of the 1PPS signal to be detected and the rising edge of the 1PPS signal of the atomic clock after the second compensation by the upper computer, sending the rising edge to the singlechip, printing a second phase difference of the rising edge of the 1PPS signal to be detected and the rising edge of the 1PPS signal of the atomic clock after the second compensation by the singlechip, uploading the second phase difference to the upper computer through a Universal Asynchronous Receiver Transmitter (UART) or a Universal Serial Bus (USB), and sending a switching high-precision timer detection command to the singlechip by the upper computer.
HRTIM's first TIMERA passageway detects atomic clock 1PPS signal rising edge, HRTIM's second TIMERA passageway detects 1PPS signal rising edge (precision 2.5ns) that awaits measuring, carry out the third compensation to the time difference that the rising edge appears by the computer host computer, the computer host computer acquires 1PPS signal rising edge and the 1PPS signal rising edge of atomic clock that awaits measuring after the third compensation, and send to the singlechip, print out 1PPS signal time precision that awaits measuring through the singlechip.
The embodiment of the invention also provides a device for testing the time precision of the 1PPS signal, which comprises:
the device comprises an acquisition module, a processing module and a processing module, wherein the acquisition module is used for acquiring M to-be-detected 1PPS signals and M reference 1PPS signals; wherein the M reference 1PPS signals are output by a reference unit through a multi-stage buffer;
the comparison module is used for comparing the M to-be-detected 1PPS signals with the M reference 1PPS signals to obtain a comparison result;
and the determining module is used for acquiring the time precision of each to-be-detected 1PPS signal according to the comparison result.
It is understood that this embodiment is an embodiment of an apparatus corresponding to the foregoing method embodiment, and the functions of the modules are not described herein again.
The embodiment of the invention also provides a system for testing the time accuracy of the 1PPS signal, which comprises:
a first processing unit; the device is used for acquiring M reference 1PPS signals and M to-be-detected 1PPS signals; the device is also used for comparing the M to-be-detected 1PPS signals with the M reference 1PPS signals to obtain a comparison result; the device is also used for acquiring the time precision of each to-be-detected 1PPS signal according to the comparison result;
the reference unit is respectively connected with the first processing unit and a multi-stage buffer, the M reference 1PPS signals are output by the reference unit through the multi-stage buffer, and the multi-stage buffers are connected in a cascade manner;
the unit to be tested is connected with the first processing unit and comprises M terminals and is used for outputting the M1 PPS signals to be tested;
and the second processing unit is connected with the first processing unit and is used for compensating the phase differences of the M to-be-detected 1PPS signals and the M reference 1PPS signals.
Wherein M is a positive integer of 16 or more; it is understood that this embodiment is a system embodiment corresponding to the foregoing method embodiment, and the functions of each unit are not described herein again.
In an optional embodiment of the present invention, the reference unit at least includes a first-stage buffer, a second-stage buffer, a third-stage buffer, and a fourth-stage buffer connected in cascade;
the first stage buffer comprises a buffer;
the second-stage buffer comprises two buffers connected;
the third-stage buffer comprises four connected buffers;
the fourth stage buffer includes eight buffers connected.
In the embodiment of the invention, the buffers in each stage of buffer are connected in series or in parallel, so that each stage of buffer can simultaneously transmit and receive the reference 1PPS signal.
In an optional embodiment of the present invention, the reference unit is connected to the first stage buffer through a voltage dividing circuit, the voltage dividing circuit includes a first resistor and a second resistor, a first end of the first resistor is connected to the reference unit, a second end of the first resistor is connected to a first end of the second resistor and the first stage buffer, respectively, and a second end of the second resistor is grounded.
Specifically, the effective current and voltage of the multi-stage buffer are reduced through the voltage division circuit, and the influence of load change on the amplitude of the output signal of the atomic clock is reduced.
In the embodiment of the invention, the reference unit is connected with the first-stage buffer through the voltage division circuit, so that the reference pulse amplitude of the output of the atomic clock does not change along with the change of the load impedance.
In addition, other configurations and functions of the system according to the embodiment of the present invention are known to those skilled in the art, and are not described herein in detail to reduce redundancy.
An embodiment of the present invention also provides a computer storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the above-described method of testing the time accuracy of a 1PPS signal.
It should be noted that the logic and/or steps represented in the flowcharts or otherwise described herein, such as an ordered listing of executable instructions that can be considered to implement logical functions, can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions.
It should be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the various steps or methods may be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any one or combination of the following techniques, which are known in the art, may be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
In the description of the present invention, it is to be understood that the terms "central," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the invention and to simplify the description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and are therefore not to be considered limiting of the invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the present invention, unless otherwise expressly stated or limited, the first feature "on" or "under" the second feature may be directly contacting the first and second features or indirectly contacting the first and second features through an intermediate. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.
Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.
Claims (12)
1. A method of testing the time accuracy of a 1PPS signal, comprising:
acquiring M to-be-detected 1PPS signals and M reference 1PPS signals; wherein the M reference 1PPS signals are output by a reference unit through a multi-stage buffer;
comparing the M to-be-detected 1PPS signals with the M reference 1PPS signals to obtain a comparison result;
and acquiring the time precision of each to-be-detected 1PPS signal according to the comparison result.
2. The method of claim 1, wherein the multi-stage buffers comprise at least a first stage buffer, a second stage buffer, a third stage buffer, and a fourth stage buffer, the first stage buffer, the second stage buffer, the third stage buffer, and the fourth stage buffer being connected in cascade;
and the reference unit outputs one path of reference 1PPS signals through the multistage buffers, sequentially passes through the first-stage buffer, the second-stage buffer, the third-stage buffer and the fourth-stage buffer, and outputs sixteen paths of reference 1PPS signals.
3. The method of claim 2, wherein the outputting of the reference 1PPS signal from the reference unit via the multi-stage buffer comprises outputting sixteen reference 1PPS signals via the first stage buffer, the second stage buffer, the third stage buffer, and the fourth stage buffer in sequence, and comprises:
the first-stage buffer receives one path of the reference 1PPS signals input by the reference unit and outputs two paths of the reference 1PPS signals to the second-stage buffer;
the second-stage buffer receives the two paths of reference 1PPS signals and outputs four paths of reference 1PPS signals to a third-stage buffer;
the third stage buffer receives four paths of the reference 1PPS signals and outputs eight paths of the reference 1PPS signals to a fourth stage buffer;
the fourth stage buffer receives eight of the reference 1PPS signals and outputs sixteen of the reference 1PPS signals.
4. The method of claim 1, wherein comparing the M to-be-measured 1PPS signals with the M reference 1PPS signals to obtain a comparison result comprises:
matching the M to-be-detected 1PPS signals with the M reference 1PPS signals, so that each to-be-detected 1PPS signal corresponds to each reference 1PPS signal;
and comparing the phase of the to-be-detected 1PPS signal with the phase of the corresponding reference 1PPS signal to obtain a comparison result.
5. The method of claim 4, wherein comparing the phases of the to-be-measured 1PPS signal and the corresponding reference 1PPS signal to obtain a comparison result comprises:
when the first phase difference is smaller than or equal to a preset first threshold value, acquiring a first comparison result; the first phase difference is a time difference of rising edges of the to-be-measured 1PPS signal and the corresponding reference 1PPS signal;
and when the first phase difference is larger than the preset first threshold value, acquiring a second comparison result.
6. The method according to claim 5, wherein when the first phase difference is less than or equal to a preset first threshold value and a first comparison result is obtained, the obtaining the time precision of each of the to-be-measured 1PPS signals according to the comparison result comprises:
performing a first compensation on the first phase difference based on the first comparison result;
and acquiring the time precision of the 1PPS signal to be detected according to the 1PPS signal to be detected subjected to the first compensation and the corresponding reference 1PPS signal.
7. The method according to claim 5, wherein when obtaining a second comparison result when the first phase difference is greater than the first preset threshold, obtaining the time accuracy of each of the to-be-measured 1PPS signals according to the comparison result comprises:
performing a second compensation on the first phase difference based on the second comparison result;
acquiring a phase difference between the to-be-detected 1PPS signal subjected to second compensation and the corresponding reference 1PPS signal, and taking the phase difference as a second phase difference;
performing third compensation on the second phase difference;
and acquiring the time precision of the 1PPS signal to be detected according to the 1PPS signal to be detected subjected to the third compensation and the corresponding reference 1PPS signal.
8. An apparatus for testing the time accuracy of a 1PPS signal, comprising:
the device comprises an acquisition module, a processing module and a processing module, wherein the acquisition module is used for acquiring M to-be-detected 1PPS signals and M reference 1PPS signals; wherein the M reference 1PPS signals are output by a reference unit through a multi-stage buffer;
the comparison module is used for comparing the M to-be-detected 1PPS signals with the M reference 1PPS signals to obtain a comparison result;
and the determining module is used for acquiring the time precision of each to-be-detected 1PPS signal according to the comparison result.
9. A system for testing the time accuracy of a 1PPS signal, comprising:
the first processing unit is used for acquiring M reference 1PPS signals and M to-be-detected 1PPS signals; the device is also used for comparing the M to-be-detected 1PPS signals with the M reference 1PPS signals to obtain a comparison result; the device is also used for acquiring the time precision of each to-be-detected 1PPS signal according to the comparison result;
the reference unit is respectively connected with the first processing unit and a multi-stage buffer, the M reference 1PPS signals are output by the reference unit through the multi-stage buffer, and the multi-stage buffers are connected in a cascade manner;
the unit to be tested is connected with the first processing unit and comprises M terminals and is used for outputting the M1 PPS signals to be tested;
and the second processing unit is connected with the first processing unit and is used for compensating the phase differences of the M to-be-detected 1PPS signals and the M reference 1PPS signals.
10. The system of claim 9, wherein the reference unit comprises at least a first stage buffer, a second stage buffer, a third stage buffer, and a fourth stage buffer connected in cascade;
the first stage buffer comprises a buffer;
the second-stage buffer comprises two buffers connected;
the third-stage buffer comprises four connected buffers;
the fourth stage buffer includes eight buffers connected.
11. The system of claim 10, wherein the reference cell is connected to the first stage buffer through a voltage divider circuit, the voltage divider circuit comprising a first resistor and a second resistor, a first end of the first resistor being connected to the reference cell, a second end of the first resistor being connected to a first end of the second resistor and the first stage buffer, respectively, and a second end of the second resistor being connected to ground.
12. A computer storage medium on which a computer program is stored, which computer program, when being executed by a processor, carries out the method according to any one of claims 1 to 7.
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