CN113852533B - Multi-channel data communication system and method and electronic equipment - Google Patents
Multi-channel data communication system and method and electronic equipment Download PDFInfo
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- CN113852533B CN113852533B CN202111137671.9A CN202111137671A CN113852533B CN 113852533 B CN113852533 B CN 113852533B CN 202111137671 A CN202111137671 A CN 202111137671A CN 113852533 B CN113852533 B CN 113852533B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40006—Architecture of a communication node
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B7/00—Radio transmission systems, i.e. using radiation field
- H04B7/14—Relay systems
- H04B7/15—Active relay systems
- H04B7/185—Space-based or airborne stations; Stations for satellite systems
- H04B7/1851—Systems using a satellite or space-based relay
- H04B7/18515—Transmission equipment in satellites or space-based relays
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L2012/40208—Bus networks characterized by the use of a particular bus standard
- H04L2012/40215—Controller Area Network CAN
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The application discloses a multichannel data communication system, a method and an electronic device, wherein the system comprises: the dynamic cache node receives bus data from different external nodes through a first bus; for each external node, the dynamic cache node performs the following: determining a cache address corresponding to the external node indicated by the external node identification, and storing the valid data in the determined cache address; the dynamic cache node determines a target cache address; the dynamic cache node generates an interrupt trigger signal and sends the interrupt trigger signal to the microcontroller; and the microcontroller reads valid data from the target cache address based on the interrupt trigger signal. By adopting the multi-channel data communication system, the multi-channel data communication method and the electronic equipment, the problems that when a certain node on the CAN bus is in data communication with a plurality of external nodes, the data processing process of the microcontroller is delayed and the response of the node equipment is delayed due to the large number of the external nodes and the large data interaction amount are solved.
Description
Technical Field
The present application relates to the field of data processing technologies, and in particular, to a multi-channel data communication system, a method, and an electronic device.
Background
A Controller Area Network (CAN) is a serial communication field bus, and is primarily used for data communication between a plurality of control and measurement instruments in an automobile, and with the application and popularization of the CAN bus, the CAN bus has the advantages of good real-time performance, high reliability, strong anti-interference capability and the like, is also recognized by the aerospace field, and is widely applied to the aerospace field. The CAN bus is introduced into an integrated electronic system at home and abroad, and a large number of micro satellites use the CAN bus as an on-satellite backbone network to complete information interaction between on-satellite equipment.
In the prior art, when a satellite device is used as a certain node on a CAN bus to process data receiving tasks of a plurality of other nodes, the node is generally regarded as a master control node, the plurality of other nodes are regarded as external nodes, and a microcontroller of the master control node is responsible for receiving, processing and distributing various data from the external nodes. If the data of a certain external node A is received and processed by the main control node, another external node B starts to send data to the main control node through the bus, and at the moment, the microcontroller of the main control node interrupts the data processing process of the external node A and receives the data sent by the external node B instead.
In the above data communication mode, if there are many external nodes on the CAN bus and a large amount of data interaction is performed between the external nodes and the master control node, the data processing process of the microcontroller is frequently interrupted, which results in problems of data processing process lag of the microcontroller and node device response delay.
Disclosure of Invention
In view of the above, the present application provides a multi-channel data communication system, method and electronic device, and aims to implement that data sent by different external nodes are stored in corresponding independent caches through dynamic cache nodes independent of a microcontroller, and a single reception interrupt CAN be implemented by using an indefinite-length data packet protocol to complete reception of a whole packet of data, thereby solving the problems of data processing process lag of the microcontroller and response delay of node devices due to a large number of external nodes and large data interaction amount when a certain node on a CAN bus communicates with a plurality of external nodes.
In a first aspect, an embodiment of the present application provides a multi-channel data communication system, including a dynamic cache node and a microcontroller;
the dynamic cache node receives bus data from different external nodes through a first bus, wherein the bus data comprises external node identification and effective data;
for each external node, the dynamic cache node performs the following: determining a cache address corresponding to the external node indicated by the external node identification, and storing the valid data in the determined cache address;
the dynamic cache node determines a target cache address, wherein the target cache address is a cache address at which the total data length of effective data stored in the cache address corresponding to each external node reaches the length of a target data packet;
the dynamic cache node generates an interrupt trigger signal and sends the interrupt trigger signal to the microcontroller, wherein the interrupt trigger signal is used for indicating that the dynamic cache node has a whole packet of data to be read, and the data is received from an external node;
and the microcontroller reads valid data from the target cache address based on the interrupt trigger signal.
Optionally, the dynamic cache node may further perform the following processing: after determining the target cache address, pointing the interrupt read address to the target cache address; wherein, the microcontroller can also execute the following processing: and responding to the interrupt trigger signal, reading the target cache address pointed by the address based on the interrupt, and reading the valid data from the target cache address.
Optionally, the bus data may include a single frame header and a single frame data, the single frame header may include an external node identifier, the single frame data may include a frame sequence number and a valid data range, and the dynamic cache node may determine and store the target packet length by: extracting a frame number from the received bus data; determining whether the received bus data is a first frame based on the frame sequence number; if the frame is the first frame, the target data packet length is read from the first bit of the effective data range, and the target data packet length is stored to the data packet length address.
Optionally, the microcontroller may also perform the following: reading the packet length from the packet length address; determining the data reading times according to the length of the data packet; and reading valid data from the target cache address according to the data reading times.
Optionally, the other bits except the first bit in the valid data range of the first frame of bus data may be used to store valid data, and each bit in the valid data range of the bus data not in the first frame is used to store valid data.
Optionally, the dynamic cache node may include a first bus interface, a second bus interface, and an interrupt interface, wherein the dynamic cache node may receive bus data from different external nodes through the first bus interface, and the dynamic cache node may be connected to the bus interface of the microcontroller through the second bus interface to transmit valid data via the second bus interface; the dynamic cache node may be connected to an interrupt trigger pin of the microcontroller through an interrupt interface to send an interrupt trigger signal to the microcontroller through the interrupt interface.
Optionally, the dynamic cache node may include a processing unit, a bus control unit, and a bus transceiver; the processing unit can be connected to a bus interface of the microcontroller through a second bus interface, the processing unit is connected to a first bus data interface of the bus control unit through the first bus interface, a second bus data interface of the bus control unit is connected to a third bus data interface of the bus transceiver, a fourth bus data interface of the bus transceiver receives bus data from different external nodes, and the processing unit is connected to an interrupt trigger pin of the microcontroller through an interrupt interface.
Optionally, the bus control unit may receive bus data of a target length from different external nodes through the first bus each time, and generate a hardware reception interrupt; the processing unit senses whether the level of the hardware receiving interrupt pin changes in real time; and if the level of the hardware receiving interrupt pin is induced to change, the processing unit reads the bus data from the bus control unit and stores the effective data in the bus data into the corresponding cache address.
In a second aspect, an embodiment of the present application provides a data synchronization apparatus, including:
receiving bus data from different external nodes through a first bus, wherein the bus data comprises external node identification and valid data;
for each external node, determining a cache address corresponding to the external node indicated by the external node identification, and storing effective data in the determined cache address;
determining a target cache address, wherein the target cache address is a cache address at which the total data length of effective data stored in the cache address corresponding to each external node reaches the length of a target data packet;
and generating an interrupt trigger signal, and sending the interrupt trigger signal to the microcontroller so that the microcontroller reads valid data from a target cache address based on the interrupt trigger signal, wherein the interrupt trigger signal is used for indicating that the dynamic cache node has a whole packet of data to be read, and the whole packet of data is received from an external node.
In a third aspect, an embodiment of the present application provides an electronic device, including: a processor, a memory and a bus, the memory storing machine-readable instructions executable by the processor, the processor and the memory communicating over the bus when the electronic device is operating, the machine-readable instructions when executed by the processor performing the steps of the multi-channel data communication system as described above.
The embodiment of the application brings the following beneficial effects:
the embodiment of the application provides a multi-channel data communication system, a multi-channel data communication method and electronic equipment, wherein the multi-channel data communication system comprises a dynamic cache node and a microcontroller; the dynamic cache node receives bus data from different external nodes through a first bus, wherein the bus data comprises external node identification and effective data; for each external node, the dynamic cache node performs the following: determining a cache address corresponding to the external node indicated by the external node identification, and storing the valid data in the determined cache address; the dynamic cache node determines a target cache address, wherein the target cache address is a cache address at which the total data length of effective data stored in the cache address corresponding to each external node reaches the length of a target data packet; the dynamic cache node generates an interrupt trigger signal and sends the interrupt trigger signal to the microcontroller, wherein the interrupt trigger signal is used for indicating that the dynamic cache node has the whole packet of data to be read, and the whole packet of data is received from an external node. When a certain node on the CAN bus communicates with a plurality of external nodes, the data processing process of the microcontroller is delayed and the response of node equipment is delayed due to the large number of the external nodes and the large data interaction amount.
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments are briefly described below, and it is obvious that the following drawings are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other related drawings without creative efforts.
FIG. 1 is a schematic diagram of a prior art multi-channel data communication system;
fig. 2 is a schematic structural diagram of a multi-channel data communication system according to an embodiment of the present application;
FIG. 3 is a schematic diagram of processing unit algorithm and data transfer provided by an embodiment of the present application;
fig. 4 is a schematic hardware structure diagram of a dynamic cache node according to an embodiment of the present application;
fig. 5 is a schematic flowchart of a multi-channel data communication method according to an embodiment of the present application;
fig. 6 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
To make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions of the present application will be clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the prior art, when a satellite device is used as a certain node on a CAN bus to process data receiving tasks of a plurality of other nodes, the node is usually used as a main control node, the plurality of other nodes are used as external nodes, and a microcontroller of the main control node is responsible for receiving, processing and distributing various data from the external nodes. If the data of a certain external node A is received and processed by the main control node, another external node B starts to send data to the main control node through the bus, and at the moment, the microcontroller of the main control node interrupts the data processing process of the external node A and receives the data sent by the external node B instead.
Fig. 1 is a schematic structural diagram of a multi-channel data communication system in the prior art, as shown in fig. 1, a microcontroller with a CAN function directly communicates with a CAN transceiver through a CAN bus and controls the CAN transceiver to receive data, when receiving data from a plurality of external nodes on the CAN bus, since valid data of 8 bytes CAN only be received each time, if the received data volume is large, an interrupt trigger signal is frequently sent to the microcontroller, so that the microcontroller needs to continuously stop a current data processing task and receive data sent by the plurality of external nodes, which may cause problems of data processing task lag of the microcontroller and node device response delay. In addition, since there are many external nodes for sending data, the microcontroller needs to perform complicated processing on the interrupt trigger signal and the cache mode of different external node data, which also increases the algorithm complexity of the microcontroller.
Based on this, embodiments of the present application provide a multi-channel data communication system, method, and electronic device, where data sent by different external nodes is stored in corresponding independent caches through dynamic cache nodes independent of a microcontroller, and a single-time sending of an interrupt trigger signal is realized by using an indefinite-length data packet protocol to complete receiving of a whole packet of data, thereby solving the problems of data processing process lag of the microcontroller and response delay of node devices due to a large number of external nodes and a large amount of data interaction when a certain node on a CAN bus communicates with multiple external nodes.
To facilitate understanding of the present embodiment, first, a multi-channel data communication system disclosed in the embodiment of the present application is described in detail, and fig. 2 is a schematic structural diagram of the multi-channel data communication system provided in the embodiment of the present application, as shown in fig. 2, the multi-channel data communication system 10 includes a dynamic cache node 100 and a microcontroller 200.
Specifically, when data interaction is performed between devices on the satellite, each device may be regarded as a node, each node performs communication through the CAN bus, when a certain node receives bus data from a plurality of external nodes, the node may be regarded as a master node, and the microcontroller 200 of the master node writes data into a plurality of operation addresses through the second bus, so as to control the dynamic cache node 100 to receive the bus data sent by a specific external node. Here, the external node needs to send the bus data according to the indefinite length packet protocol, so that the dynamic cache node 100 of the master node can parse the bus data according to the indefinite length packet protocol.
In an example, the dynamic cache node 100 includes a first bus interface through which the dynamic cache node 100 receives bus data from different external nodes, a second bus interface through which the dynamic cache node 100 is connected to a bus interface of the microcontroller 200 to transmit valid data via the second bus interface, and an interrupt interface; the dynamic cache node 100 is connected to an interrupt trigger pin of the microcontroller 200 through an interrupt interface to transmit an interrupt trigger signal to the microcontroller through the interrupt interface.
Illustratively, the first Bus may be a CAN Bus, the second Bus may be an APB (Advanced Peripheral Bus), the Bus data may be Controller Area Network data (CAN Bus data), a clock frequency of the second Bus is the same frequency as a master frequency of the microcontroller 200, and a communication rate of the second Bus is higher than a communication rate of the first Bus, it CAN be understood that, since the clock frequency of the second Bus is the same frequency as the master frequency of the microcontroller 200, the microcontroller 200 is no longer limited by the baud rate when reading and writing the CAN Bus data, and the efficiency of reading and writing the data of the microcontroller 200 is improved. Through the second bus, the microcontroller 200 may use the multiple offset addresses as operation addresses of each control function, and write the external node identifiers corresponding to the external nodes into the multiple operation addresses, to control the dynamic cache node 100 to receive the bus data sent by the external node indicated by the external node identifier, so that the dynamic cache node 100 can determine whether the external node identifier of the bus data matches with the external node identifier in the operation address, and if the external node identifier of the bus data matches with the external node identifier in the operation address, place the valid data in the bus data into the cache for storage; if the external node identification of the bus data does not match the external node identification in the operation address, the bus data is filtered out.
In one example, the offset address of the plurality of entries is 12 bits, and the upper 8 bits of the address represent the lane number of the different receiving buffers, for example: 0X00X represents the controls for channel 0, 0X1FX represents the controls for channel 31, and X represents the bit uncertainty. The address is 4 bits low, and the following conditions are provided: 0x000 represents a cache data read address; 0x004 indicates the ID value corresponding to the cache channel; 0x008 denotes a target packet length; 0x00C represents the amount of data currently in the cache. In addition, the interrupt read address 0xFF0 indicates a buffer address where the total data length of valid data stored in the buffer address reaches the target packet length, and when the CAN bus dynamic buffer node 100 generates an interrupt trigger signal, the microcontroller 200 is required to read the address 0xFF0 and determine which channel the interrupt trigger signal is sent.
For each external node, the dynamic cache node 100 performs the following processing: and determining a cache address corresponding to the external node indicated by the external node identification, and storing the valid data in the determined cache address.
Specifically, the dynamic cache node 100 includes a processing unit 1001, a bus control unit 1002, and a bus transceiver 1003, where the processing unit 1001 includes a plurality of independent caches with different IDs. Bus data sent by different external nodes can be stored in different independent caches. Here, by using a plurality of offset addresses as operation addresses of each control function, an external node identifier corresponding to valid data received by each independent cache is determined, and each independent cache has a corresponding cache address, so that a cache address corresponding to an external node indicated by the external node identifier is determined.
In an example, the processing unit 1001 is connected to a bus interface of the microcontroller 200 through a second bus interface, the processing unit 1001 is connected to a first bus data interface of the bus control unit 1002 through the first bus interface, a second bus data interface of the bus control unit 1002 is connected to a third bus data interface of the bus transceiver 1003, a fourth bus data interface of the bus transceiver 1003 receives bus data from different external nodes, and the processing unit 1001 is connected to an interrupt trigger pin of the microcontroller 200 through an interrupt interface.
Illustratively, the processing unit 1001 may be a Field Programmable Gate Array (FPGA), the processing unit 1001 is connected to the microcontroller 200 through a second bus, the bus control unit 1002 may be a CAN controller, the bus transceiver 1003 may be a CAN transceiver, the bus control unit 1002 is connected to the bus transceiver 1003 through a first bus, and the processing unit 1001, the bus control unit 1002 and the bus transceiver 1003 together form the dynamic cache node 100. It can be understood that the processing of the bus data is performed by the dynamic cache node 100, and the microcontroller 200 only needs to perform data writing or reading operation on the operation address, which not only simplifies the interrupt processing operation of the microcontroller 200, but also releases the instruction resource of the bus processing consumed by the microcontroller 200 when receiving the bus data. When the processing unit 1001 is used in cooperation with the bus control unit 1002 and the bus transceiver 1003, the external interface only has the CAN bus interfaces CANH and CANL at the bus transceiver end, which is consistent with the interface of the CAN bus realized by the microcontroller 200 by using an internal CAN control algorithm in cooperation with the CAN transceiver in the prior art, and the interface CAN be directly compatible with the node design of the original CAN bus, and has good compatibility.
In an example, the bus data includes a plurality of single frame bus data, each single frame bus data includes a single frame header including the external node identification and a single frame data including a frame sequence number and a valid data range. The following table is an example of an indefinite length packet protocol table provided in an embodiment of the present application.
As shown in the above table, 1-10 indicates that the data bit is in the bit of the byte; IDs 0-10 represent external node identifiers; index indicates a 16-ary frame number; length represents the target packet Length; D0-DXX represent valid data; 00H to XXH are values of frame numbers; the RTR is a remote transmission request bit, is an RTR bit of an arbitration segment in a frame structure of a data frame, and is invariably recessive 1 in the data frame; DLC is used to indicate the number of bytes of data frame, for the indefinite length packet protocol, DLC is used to indicate the number of bytes in single frame bus data except the single frame header, for example: the whole data packet has 8 frames in total, the frame number is from 00H to 07H, except the last frame with the frame number of 07H, the DLC bits of other frames are 8, the numerical value of the DLC bit of the last frame needs to be determined according to the actual situation, and if the last frame comprises 4 bytes of valid data, the DLC bit is 5. The external node sends a plurality of single-frame bus data to the main control node according to the indefinite length data packet protocol, each single-frame bus data comprises a single-frame header and single-frame data, the single-frame header comprises an external node identifier, the external node identifier has 11 bits, each bit can be 0 or 1, the single-frame header can represent 2048 specific external node identifiers of the power of 11 of 2, for the same external node, the external node identifier of each single-frame bus data is the same no matter how many single-frame bus data the bus data are divided into, and the first byte, namely Index bit, of the single-frame data in each single-frame bus data is used for setting a frame sequence number bit in the indefinite length data packet. In the indefinite length packet protocol, a single frame of data includes a frame number and an effective data range, and the effective data range includes a target packet length and effective data. Here, whether the bus data is the first frame or not can be judged through the frame number, the other bits except the first bit in the valid data range of the bus data of the first frame are used for storing valid data, the first bit in the valid data range of the bus data of the first frame is used for storing the target data packet length, and each bit in the valid data range of the bus data of the non-first frame is used for storing valid data, that is, the valid data in the bus data of the first frame is 6 bits, and the valid data in the bus data of the non-first frame is 7 bits.
In an example, the bus control unit 1002 receives bus data of a target length from different external nodes through a first bus each time, generates a hardware reception interrupt, and the processing unit 1001 senses whether the level of a hardware reception interrupt pin changes in real time, and if the level of the hardware reception interrupt pin changes, the processing unit 1001 reads the bus data from the bus control unit 1002 and stores valid data in the bus data in a corresponding cache address. For example: the bus control unit 1002 generates a hardware reception interrupt every time it receives 8 bytes of bus data through the CAN bus, the hardware reception interrupt is not controlled, as long as the bus control unit 1002 receives 8 bytes of bus data, i.e., autonomously generates a level change, where the 8 bytes of bus data is single frame data, which is data excluding a header of a single frame in the bus data. Meanwhile, the processing unit 1001 sets the trigger mode to be falling edge trigger, can sense the level change of the hardware reception interrupt pin in real time, and reads bus data from the bus control unit 1002 if the falling edge from high level to low level of the hardware reception interrupt pin is triggered. After the processing unit 1001 reads the bus data from the bus control unit 1002, it parses the read bus data, extracts the external node identifier, and parses and extracts the frame number, the target packet length, and the valid data of the bus data according to the indefinite length packet protocol. Here, a frame number is extracted from the received bus data, whether the received bus data is a first frame or not can be determined based on the frame number, if so, a target packet length is read from a first bit of the valid data range, the target packet length is stored to a packet length address, and the extracted valid data is placed in the determined buffer address to be stored.
The dynamic cache node 100 determines a target cache address. The target cache address is a cache address at which the total data length of valid data stored in the cache address corresponding to each external node reaches the target packet length.
Specifically, after the processing unit 1001 of the dynamic cache node 100 puts the valid data into the determined cache address for storage, it may determine whether the total data length of the valid data stored in each cache reaches the target packet length, and if the total data length of the valid data stored in the cache reaches the target packet length, determine the address corresponding to the cache as the target cache address. Meanwhile, in order to enable the microcontroller 200 to read valid data from the target cache address, the interrupt read address needs to be pointed to the target cache address to facilitate the microcontroller 200 to obtain the target cache address, and therefore, after determining the target cache address, the processing unit 1001 of the dynamic cache node 100 points the interrupt read address to the target cache address.
The dynamic cache node 100 generates an interrupt trigger signal and sends the interrupt trigger signal to the microcontroller 200, where the interrupt trigger signal is used to indicate that there is a whole packet of data received from an external node in the dynamic cache node to be read.
Specifically, after the dynamic cache node 100 determines the target cache address, the target cache address is written into the interrupt read address, and generates an interrupt trigger signal, and sends the interrupt trigger signal to the microcontroller 200 through the interrupt trigger pin.
Specifically, the microcontroller 200 reads a target buffer address from the interrupt read address and reads valid data from the target buffer address in response to the interrupt trigger signal. Meanwhile, the microcontroller 200 also reads the packet length from the packet length address, determines the data reading times according to the packet length, reads valid data from the target cache address according to the data reading times, where all data in the target cache address can be read into the microcontroller 200 by the interrupt processing function, and then clears the interrupt trigger signal.
It CAN be seen that, when the bus data sent by a certain external node is not completely received, if there are other external nodes sending the bus data on the CAN bus, the master control node may analyze the bus data according to the indefinite length data packet protocol, and store the valid data in the bus data into the corresponding receiving buffer, so that it does not affect the accumulation of the currently uncompleted bus data. When the bus data sent by any external node is received, the corresponding interrupt trigger signal is generated, so that the microcontroller 200 receives complete valid data, and the target data packet lengths and the receiving completion sequence corresponding to the cache channels are independent from each other, thereby not causing delay influence.
The application can obtain the following beneficial effects: the first dynamic cache node is an external device independent of the microcontroller, and for different independent caches, the internal data space of the microcontroller does not need to be called for data distribution, so that the data scheduling design of the microcontroller is simplified. Secondly, for the data packet with indefinite length, the data packet protocol with indefinite length is utilized, the interrupt trigger signal corresponding to the data packet can be sent after the complete data packet is received, the microcontroller only needs to process the single interrupt trigger signal, the complete multiframe effective data can be obtained, and the design of the processing function of the microcontroller for receiving the interrupt is simplified.
It CAN be understood that, through the dynamic cache node independent of the microcontroller, the data sent by different external nodes are stored in the corresponding independent caches, and the receiving of the whole packet of data CAN be completed by sending the interrupt trigger signal once by using the indefinite-length data packet protocol, so that the problems of data processing process lag of the microcontroller and node equipment response delay caused by a large number of external nodes and large data interaction amount when a certain node on the CAN bus communicates with a plurality of external nodes are solved.
Fig. 3 is a schematic diagram of processing unit algorithm and data transmission provided in the embodiment of the present application, and as shown in fig. 3, a CAN dynamic cache node control process is completely implemented by an FPGA, and the implemented main functions include: CAN controller sequential logic, namely the control of the CAN controller; communication bus control, namely control of a communication bus protocol of a microcontroller; the cache and cache controller is used for sending bus data by a plurality of external nodes; and a single frame data analysis function.
Here, the control of the CAN controller by the FPGA includes operating the CAN controller to receive bus data, reading a hardware reception interrupt of a CAN controller chip. The FPGA acquires the bus data, namely after the FPGA acquires the level change of a hardware receiving interrupt pin of the CAN controller, the effective data acquired from the CAN controller is read into a corresponding receiving cache according to an external node identifier.
The CAN dynamic cache node is connected with an upper computer interface connected with the microcontroller by adopting a customized address data bus type interface. Through the bus type interface, the microcontroller CAN directly access the internal cache data, the cached data volume, the target cache address and the target data packet length of the CAN dynamic cache node.
And the cache of CAN bus data is realized by utilizing a FIFO cache mechanism in the FPGA. By means of 32 different independent buffers, 32 different FIFO data inlets are realized, and the received effective data are buffered into different FIFOs by utilizing the data distribution function of the FPGA. For the data packets with indefinite length, the external nodes need to format and send the data packets according to the given protocol of the data packets with indefinite length. The indefinite length packet protocol includes a target packet length and a frame number, and packet packing can be performed based on the target packet length and the frame number.
The single frame data parsing function includes: and (4) the analysis function of the data packet protocol and the extraction of the external node identification.
Fig. 4 is a schematic diagram of a hardware structure of a dynamic cache node according to an embodiment of the present disclosure, and as shown in fig. 4, the processing unit may be an FPGA, the bus control unit may be a chip SJA1000T, and the bus transceiver may be a chip TJA 1040T. Here, in order to adapt to different level standards, level conversion is performed using the chip SN74LVC16T 245. The communication bus connecting the front end of the dynamic cache node and the microcontroller can use APB bus, address bit width 12 bit and data bit width 32 bit. And is designed according to standard APB bus timing.
Therefore, the dynamic cache node adopts the FPGA chip as the main control, and the CAN controller chip is controlled by the FPGA to complete the access process of the CAN bus. The FPGA is connected with the microcontroller, and the CAN controller chip is connected with the CAN transceiver chip and then is connected into the CAN bus. The external interface of the CAN dynamic cache node comprises: a bus interface connected with the microcontroller, an interrupt trigger signal interface, and a CAN _ H, CAN _ L port connected with a CAN bus.
Fig. 5 is a flowchart of a multichannel data communication method provided in an embodiment of the present application, where the multichannel data communication method may be executed in the processing unit 1001 in the multichannel data communication, as shown in fig. 5, the method includes:
in step 301, bus data is received from different external nodes over a first bus. Here, the bus data includes an external node identification and valid data.
And step 304, generating an interrupt trigger signal, and sending the interrupt trigger signal to the microcontroller so that the microcontroller reads valid data from the target cache address based on the interrupt trigger signal. Here, the interrupt trigger signal is used to indicate that there is an entire packet of data received from the external node in the dynamic cache node to be read.
Corresponding to the multi-channel data communication method in fig. 5, an embodiment of the present application further provides a structural schematic diagram of an electronic device 400, as shown in fig. 6, the electronic device 400 includes a processor 410, a memory 420, and a bus 430. The memory 420 stores machine-readable instructions executable by the processor 410, when the electronic device 400 runs, the processor 410 and the memory 420 communicate through the bus 430, and when the machine-readable instructions are executed by the processor 410, the multi-channel data communication system CAN be executed to store data sent by different external nodes into corresponding independent caches through dynamic cache nodes independent of a microcontroller, and receive the whole packet of data by sending interrupt trigger signals once through an indefinite-length data packet protocol, so that the problems of data processing process lag of the microcontroller and node device response delay caused by the large number of external nodes and large data interaction amount when a certain node on a CAN bus communicates with a plurality of external nodes are solved.
It can be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working processes of the method and the electronic device described above may refer to the corresponding processes in the foregoing system embodiments, and are not described herein again.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, a division of a unit is merely a division of one logic function, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments provided in the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.
The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application or portions thereof that substantially contribute to the prior art may be embodied in the form of a software product stored in a storage medium and including instructions for causing an electronic device (which may be a personal computer, a server, or a network device) to perform all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus once an item is defined in one figure, it need not be further defined and explained in subsequent figures, and moreover, the terms "first", "second", "third", etc. are used merely to distinguish one description from another and are not to be construed as indicating or implying relative importance.
Finally, it should be noted that: the above-mentioned embodiments are only specific embodiments of the present application, and are used to illustrate the technical solutions of the present application, but not to limit the technical solutions, and the scope of the present application is not limited to the above-mentioned embodiments, although the present application is described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: any person skilled in the art can modify or easily conceive the technical solutions described in the foregoing embodiments or equivalent substitutes for some technical features within the technical scope disclosed in the present application; such modifications, changes or substitutions do not depart from the spirit and scope of the exemplary embodiments of the present application, and are intended to be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (9)
1. A multi-channel data communication system is characterized by comprising a dynamic cache node and a microcontroller, wherein the dynamic cache node is independent of the microcontroller and is connected with the microcontroller through a second bus, and the second bus is a peripheral bus;
the method comprises the steps that a dynamic cache node receives bus data from different external nodes through a first bus, wherein the bus data comprises external node identification and valid data;
for each external node, the dynamic cache node performs the following: determining a cache address corresponding to the external node indicated by the external node identification, and storing the valid data in the determined cache address;
the dynamic cache node determines a target cache address, wherein the target cache address is a cache address at which the total data length of valid data stored in the cache address corresponding to each external node reaches the length of a target data packet;
the dynamic cache node generates an interrupt trigger signal and sends the interrupt trigger signal to the microcontroller, wherein the interrupt trigger signal is used for indicating that the dynamic cache node has a whole packet of data to be read, and the data is received from an external node;
the microcontroller reads valid data from a target cache address based on the interrupt trigger signal;
wherein the bus data comprises a single frame header and single frame data, the single frame header comprises an external node identifier, the single frame data comprises a frame sequence number and an effective data range,
the dynamic cache node determines and stores the length of the target data packet in the following mode:
extracting a frame number from the received bus data;
determining whether the received bus data is a first frame based on the frame sequence number;
if the frame is the first frame, reading the target data packet length from the first bit of the effective data range, and storing the target data packet length to the data packet length address.
2. A multi-channel data communication system as claimed in claim 1, characterized in that the dynamic cache node further performs the following processing:
after determining the target cache address, pointing the interrupt read address to the target cache address;
wherein the microcontroller further performs the following processing:
and in response to the interrupt trigger signal, reading valid data from the target cache address based on the target cache address pointed to by the interrupt read address.
3. The multi-channel data communication system of claim 1, wherein the microcontroller further performs the following:
reading the packet length from the packet length address;
determining the data reading times according to the length of the data packet;
and reading valid data from the target cache address according to the data reading times.
4. The multi-channel data communication system according to claim 1, wherein the other bits than the first bit in the valid data range of the bus data of the first frame are used for storing the valid data, and each bit in the valid data range of the bus data of the non-first frame is used for storing the valid data.
5. A multi-channel data communication system as claimed in claim 1 wherein the dynamic cache node comprises a first bus interface, a second bus interface and an interrupt interface,
wherein the dynamic cache node receives bus data from different external nodes through a first bus interface,
the dynamic cache node is connected to a bus interface of the microcontroller through a second bus interface so as to transmit valid data through the second bus interface;
the dynamic cache node is connected to an interrupt trigger pin of the microcontroller through an interrupt interface so as to send an interrupt trigger signal to the microcontroller through the interrupt interface.
6. The multi-channel data communication system of claim 5, wherein the dynamic cache node includes a processing unit, a bus control unit, and a bus transceiver;
wherein the processing unit is connected to a bus interface of the microcontroller via a second bus interface,
the processing unit is connected to a first bus data interface of the bus control unit through a first bus interface, a second bus data interface of the bus control unit is connected to a third bus data interface of the bus transceiver, a fourth bus data interface of the bus transceiver receives bus data from different external nodes,
the processing unit is connected to an interrupt trigger pin of the microcontroller through an interrupt interface.
7. The multi-channel data communication system according to claim 6, wherein the bus control unit generates a hardware reception interrupt each time bus data of a target length is received from a different external node through the first bus;
the processing unit senses whether the level of the hardware receiving interrupt pin changes in real time;
and if the level of the hardware receiving interrupt pin is induced to change, the processing unit reads the bus data from the bus control unit and stores the effective data in the bus data into the corresponding cache address.
8. A method of multi-channel data communication, comprising:
receiving bus data from different external nodes through a first bus, wherein the bus data comprises external node identification and valid data;
for each external node, determining a cache address corresponding to the external node indicated by the external node identification, and storing effective data in the determined cache address;
determining a target cache address, wherein the target cache address is a cache address at which the total data length of valid data stored in the cache address corresponding to each external node reaches the length of a target data packet;
generating an interrupt trigger signal, and sending the interrupt trigger signal to a microcontroller so that the microcontroller reads valid data from a target cache address based on the interrupt trigger signal, wherein the interrupt trigger signal is used for indicating that the dynamic cache node has a whole packet of data to be read, and the data is received from an external node;
the bus data comprises a single frame header and single frame data, the single frame header comprises an external node identifier, and the single frame data comprises a frame sequence number and an effective data range;
wherein the method further comprises:
extracting a frame number from the received bus data;
determining whether the received bus data is a first frame based on the frame sequence number;
if the frame is the first frame, the target data packet length is read from the first bit of the effective data range, and the target data packet length is stored to the data packet length address.
9. An electronic device comprising a processor, a memory and a bus, the memory storing machine-readable instructions executable by the processor, the processor and the memory communicating over the bus when the electronic device is run, the machine-readable instructions when executed by the processor performing the steps of the multi-channel data communication method of claim 8.
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