CN113849438B - Protection circuit, method of protecting circuit, storage medium, and electronic device - Google Patents
Protection circuit, method of protecting circuit, storage medium, and electronic device Download PDFInfo
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- CN113849438B CN113849438B CN202111139055.7A CN202111139055A CN113849438B CN 113849438 B CN113849438 B CN 113849438B CN 202111139055 A CN202111139055 A CN 202111139055A CN 113849438 B CN113849438 B CN 113849438B
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- 238000000034 method Methods 0.000 title claims abstract description 31
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
- G06F13/4081—Live connection to bus, e.g. hot-plugging
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
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Abstract
The embodiment of the invention provides a protection circuit, a method for protecting the circuit, a storage medium and an electronic device, wherein the protection circuit comprises: the first end of the target diode is connected with the first pin of the signal output module, and the second end of the target diode is grounded, wherein the target diode is used for adjusting the bias voltage of the first pin; the comparison circuit is used for collecting the bias voltage of the first pin of the signal output module and comparing the bias voltage with the set voltage to obtain a comparison result; determining a target state value of the target diode based on the comparison result; and outputting the target state value to the processor to instruct the processor to adjust the working state of the signal output module based on the target state value, wherein a first input end of the comparison circuit is connected with the first pin, a second input end of the comparison circuit is connected with the power supply circuit, an output end of the comparator is connected with the signal output module, and the power supply circuit is used for providing set voltage for the second input end.
Description
Technical Field
The embodiment of the invention relates to the field of electronics, in particular to a protection circuit, a method for protecting the circuit, a storage medium and an electronic device.
Background
In the related art, the protection circuit uses a conventional TVS protection circuit (a shallow flyback structure), which has a high clamping voltage and a small through-flow under the same package, and cannot meet the protection requirement. The SCR structure (deep flyback) TVS is used, mechanism management is not performed, and once the protection circuit enters a latch state, the protection circuit needs to be powered up and powered down again to recover.
Therefore, the related art has the problems of poor protection effect, low efficiency and poor user experience of the protection circuit.
In view of the above problems in the related art, no effective solution has been proposed at present.
Disclosure of Invention
The embodiment of the invention provides a protection circuit, a method for protecting the circuit, a storage medium and an electronic device, which are used for at least solving the problems of poor protection effect, low efficiency and poor user experience of the protection circuit in the related technology.
According to an embodiment of the present invention, there is provided a protection circuit including: the first end of the target diode is connected with a first pin of the signal output module, and the second end of the target diode is grounded, wherein the target diode is used for adjusting the bias voltage of the first pin; the first input end of the comparison circuit is connected with a first pin of the signal output module, the second input end of the comparison circuit is connected with the power supply circuit, the output end of the comparison circuit is connected with the signal output module, the power supply circuit is used for providing a set voltage for the second input end, and the comparison circuit is used for collecting the bias voltage of the first pin of the signal output module and comparing the bias voltage with the set voltage to obtain a comparison result; determining a target state value of the target diode based on the comparison result; and outputting the target state value to a processor to instruct the processor to adjust the working state of the signal output module based on the target state value.
According to another embodiment of the present invention, there is provided a method of protecting a circuit, including: collecting the bias voltage of a first pin of the signal output module; comparing the bias voltage with the set voltage to obtain a comparison result; determining a target state value of the target diode based on the comparison result; and sending the target state value to the processor to instruct the processor to adjust the working state of the signal output module based on the target state value.
According to yet another embodiment of the present invention, there is also provided a computer-readable storage medium having stored therein a computer program, wherein the computer program when executed by a processor implements the steps of the method as described in any of the above.
According to a further embodiment of the invention, there is also provided an electronic device comprising a memory having stored therein a computer program and a processor arranged to run the computer program to perform the steps of any of the method embodiments described above.
According to the invention, the target diode is connected with the first pin of the signal output module, the bias voltage of the first pin is adjusted, the comparison circuit collects the bias voltage of the first pin, the bias voltage is compared with the set voltage to obtain a comparison result, the target state value of the target diode is determined according to the comparison result, and the target state value is output to the processor to instruct the processor to adjust the working state of the signal output module based on the target state value. The processor can adjust the working state of the signal output module through the target state value determined by the comparison result of the comparator, and the signal output module is not required to be electrified and electrified again, so that the problems of poor protection effect and low efficiency of the protection circuit in the related technology can be solved, the protection effect and the protection efficiency of the protection circuit are improved, and the user experience is improved.
Drawings
Fig. 1 is a structural diagram of a protection circuit according to an embodiment of the present invention;
fig. 2 is a circuit diagram of a protection circuit according to an exemplary embodiment of the present invention;
fig. 3 is a circuit diagram two of a protection circuit according to an exemplary embodiment of the present invention;
fig. 4 is a block diagram of a hardware structure of a mobile terminal of a method of protecting a circuit according to an embodiment of the present invention;
FIG. 5 is a flow chart of a method of protecting a circuit according to an embodiment of the invention;
fig. 6 is a block diagram of a protection circuit according to an embodiment of the present invention.
Detailed Description
Embodiments of the present invention will be described in detail below with reference to the accompanying drawings in conjunction with the embodiments.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order.
In hot plugging, since the signal lines (such as USB lines, HDMI lines, DP lines, etc.) at the interface end are already charged, the large capacitor, which is itself charged, will discharge when contacting the machine. This phenomenon is equivalent to the fact that the electrostatic discharge effect (sometimes more severe) can cause serious damage to the machine, and we generally call this phenomenon direct injection. Therefore, many electronic products require higher-level electrostatic protection tests for hot plug in order to prevent direct discharge.
After being subjected to ESD attack, people have pain, but do not form "defects", which is attributed to the fact that the resistance of the human body to the ground is large enough, and the electrostatic voltage cannot form large current to cause damage. The path through which static electricity enters the electronic equipment does not provide enough resistance to prevent damage, and a weak grid oxide layer or a reverse biased PN junction in the components can become a static electricity discharge path, so that the static voltage breaks down the parts and forms a weak point through which high current burns out, thereby damaging the components and causing the integral function failure of the electronic equipment. The high-speed data ports such as USB2.0, HDMI1.4, USB3.X and HDMI2.0 in the device are particularly sensitive to ESD events, are difficult in ESD protection design, and also provide extremely high requirements for TVS device design used at the ports.
Firstly, in order to enhance the user experience, the port transmission rate is continuously increased, taking the USB3.1 high-speed data port which is widely used as an example, the transmission rate of the USB3.1 Gen1 in the super speed working mode reaches 5Gbps, and the transmission rate of the USB3.1 Gen2 reaches 10Gbps. The ultra-high data transfer rate requires very little port loading and the TVS used at the port to have ultra-low capacitance.
Secondly, the miniaturization requirement and the improvement of chip design technology, manufacturing process technology and IP design technology are improved, so that the chip integration level is continuously improved, and more designs integrate a CPU, a communication protocol chip and a Phy chip into one chip through SoC design technology; the process nodes used are also smaller and smaller, for example, the process nodes of the early USB3.0 protocol chip and the Phy chip are 65nm, the process nodes are reduced to 28nm, and part of SoC products are used for 10 nm-14 nm. Namely, the Phy chip which needs TVS protection for ESD impact uses the same process as the CPU, and the design difficulty of ESD protection is increased. Shrinking the process corresponds to weakening of ESD endurance, requiring TVS to provide a low enough clamp voltage to protect the SoC chip.
Again, more and more of the same application will have multiple SoC chip vendor solutions, and there will be a certain difference between chips in design technology and process technology, resulting in different ESD tolerance capabilities of the chip ports. In order to ensure that different complete machine schemes can have ESD indexes meeting the application, the TVS device needs to cover ESD protection of the SoC chip with the weakest tolerance, and therefore, the TVS needs to provide a sufficiently low clamping voltage.
The TVS of the SCR structure (deep flyback) can satisfy the above requirements:
1, the clamp is low, and the chip is safer. The high-speed chip port has a small withstand voltage, such as 10V. The common TVS breaks down at 7-8V, is clamped at about 10V, and has the risk of damage; the deep flyback TVS breaks down at 7-8V, the clamping voltage can be 3V, and the chip is not damaged.
2, the through flow is larger. Under the same package and the same peak power, the clamp voltage is low, the transient through current is larger, and the overall surge protection can be made to be higher in grade.
The condition that the SCR structure exits the latch-up state (protection freewheel state) to resume to the protection circuit state requires either of the following two conditions to be satisfied:
(1) The signal port provides a voltage for the latch structure that is less than the sustain voltage;
(2) The signal port provides a current to the latch structure that is less than the sustain current.
In this embodiment, a protection circuit is provided, fig. 1 is a structural diagram of the protection circuit according to an embodiment of the present invention, and as shown in fig. 1, the circuit includes:
a target diode 12, a first end of which is connected with a first pin of the signal output module, and a second end of which is grounded, wherein the target diode is used for adjusting the bias voltage of the first pin;
the first input end of the comparison circuit is connected with a first pin of the signal output module, the second input end of the comparison circuit is connected with the power supply circuit, the output end of the comparison circuit is connected with the signal output module, the power supply circuit is used for providing a set voltage for the second input end, wherein the comparison circuit is used for collecting the bias voltage of the first pin of the signal output module and comparing the bias voltage with the set voltage to obtain a comparison result; determining a target state value of the target diode based on the comparison result; and outputting the target state value to a processor to instruct the processor to adjust the working state of the signal output module based on the target state value.
In the above embodiment, the processor may be a central processing unit CPU, and the signal output module may be a high-speed differential signal output module, such as a high-speed data output module in the device, including USB2.0, HDMI1.4, USB3.X, HDMI2.0, and the like, which is generally built in the CPU. The USB2.0, HDMI1.4, USB3.X, HDMI2.0 and other high-speed data output external connectors in the device can support hot plug. Therefore, a high-speed differential signal protection circuit needs to be provided.
In the above embodiment, the target diode may be an SCR structure (deep regression) TVS, and the differential signal output by the signal output module may have a dc bias level (corresponding to the bias voltage) by default, where the differential signal is superimposed on the dc bias level and is output to the outside through the first pin of the signal output module. When triggering to the protection device TVS to enter a protection state, that is, when electrostatic discharge or direct current discharge occurs, the SCR structure TVS enters a freewheel mode, and the direct current bias level of the signal to ground is pulled down to a certain value of the TVS characteristic, that is, the bias voltage is adjusted. The first input end of the comparison circuit is connected with a first pin of the signal output module, the bias voltage on the first pin is collected, the second input end of the comparison circuit is connected with the power supply circuit, wherein the power supply circuit can be a constant current power supply, namely, a set voltage is provided for the second input end of the comparison circuit. The comparison circuit may include a comparator, which may be a hysteresis comparator.
In the above embodiment, the comparison circuit compares the bias voltage with the set voltage to obtain the comparison result. The target state value of the target diode can be determined according to the comparison result, the target state value is output to the processor, and the processor can adjust the working state of the signal output module according to the target state value. When the target diode is in an unprotected state, the bias voltage VDet on the first pin is larger than the set voltage VRef, when the target diode is triggered to be in the protected state, namely, the target diode enters a freewheel mode, the bias voltage on the first pin is regulated down and smaller than VRef, and when the comparison circuit determines that the bias voltage is smaller than VRef, a first target state value is output to the processor to instruct the processor to control the signal output module to turn off and restart again. For example, when the hot plug interface performs a plug operation, if an interference impact such as EOS or ESD occurs, the SCR structure (deep flyback) TVS circuit acts and clamps to a lower level, and at this time, it always maintains a low-voltage clamping requirement state and cannot be actively recovered; the clamp voltage is compared with the reference voltage of the hysteresis comparator, namely the set voltage, the low level is output to inform the CPU that the protection circuit enters a protection state, and the CPU operates the high-speed differential signal output module to turn off and on again after receiving the information, so that the high-speed differential signal protection circuit returns to the protection state again, and the interface protection and the complete function of the hot plug equipment are realized.
In the above embodiment, the target state values may include a first target state value and a second target state value. When VDet detected by the comparison circuit is smaller than VRef, a first target state value is output, and when VDet detected by the comparison circuit is larger than VRef, a second target state value is output. The first target state value is used for indicating the processor to turn off and turn on the signal output module again, and the second target state value is used for indicating the processor to keep the state of the signal output module without adjustment. The first target state value may be a low level, the second target state value may be a high level, or the first target state value may be a high level, and the second target state value may be a low level.
According to the invention, the target diode is connected with the first pin of the signal output module, the bias voltage of the first pin is adjusted, the comparison circuit collects the bias voltage of the first pin, the bias voltage is compared with the set voltage to obtain a comparison result, the target state value of the target diode is determined according to the comparison result, and the target state value is output to the processor to instruct the processor to adjust the working state of the signal output module based on the target state value. The processor can adjust the working state of the signal output module through the target state value determined by the comparison result of the comparator, and the signal output module is not required to be electrified and electrified again, so that the problems of poor protection effect and low efficiency of the protection circuit in the related technology can be solved, the protection effect and the protection efficiency of the protection circuit are improved, and the user experience is improved.
In one exemplary embodiment, the target diode includes: a transient diode. In this embodiment, the target diode may be an SCR structure (deep regression) TVS.
In an exemplary embodiment, the protection circuit further includes: and the second end of the first resistor is connected with the first input end of the comparison circuit. In this embodiment, the comparator may be connected to the first pin of the signal output module through a first resistor.
In an exemplary embodiment, in a case where the signal output module includes a first number of the first pins, the number of the target diodes is the first number, and one of the first pins is disposed corresponding to one of the target diodes, wherein the first number is an integer greater than 1. In this embodiment, when the signal output module includes the first number of first pins, the number of target diodes is also the first number, that is, each of the first pins is connected to one target diode. When an EOS, ESD or other interference impact occurs on a certain first pin, the target diode connected with the first pin enters a freewheel state. For example, when the first number is 2, i.e. the signal output module includes two pins, two target diodes may be provided, one target diode being connected to each pin for adjusting the bias voltage of the pin connected thereto to protect the interface signal in case the target diode is triggered. Therefore, the abnormal state monitoring of the protected signal can be judged through the state of the target diode, the interface function problem can be rapidly positioned, such as the occurrence of abnormal (welding abnormal and the like) ground short circuit and the like of the signal channel, the problem point can be rapidly positioned in real time, and the problem is solved.
In one exemplary embodiment, the comparison circuit includes: the first input end of the comparator is connected with a first number of the first pins, the second input end of the comparator is connected with the power supply circuit, the output end of the comparator is connected with the signal output module, the comparator outputs the comparison result to the signal output module as the target state value, the first input end of the comparison circuit comprises the first input end of the comparator, the second input end of the comparison circuit comprises the second input end of the comparator, and the output end of the comparison circuit comprises the output end of the comparator. In this embodiment, when the signal output module includes a first number of first pins and a first number of target diodes, a comparator may be included. For example, when the first number is 2, the two pins may be connected through two resistors, the first resistor and the second resistor are connected in series, the first end of the first resistor and the second end of the second resistor are respectively connected with the two pins, the first input end of the comparator may be connected with the second end of the first resistor and the first end of the second resistor, that is, the first input end of the comparator collects the average voltage of the two pins, and the second input end of the comparator is connected with the power supply circuit. And outputting a comparison result according to the collected average voltage and the set voltage provided by the power supply circuit. The comparison result may include an abnormal result and a normal result, the abnormal result may be a low level, and the normal result may be a high level. When a comparator is included, the result of the comparator output may be used to determine the target state value.
In the above embodiment, when the first number is 2, the first circuit diagram of the protection circuit can refer to fig. 2, and as shown in fig. 2, vdet detects the dc level of the differential signal in real time, and outputs the state value after comparison by the comparator. And taking the differential signals as a group to perform level detection, wherein Vdet= (VOUT_P+VOUT_N)/2, and when a certain TVS acts to enter a follow current mode, namely Vdet < Vref, the comparator outputs an abnormal state value.
In one exemplary embodiment, the comparison circuit includes: a second number of comparators, wherein a first input end of the comparator is connected with one or more first pins, and first pins connected by different comparators are different, a second input end of the comparator is connected with the power supply circuit, an output end of the comparator is connected with an input end of a logic circuit, the second number is an integer greater than 1, and the second number is smaller than or equal to the first number; the logic circuit is used for carrying out preset logic operation on the received second number of comparison results to obtain the target state value, and outputting the target state value to the signal output module; wherein the first input of the comparison circuit comprises a second number of first inputs of the comparators, the second input of the comparison circuit comprises a second number of second inputs of the comparators, and the output of the comparison circuit comprises an output of the logic circuit. In this embodiment, when the signal output module includes the first number of the first pins and the first number of the target diodes, the number of the comparators may be a second number, where the second number is smaller than or equal to the first number. For example, when the first number is 2, the second number may be 2, that is, each pin is connected to one comparator, each comparator compares the relationship between the bias voltage and the set voltage of the pin connected to the first number, so as to determine the comparison result, each comparator inputs the respective comparison result into the logic circuit, and the logic circuit performs logic operation on the second number of comparison results to obtain the target state value.
In the above embodiment, when the first number is equal to the second number is equal to 2, as shown in fig. 3, the comparator performs level detection on the differential signals individually, and when vdet=vout_p or vout_n, the comparator outputs an abnormal state value when Vdet < Vref. The detection and judgment of whether the TVS enters into the follow current mode are achieved through the state output. When the TVS, i.e. the target diode, is determined to enter the freewheel mode, an abnormal state value is output to the processor to instruct the processor to turn off and on the signal output module again.
In the above embodiment, when the second number is smaller than the first number, a part of the pins may be set to share one comparator, and a part of the pins are respectively connected to one comparator. For example, when the first number is 3 and the second number is 2, two pins may be set to share one comparator (the connection manner may be see fig. 2), the other pin is connected to the other comparator, and then the output ends of the two comparators are respectively connected to the input ends of the logic circuit, and the logic circuit determines the target state value based on the comparison result.
In one exemplary embodiment, the logic circuit includes a logic AND gate circuit. In this embodiment, the logic circuit may be a logic and circuit, and when the comparison result output by the comparator has an abnormal result, the and circuit outputs an abnormal state value, such as a low level. When the output results of the comparators are all normal results, the AND gate circuit outputs a normal state value, such as a high level.
The method embodiments provided in the embodiments of the present application may be performed in a mobile terminal, a computer terminal or similar computing device. Taking the mobile terminal as an example, fig. 4 is a block diagram of a hardware structure of the mobile terminal according to a method for protecting a circuit according to an embodiment of the present invention. As shown in fig. 4, the mobile terminal may include one or more processors 102 (only one is shown in fig. 4) (the processor 102 may include, but is not limited to, a microprocessor MCU, a programmable logic device FPGA, etc. processing means) and a memory 104 for storing data, wherein the mobile terminal may further include a transmission device 106 for communication functions and an input-output device 108. It will be appreciated by those skilled in the art that the structure shown in fig. 4 is merely illustrative and not limiting of the structure of the mobile terminal described above. For example, the mobile terminal may also include more or fewer components than shown in fig. 4, or have a different configuration than shown in fig. 4.
The memory 104 may be used to store a computer program, for example, a software program of application software and a module, such as a computer program corresponding to a method of protecting a circuit in an embodiment of the present invention, and the processor 102 executes the computer program stored in the memory 104, thereby performing various functional applications and data processing, that is, implementing the above-mentioned method. Memory 104 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include memory remotely located relative to the processor 102, which may be connected to the mobile terminal via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The transmission device 106 is used to receive or transmit data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider of the mobile terminal. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, simply referred to as NIC) that can connect to other network devices through a base station to communicate with the internet. In one example, the transmission device 106 may be a Radio Frequency (RF) module, which is configured to communicate with the internet wirelessly.
In this embodiment, a method for protecting a circuit is provided, and fig. 5 is a flowchart of a method for protecting a circuit according to an embodiment of the present invention, as shown in fig. 5, the flowchart includes the following steps:
step S502, collecting the bias voltage of a first pin of the signal output module;
step S504, comparing the bias voltage with the set voltage to obtain a comparison result;
step S506, determining a target state value of the target diode based on the comparison result;
and step S508, the target state value is sent to the processor so as to instruct the processor to adjust the working state of the signal output module based on the target state value.
In the above embodiment, the processor may be a central processing unit CPU, and the signal output module may be a high-speed differential signal output module, such as a high-speed data output module in the device, including USB2.0, HDMI1.4, USB3.X, HDMI2.0, and the like, which is generally built in the CPU. The USB2.0, HDMI1.4, USB3.X, HDMI2.0 and other high-speed data output external connectors in the device can support hot plug. Therefore, a high-speed differential signal protection circuit needs to be provided.
In the above embodiment, the target diode may be an SCR structure (deep regression) TVS, and the differential signal output by the signal output module may have a dc bias level (corresponding to the bias voltage) by default, where the differential signal is superimposed on the dc bias level and is output to the outside through the first pin of the signal output module. When triggering to the protection device TVS to enter a protection state, that is, when electrostatic discharge or direct current discharge occurs, the SCR structure TVS enters a freewheel mode, and the direct current bias level of the signal to ground is pulled down to a certain value of the TVS characteristic, that is, the bias voltage is adjusted. The first input end of the comparison circuit is connected with a first pin of the signal output module, the bias voltage on the first pin is collected, the second input end of the comparison circuit is connected with the power supply circuit, wherein the power supply circuit can be a constant current power supply, namely, a set voltage is provided for the second input end of the comparator. The comparison circuit may include a comparator, which may be a hysteresis comparator.
In the above embodiment, the comparison circuit compares the bias voltage with the set voltage to obtain the comparison result. The target state value of the target diode can be determined according to the comparison result, the target state value is output to the processor, and the processor can adjust the working state of the signal output module according to the target state value. When the target diode is in an unprotected state, the bias voltage VDet on the first pin is larger than the set voltage VRef, when the target diode is triggered to be in the protected state, namely, the target diode enters a freewheel mode, the bias voltage on the first pin is regulated down and smaller than VRef, and when the comparison circuit determines that the bias voltage is smaller than VRef, a first target state value is output to the processor to instruct the processor to control the signal output module to turn off and restart again. For example, when the hot plug interface performs a plug operation, if an interference impact such as EOS or ESD occurs, the SCR structure (deep flyback) TVS circuit acts and clamps to a lower level, and at this time, it always maintains a low-voltage clamping requirement state and cannot be actively recovered; the clamp voltage is compared with the reference voltage of the hysteresis comparator, namely the set voltage, the low level is output to inform the CPU that the protection circuit enters a protection state, and the CPU operates the high-speed differential signal output module to turn off and on again after receiving the information, so that the high-speed differential signal protection circuit returns to the protection state again, and the interface protection and the complete function of the hot plug equipment are realized.
In the above embodiment, the target state values may include a first target state value and a second target state value. When VDet detected by the comparison circuit is smaller than VRef, a first target state value is output, and when VDet detected by the comparison circuit is larger than VRef, a second target state value is output. The first target state value is used for indicating the processor to turn off and turn on the signal output module again, and the second target state value is used for indicating the processor to keep the state of the signal output module without adjustment. The first target state value may be a low level, the second target state value may be a high level, or the first target state value may be a high level, and the second target state value may be a low level.
Alternatively, the execution subject of the above steps may be a comparison circuit. Such as a comparator, or a comparison circuit comprising a comparator and a logic gate.
Through the steps, the bias voltage of the first pin of the signal output module is collected, the bias voltage is compared with the set voltage to obtain a comparison result, the target state value of the target diode is determined according to the comparison result, and the target state value is sent to the processor to instruct the processor to adjust the working state of the signal output module based on the target state value. The processor can adjust the working state of the signal output module through the target state value determined by the comparison result, and the signal output module is not required to be electrified and electrified again, so that the problems of poor protection effect, low efficiency and poor user experience of the protection circuit in the related technology can be solved, the protection effect and the protection efficiency of the protection circuit are improved, and the user experience is improved.
In one exemplary embodiment, determining the target state value of the target diode based on the comparison result includes: determining the comparison result as the target state value in the case that the comparison result includes only one comparison result; and carrying out logical AND operation on the comparison results to obtain the target state value under the condition that the comparison results comprise a plurality of comparison results. In this embodiment, when the signal output module includes the first number of first pins and the first number of target diodes, a comparator may be disposed in the circuit to obtain a comparison result. For example, when the first number is 2, the two pins may be connected through two resistors, the first resistor and the second resistor are connected in series, the first end of the first resistor and the second end of the second resistor are respectively connected with the two pins, the first input end of the comparator may be connected with the second end of the first resistor and the first end of the second resistor, that is, the first input end of the comparator collects the average voltage of the two pins, and the second input end of the comparator is connected with the power supply circuit. And outputting a comparison result according to the collected average voltage and the set voltage provided by the power supply circuit. The comparison result may include an abnormal result and a normal result, the abnormal result may be a low level, and the normal result may be a high level. When a comparator is included, the result of the comparator output may be used to determine the target state value.
In the above embodiment, when the first number is 2, the circuit diagram of the protection circuit may refer to fig. 2, and as shown in fig. 2, vdet detects the dc level of the differential signal in real time, and outputs the state value after comparison by the comparator. And taking the differential signals as a group to perform level detection, wherein Vdet= (VOUT_P+VOUT_N)/2, and when a certain TVS acts to enter a follow current mode, namely Vdet < Vref, the comparator outputs an abnormal state value.
In the above embodiment, in the case that the signal output module includes the first number of the first pins and the first number of the target diodes, the number of the comparators may be set to a second number to obtain the second number of comparison results, where the second number is smaller than or equal to the first number. For example, when the first number is 2, the second number may be 2, that is, each pin is connected to one comparator, each comparator compares the relationship between the bias voltage and the set voltage of the pin connected to the first number, so as to determine the comparison result, each comparator inputs the respective comparison result into the logic circuit, and the logic circuit performs logic operation on the second number of comparison results to obtain the target state value.
In the above embodiment, when the first number is equal to the second number is equal to 2, the circuit diagram of the protection circuit may refer to fig. 3, and as shown in fig. 3, the comparators individually perform level detection on the differential signals, vdet=vout_p or vout_n, and when Vdet < Vref, the comparators output abnormal state values. The detection and judgment of whether the TVS enters into the follow current mode are achieved through the state output. When the TVS, i.e. the target diode, is determined to enter the freewheel mode, an abnormal state value is output to the processor to instruct the processor to turn off and on the signal output module again.
In the above embodiment, when the second number is smaller than the first number, a part of the pins may be set to share one comparator, and a part of the pins are respectively connected to one comparator. For example, when the first number is 3 and the second number is 2, two pins may be set to share one comparator (the connection manner may be see fig. 2), the other pin is connected to the other comparator, and then the output ends of the two comparators are respectively connected to the input ends of the logic circuit, and the logic circuit determines the target state value based on the comparison result.
The method of protecting the circuit is described below in connection with the embodiments:
fig. 6 is a block diagram of a protection circuit according to an embodiment of the present invention, and as shown in fig. 6, the high-speed differential signal output module may be a high-speed data output module such as USB2.0, HDMI1.4, USB3.X, HDMI2.0, etc. in the device, which is generally built in a CPU. The high-speed differential signal protection circuit is an SCR structure (deep flyback) TVS circuit. The output interface comprises a USB2.0, HDMI1.4, USB3.X, HDMI2.0 and other high-speed data output external connector in the device, and the interfaces can support hot plug. Differential signal level detection module: the module mainly collects direct current bias level on differential signal lines and provides the direct current bias level for a hysteresis comparator to perform level comparison. Hysteresis comparator module (corresponding to the comparator described above): in order to avoid misjudgment, the direct current bias on the differential signal circuit is compared by using delay to judge whether the protection circuit enters a protection follow current state, if so, a certain fixed level is output to the CPU for control judgment.
In the foregoing embodiment, the characteristic defect of the SCR structure (deep flyback) TVS circuit is that the trigger protection enters into the freewheel mode, the high-speed signal transmission cannot work normally, and when the clamp voltage is lower than the high-speed signal in the freewheel mode and works normally, the hysteresis comparator is used to report the status information to the CPU, and the output is controlled again, so that the high-speed data interfaces such as USB2.0, HDMI1.4, USB3.x, HDMI2.0 and the like in the device are effectively protected. The interface protection and the complete functions of the hot plug equipment are realized.
From the description of the above embodiments, it will be clear to a person skilled in the art that the method according to the above embodiments may be implemented by means of software plus the necessary general hardware platform, but of course also by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art in the form of a software product stored in a storage medium (e.g. ROM/RAM, magnetic disk, optical disk) comprising instructions for causing a terminal device (which may be a mobile phone, a computer, a server, or a network device, etc.) to perform the method according to the embodiments of the present invention.
Embodiments of the present invention also provide a computer readable storage medium having a computer program stored therein, wherein the computer program when executed by a processor implements the steps of the method described in any of the above.
In one exemplary embodiment, the computer readable storage medium may include, but is not limited to: a usb disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a removable hard disk, a magnetic disk, or an optical disk, or other various media capable of storing a computer program.
An embodiment of the invention also provides an electronic device comprising a memory having stored therein a computer program and a processor arranged to run the computer program to perform the steps of any of the method embodiments described above.
In an exemplary embodiment, the electronic apparatus may further include a transmission device connected to the processor, and an input/output device connected to the processor.
Specific examples in this embodiment may refer to the examples described in the foregoing embodiments and the exemplary implementation, and this embodiment is not described herein.
It will be appreciated by those skilled in the art that the modules or steps of the invention described above may be implemented in a general purpose computing device, they may be concentrated on a single computing device, or distributed across a network of computing devices, they may be implemented in program code executable by computing devices, so that they may be stored in a storage device for execution by computing devices, and in some cases, the steps shown or described may be performed in a different order than that shown or described herein, or they may be separately fabricated into individual integrated circuit modules, or multiple modules or steps of them may be fabricated into a single integrated circuit module. Thus, the present invention is not limited to any specific combination of hardware and software.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A protection circuit, comprising:
the first end of the target diode is connected with a first pin of the signal output module, and the second end of the target diode is grounded, wherein the target diode is used for adjusting the bias voltage of the first pin;
the first input end of the comparison circuit is connected with a first pin of the signal output module, the second input end of the comparison circuit is connected with the power supply circuit, the output end of the comparison circuit is connected with the signal output module, the power supply circuit is used for providing set voltage for the second input end, the comparison circuit is used for collecting bias voltage of the first pin of the signal output module, and comparing the bias voltage with the set voltage to obtain a comparison result; determining a target state value of the target diode based on the comparison result; outputting the target state value to a processor to instruct the processor to adjust the working state of the signal output module based on the target state value;
in the case that the signal output module includes a first number of the first pins, the number of the target diodes is the first number, and one of the first pins is arranged corresponding to one of the target diodes, wherein the first number is an integer greater than 1;
the comparison circuit comprises one or a second number of comparators, the first input end is connected with a first number of first pins, the second input end of the comparators is connected with the power supply circuit, and the output end of the comparators is connected with the signal output module; in the case that the comparison circuit comprises the second number of comparators, a first input end of the comparator is connected with one or more first pins, and first pins connected by different comparators are different, a second input end of the comparator is connected with the power supply circuit, an output end of the comparator is connected with an input end of a logic circuit, the second number is an integer greater than 1, and the second number is smaller than or equal to the first number;
the target diode comprises a TVS diode with an SCR structure.
2. The protection circuit of claim 1, wherein the target diode comprises: a transient diode.
3. The protection circuit of claim 1, further comprising:
and the second end of the first resistor is connected with the first input end of the comparison circuit.
4. The protection circuit of claim 1, wherein,
in case the comparison circuit comprises a comparator, the first input of the comparison circuit comprises a first input of the comparator, the second input of the comparison circuit comprises a second input of the comparator, and the output of the comparison circuit comprises an output of the comparator.
5. The protection circuit of claim 1, wherein,
in the case that the comparison circuit includes the second number of comparators, the comparison circuit further includes the logic circuit, where an output terminal of the logic circuit is connected to the processor, the logic circuit is configured to perform a predetermined logic operation on the received second number of comparison results to obtain the target state value, and output the target state value to the processor; wherein the first input of the comparison circuit comprises a second number of first inputs of the comparators, the second input of the comparison circuit comprises a second number of second inputs of the comparators, and the output of the comparison circuit comprises an output of the logic circuit.
6. The protection circuit of claim 5, wherein the logic circuit comprises a logic and circuit.
7. A method of protecting a circuit, for use in the protection circuit of any one of claims 1 to 6, comprising:
collecting the bias voltage of a first pin of the signal output module;
comparing the bias voltage with the set voltage to obtain a comparison result;
determining a target state value of the target diode based on the comparison result;
and sending the target state value to the processor to instruct the processor to adjust the working state of the signal output module based on the target state value.
8. The method of claim 7, wherein determining a target state value for the target diode based on the comparison result comprises:
determining the comparison result as the target state value in the case that the comparison result includes only one comparison result;
and carrying out logical AND operation on the comparison results to obtain the target state value under the condition that the comparison results comprise a plurality of comparison results.
9. A computer readable storage medium, characterized in that a computer program is stored in the computer readable storage medium, wherein the computer program, when being executed by a processor, implements the steps of the method according to any of the claims 7 to 8.
10. An electronic device comprising a memory and a processor, characterized in that the memory has stored therein a computer program, the processor being arranged to run the computer program to perform the method of any of the claims 7 to 8.
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