CN113836594A - Boolean circuit for implementing two-sided multi-branch conditions - Google Patents
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Abstract
Embodiments of the present disclosure provide a boolean circuit for implementing a two-way multi-branch condition that may employ the implementation of a garbled circuit. The circuit comprises: a comparison unit for determining respective comparison results of the N branch conditions; the N branch conditions respectively correspond to N numerical values which are sequentially arranged, and any branch condition comprises size comparison of privacy data held by a first party and privacy data held by a second party; the selection unit is used for respectively executing N rounds of selection processing on N numerical values corresponding to N branch conditions according to the sequence from back to front by taking the (N + 1) th numerical value as an initial value of an intermediate result, wherein the (N + 1) th numerical value is a value when all the branch conditions are not satisfied; each round of selection processing comprises: and according to the comparison result corresponding to the current numerical value, selecting one of the current numerical value and the intermediate result of the previous round as the intermediate result of the current round. The two-party multi-branch condition can be realized on the premise of protecting the private data.
Description
Technical Field
One or more embodiments of the present description relate to the field of computers, and more particularly, to boolean circuits for implementing a two-way multi-branch condition.
Background
The secure multi-party computation is also called multi-party secure computation, namely, a plurality of parties compute the result of a function together without revealing the input data of each party of the function, and the computed result is disclosed to one or more parties. Where the input data for the parties is often private data.
The two-party multi-branch condition is one of basic operation functions of user operation logic in secure multi-party computing, and is used for returning a numerical value corresponding to an established branch condition from N +1 numerical values arranged in sequence according to the established branch condition in N sequentially executed branch conditions, wherein any branch condition comprises size comparison of privacy data held by the two parties respectively.
Disclosure of Invention
One or more embodiments of the present specification describe a boolean circuit for implementing a two-way multi-branch condition that enables the implementation of the two-way multi-branch condition while preserving private data.
In a first aspect, there is provided a boolean circuit for implementing a two-way multi-branch condition, the boolean circuit comprising:
a comparison unit for determining a comparison result for each of the N branch conditions; the N branch conditions respectively correspond to N numerical values which are sequentially arranged, and any branch condition comprises size comparison of privacy data held by a first party and privacy data held by a second party;
the selection unit is used for respectively executing N rounds of selection processing on N numerical values corresponding to N branch conditions according to the sequence from back to front by taking the (N + 1) th numerical value as an initial value of an intermediate result, wherein the (N + 1) th numerical value is a value when all the branch conditions are not satisfied; each round of selection processing comprises: selecting one of the current value and the intermediate result of the previous round as the intermediate result of the current round according to the comparison result of the branch condition corresponding to the current value; and taking the intermediate result after the N rounds of selection processing as the processing result of the multi-branch condition.
In a possible embodiment, the comparison unit further comprises N comparison subunits corresponding to N branch conditions, respectively;
each comparison subunit receives the private data to be compared of the corresponding branch condition and outputs the comparison result corresponding to the branch condition.
In one possible embodiment, each of the N +1 values is l bits; the selection unit further comprises N times l selection sub-units respectively corresponding to each bit of the N numerical values;
each selection subunit receives the comparison result of the branch condition corresponding to the current value, the target bit of the current value and the target bit of the intermediate result of the previous round, and outputs the target bit of the intermediate result of the current round through a single AND gate.
Further, the selecting subunit further comprises: the first exclusive-OR gate and the first AND gate are used as the single AND gate and the second exclusive-OR gate;
the first exclusive-or gate receives a target bit of a current value and the target bit of an intermediate result of a previous round and outputs a first intermediate value;
the first AND gate receives a comparison result of the branch condition corresponding to the first intermediate value and the current value and outputs a second intermediate value;
and the second exclusive-or gate receives the second intermediate value and the target bit of the current value and outputs the target bit of the intermediate result of the current round.
In one possible implementation, the boolean circuit further includes:
and the splitting unit is used for splitting the processing result of the multi-branch condition into corresponding fragments and respectively outputting the fragments to the first party and the second party.
In a possible implementation, the first party has N private data in a first private data set, the second party has N private data in a second private data set, and the comparison result is characterized based on whether a preset comparison relationship is satisfied between the first private data in the first private data set and the second private data in the second private data set.
Further, the preset comparison relationship includes at least one of:
less than, less than or equal to, greater than or equal to, greater than.
In one possible implementation, the boolean circuit employs an implementation of a garbled circuit.
In a second aspect, there is provided a computer readable storage medium having stored thereon a computer program which, when executed in a computer, causes the computer to implement the boolean circuit of the first aspect.
In a third aspect, a computing device is provided, comprising a memory and a processor, wherein the memory stores executable code, and the processor implements the boolean circuit of the first aspect when executing the executable code.
The boolean circuit provided by the embodiments of the present specification includes: a comparison unit for determining a comparison result for each of the N branch conditions; the N branch conditions respectively correspond to N numerical values which are sequentially arranged, and any branch condition comprises size comparison of privacy data held by a first party and privacy data held by a second party; the selection unit is used for respectively executing N rounds of selection processing on N numerical values corresponding to N branch conditions according to the sequence from back to front by taking the (N + 1) th numerical value as an initial value of an intermediate result, wherein the (N + 1) th numerical value is a value when all the branch conditions are not satisfied; each round of selection processing comprises: selecting one of the current value and the intermediate result of the previous round as the intermediate result of the current round according to the comparison result of the branch condition corresponding to the current value; and taking the intermediate result after the N rounds of selection processing as the processing result of the multi-branch condition. As can be seen from the above, in the embodiments of the present specification, the comparison unit determines the comparison result of each of the N branch conditions, and the selection unit respectively executes N rounds of selection processing on the N values corresponding to the N branch conditions according to a sequence from back to front, so as to provide a specific way of implementing the two-party multi-branch condition through the boolean circuit, and implement the two-party multi-branch condition on the premise of protecting the private data.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic diagram illustrating an implementation scenario of an embodiment disclosed herein;
FIG. 2 illustrates a Boolean circuit architecture diagram for implementing a two-way multi-branch condition, according to one embodiment;
fig. 3 shows a schematic structural diagram of a selection subunit according to an embodiment.
Detailed Description
The scheme provided by the specification is described below with reference to the accompanying drawings.
Fig. 1 is a schematic view of an implementation scenario of an embodiment disclosed in this specification. This implementation scenario involves a boolean circuit for implementing a two-party multi-branch condition. In the prior art, N branch conditions are usually executed in sequence, and when a certain branch condition is satisfied, a numerical value corresponding to the satisfied branch condition is returned from N +1 numerical values arranged in sequence, wherein any one branch condition includes a comparison of the sizes of private data held by each of the first party and the second party. Referring to fig. 1, the first party and the second party each have N private data for constructing N branch conditions, the first party has N private data of a0, … a (N-1), and the second party has N private data of b0, … b (N-1), each branch condition corresponds to a value returned when it is established, and the N branch conditions do not have a value returned when it is established, and there are N +1 possible returned values, which may be represented as c0, … cN, and all of the N +1 values are provided by the first party or the second party, or some of the N +1 values are provided by the first party and the other part is provided by the second party, for example, the first party provides c0, c1, c2, and the second party provides c3, … cN, and only the scenario where all of the N +1 values are provided by the first party is shown in the figure. The value returned after the multi-branch condition is executed can be directly provided for the first party and the second party, or the value returned after the multi-branch condition is executed can be distributed on the first party and the second party in a slicing mode, the slicing of the value obtained by the first party is marked as r0, the slicing of the value obtained by the second party is marked as r1, and the returned value is obtained after the r0 and the r1 are combined.
It will be appreciated that the above-described slicing of the values may be additive or exclusive-or slicing. Add-split (ADDShare), one number modulo 2nThe integer ring of the space is divided into two addition slices by subtraction, and the two addition slices are modulo 2nThe original number can be obtained by adding the integer ring of the space, and two parties respectively have an adding fragment. The add slices are unsigned numbers. Xor shard (XORShare), a string of bits is split into two bit shards with xor. The original bit string can be obtained by performing XOR on the two XOR fragments, and each party has one XOR fragment.
The branch condition includes a comparison operation, which may be <, >, or the like, and taking the comparison operation included in each branch condition as < as an example, the multi-branch condition may be used to complete the following calculation:
If a0<b0
return c0
elif a1<b1
return c1
……
elif a(N-1)<b(N-1)
return c(N-1)
else
return cN
it is understood that the multi-branch condition includes N branch conditions executed sequentially, the first branch condition is a0< b0, the comparison result corresponding to the branch condition is determined first, if the comparison result indicates that a0< b0 is true, the returned value is c0, and the subsequent branch condition is not executed, and if the comparison result indicates that a0< b0 is not true, the second branch condition is executed; the second branch condition is a1< b1, if a1< b1 holds, the returned value is c1 and no subsequent branch condition is performed, if a1< b1 does not hold, the third branch condition is performed; … …, respectively; the nth branch condition is a (N-1) < b (N-1), if a (N-1) < b (N-1) is true, the returned value is c (N-1), and if a (N-1) < b (N-1) is false, the returned value is cN.
Boolean circuit (boolean circuit): the method is a set of logic gates connected by connecting lines, and can complete function calculation on a set of inputs and output results. The logic gates include AND gates (AND), exclusive or gates (XOR), NOT gates (NOT), AND the like which implement boolean functions, AND generally a function can be compiled into a group of AND gates, exclusive or gates, AND NOT gates to complete calculation.
In the embodiment of the present specification, the comparison unit determines the comparison result of each of the N branch conditions, and the selection unit performs N rounds of selection processing on N values corresponding to the N branch conditions respectively in the order from the back to the front, so as to provide a specific way of implementing the two-party multi-branch condition through the boolean circuit, and implement the two-party multi-branch condition on the premise of protecting private data.
The structure of the boolean circuit of the invention will be explained in detail below on the basis of fig. 2.
Fig. 2 shows a schematic diagram of a boolean circuit architecture for implementing a two-way multi-branch condition according to an embodiment, which may be based on the implementation scenario shown in fig. 1. As shown in fig. 2, the boolean circuit 200 includes:
a comparison unit 21 for determining a comparison result for each of the N branch conditions; the N branch conditions respectively correspond to N numerical values which are sequentially arranged, and any branch condition comprises size comparison of privacy data held by a first party and privacy data held by a second party;
a selecting unit 22, configured to use the N +1 th numerical value as an initial value of the intermediate result, and respectively perform N rounds of selection processing on the N numerical values corresponding to the N branch conditions according to a sequence from back to front, where the N +1 th numerical value is a value when all branch conditions are not satisfied; each round of selection processing comprises: selecting one of the current value and the intermediate result of the previous round as the intermediate result of the current round according to the comparison result of the branch condition corresponding to the current value; and taking the intermediate result after the N rounds of selection processing as the processing result of the multi-branch condition.
It is to be understood that the above-described N-round selection processing is performed in reverse order of the execution of the normal multi-branch condition, and the N-round selection processing is performed in the order from the rear to the front, so as to realize the sequential execution of the multi-branch condition.
Optionally, as an embodiment, the comparing unit 21 further includes N comparing sub-units respectively corresponding to the N branch conditions;
each comparison subunit receives the private data to be compared of the corresponding branch condition and outputs the comparison result corresponding to the branch condition.
It can be understood that N comparison results are determined by the N comparison subunits, and may be represented as si — CMP _ CIRCUIT (ai, bi), where i has values from 0 to N-1, and respectively corresponds to N branch conditions, ai and bi represent private data to be compared for the corresponding branch conditions, and si represents the comparison result for the branch conditions. For example, the first branch condition is a0< b0, if a0< b0 holds, the comparison result s0 is 0, if a0< b0 does not hold, the comparison result s0 is 1; the second branch condition is a1< b1, if a1< b1 holds, the comparison result s1 is 0, if a1< b1 does not hold, the comparison result s1 is 1; … …, respectively; the Nth branch condition is a (N-1) < b (N-1), and if a (N-1) < b (N-1) is true, the comparison result s (N-1) is 0, and if a1< b1 is not true, the comparison result s (N-1) is 1.
Optionally, as an embodiment, the first party has N private data in a first private data set, the second party has N private data in a second private data set, and the comparison result is characterized based on whether a preset comparison relationship is satisfied between the first private data in the first private data set and the second private data in the second private data set.
Further, the preset comparison relationship includes at least one of:
less than, less than or equal to, greater than or equal to, greater than.
In an embodiment of the present description, each of the N branch conditions may correspond to the same preset comparison relationship, for example, all of the N branch conditions are smaller, or may correspond to different preset comparison relationships, for example, one branch condition corresponds to a preset comparison relationship smaller than the other branch condition corresponds to a preset comparison relationship larger than the other branch condition.
Optionally, as an embodiment, each of the N +1 values is l bits; the selection unit 22 further comprises N times l selection sub-units corresponding to respective ones of the N values, respectively;
each selection subunit receives the comparison result of the branch condition corresponding to the current value, the target bit of the current value and the target bit of the intermediate result of the previous round, and outputs the target bit of the intermediate result of the current round through a single AND gate.
For example, the N +1 values are c0, c1, … c (N-1), cN, each of which is l bits, and for c0, the bits can be respectively denoted as c0[0], c0[1], … c0[ l-1], and for cN, the bits can be respectively denoted as cN [0], cN [1], … cN [ l-1 ].
In the embodiment of the specification, the intermediate result can be assigned through the assignment gate. Assignment gates are a common type of logic gate that can be expressed as: c equals eqw (a) and c equals a.
And (3) taking the (N + 1) th numerical value as an initial value of the intermediate result, and assigning the (N + 1) th numerical value to the intermediate result through the (l) assignment gates. An assignment statement can be expressed as follows:
for i in range(0,l-1):
w[i]＝EQW(cN[i])
it will be appreciated that cN represents the N +1 th value, cN [ i ] represents the ith bit of cN, w represents the intermediate result, and w [ i ] represents the ith bit of w.
Further, the selecting subunit further comprises: the first exclusive-OR gate and the first AND gate are used as the single AND gate and the second exclusive-OR gate;
the first exclusive-or gate receives a target bit of a current value and the target bit of an intermediate result of a previous round and outputs a first intermediate value;
the first AND gate receives a comparison result of the branch condition corresponding to the first intermediate value and the current value and outputs a second intermediate value;
and the second exclusive-or gate receives the second intermediate value and the target bit of the current value and outputs the target bit of the intermediate result of the current round.
In this embodiment, the selection of a certain bit of the numerical value in each round of selection processing can be realized by two exclusive or gates and one and gate. Exclusive or gates and gates are common logic gates, and an exclusive or gate can be represented as: c ═ XOR (a, b), c ^ a ^ b; the AND gate may be represented as: AND c is AND (a, b), AND c is a & b.
The N comparison subunits and the N by l selection subunits may correspond to a loop statement as follows:
for i in range(0,N-1):
si＝CMP_CIRCUIT(ai,bi)
for j in range(0,l-1):
t0＝XOR(w[j],ci[j])
t1＝AND(t0,si)
w[j]＝XOR(t1,ci[j])
it is understood that N represents the number of branch conditions, ai and bi represent the private data to be compared for branch condition i, si represents the comparison result corresponding to branch condition i, ci represents the value corresponding to branch condition i, ci [ j ] represents the jth bit of ci, w represents the intermediate result, w [ j ] represents the jth bit of w, t0 represents the first intermediate value, and t1 represents the second intermediate value.
In the embodiment of the present specification, N rounds of selection processing are performed on N numbers of values corresponding to N branch conditions in the order from the back to the front, unlike the execution order of a normal loop statement, and when w is cN, ci is c (N-1), si is 0, the intermediate result of the first round is c (N-1), and when si is 1, the intermediate result of the first round is cN. For the selection processing of other rounds, the analogy can be repeated, and the details are not described herein.
Fig. 3 shows a schematic structural diagram of a selection subunit according to an embodiment. Referring to fig. 3, the selection subunit includes: a first exclusive or gate 31, a first and gate 32, and a second exclusive or gate 33;
the first exclusive-or gate 31 receives the target bit ci [ j ] of the current value and the target bit w [ j ] of the intermediate result of the previous round, and outputs a first intermediate value t 0;
the first and gate 32 receives the comparison result si of the branch condition corresponding to the first intermediate value t0 and the current value, and outputs a second intermediate value t 1;
the second xor gate 33 receives the second intermediate value t1 and the target bit ci [ j ] of the current value, and outputs the target bit w [ j ] of the intermediate result of the current round.
It will be appreciated that the N by l selection sub-units comprised by the selection unit 22, which correspond to respective ones of the N values, have the same structure, thus requiring a total of N by l and gates.
It should be noted that the circuit structure provided in the embodiments of this specification is not unique, and the function of the selection subunit can also be implemented by slightly modifying the circuit structure shown in fig. 3, as long as a single and gate is ensured.
Optionally, as an embodiment, the boolean circuit further includes:
and the splitting unit is used for splitting the processing result of the multi-branch condition into corresponding fragments and respectively outputting the fragments to the first party and the second party.
Optionally, as an embodiment, the boolean circuit employs an implementation of an obfuscation circuit.
A Garbled Circuit (GC), a two-party secure multi-party computing protocol, generates a garbled table with cryptographic functions for boolean circuits implementing a computation function, inputs the computation result to both parties, and does not leak the input to the other party during the computation. At present, the optimal implementation scheme of the garbled circuit does not need to communicate between the exclusive-or gate and the not gate, only needs local computation, and the and gate needs to call cryptographic computation and communicate, and the communication traffic is the bottleneck of the upper limit of throughput in a general application scenario. The amount of communication of the garbled circuit is positively correlated with the number of AND gates of the Boolean circuit.
In the embodiment of the present specification, any multi-branch condition is realized by a boolean circuit, and for N branches, that is, N comparisons, the number to be selected is N +1, each number is l bits, and the selection unit only needs N × l and gates. The circuit can complete calculation through one round of the garbled circuit, and the minimum communication cost can be achieved.
The boolean circuit provided by the embodiments of the present specification includes: a comparison unit 21 for determining a comparison result for each of the N branch conditions; the N branch conditions respectively correspond to N numerical values which are sequentially arranged, and any branch condition comprises size comparison of privacy data held by a first party and privacy data held by a second party; a selecting unit 22, configured to use the N +1 th numerical value as an initial value of the intermediate result, and respectively perform N rounds of selection processing on the N numerical values corresponding to the N branch conditions according to a sequence from back to front, where the N +1 th numerical value is a value when all branch conditions are not satisfied; each round of selection processing comprises: selecting one of the current value and the intermediate result of the previous round as the intermediate result of the current round according to the comparison result of the branch condition corresponding to the current value; and taking the intermediate result after the N rounds of selection processing as the processing result of the multi-branch condition. As can be seen from the above, in the embodiments of the present specification, the comparison unit determines the comparison result of each of the N branch conditions, and the selection unit respectively executes N rounds of selection processing on the N values corresponding to the N branch conditions according to a sequence from back to front, so as to provide a specific way of implementing the two-party multi-branch condition through the boolean circuit, and implement the two-party multi-branch condition on the premise of protecting the private data.
According to an embodiment of another aspect, there is also provided a computer-readable storage medium having stored thereon a computer program which, when executed in a computer, causes the computer to implement the boolean circuit described in connection with fig. 2.
According to an embodiment of yet another aspect, there is also provided a computing device comprising a memory having stored therein executable code, and a processor that, when executing the executable code, implements the boolean circuit described in connection with fig. 2.
Those skilled in the art will recognize that, in one or more of the examples described above, the functions described in this invention may be implemented in hardware, software, firmware, or any combination thereof. When implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium.
The above-mentioned embodiments, objects, technical solutions and advantages of the present invention are further described in detail, it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made on the basis of the technical solutions of the present invention should be included in the scope of the present invention.
Claims (10)
1. A boolean circuit for implementing a two-sided multi-branch condition, the boolean circuit comprising:
a comparison unit for determining a comparison result for each of the N branch conditions; the N branch conditions respectively correspond to N numerical values which are sequentially arranged, and any branch condition comprises size comparison of privacy data held by a first party and privacy data held by a second party;
the selection unit is used for respectively executing N rounds of selection processing on N numerical values corresponding to N branch conditions according to the sequence from back to front by taking the (N + 1) th numerical value as an initial value of an intermediate result, wherein the (N + 1) th numerical value is a value when all the branch conditions are not satisfied; each round of selection processing comprises: selecting one of the current value and the intermediate result of the previous round as the intermediate result of the current round according to the comparison result of the branch condition corresponding to the current value; and taking the intermediate result after the N rounds of selection processing as the processing result of the multi-branch condition.
2. The boolean circuit according to claim 1, wherein the comparison unit further includes N comparison sub-units corresponding to N branch conditions, respectively;
each comparison subunit receives the private data to be compared of the corresponding branch condition and outputs the comparison result corresponding to the branch condition.
3. The boolean circuit according to claim 1, wherein each of the N +1 numerical values is an l bit; the selection unit further comprises N times l selection sub-units respectively corresponding to each bit of the N numerical values;
each selection subunit receives the comparison result of the branch condition corresponding to the current value, the target bit of the current value and the target bit of the intermediate result of the previous round, and outputs the target bit of the intermediate result of the current round through a single AND gate.
4. The boolean circuit according to claim 3, wherein the selection subunit further includes: the first exclusive-OR gate and the first AND gate are used as the single AND gate and the second exclusive-OR gate;
the first exclusive-or gate receives a target bit of a current value and the target bit of an intermediate result of a previous round and outputs a first intermediate value;
the first AND gate receives a comparison result of the branch condition corresponding to the first intermediate value and the current value and outputs a second intermediate value;
and the second exclusive-or gate receives the second intermediate value and the target bit of the current value and outputs the target bit of the intermediate result of the current round.
5. The boolean circuit according to claim 1, wherein the boolean circuit further comprises:
and the splitting unit is used for splitting the processing result of the multi-branch condition into corresponding fragments and respectively outputting the fragments to the first party and the second party.
6. The boolean circuit according to claim 1, wherein the first party has N private data of a first set of private data, the second party has N private data of a second set of private data, the comparison result is characterized based on whether a preset comparison relationship is satisfied between the first private data of the first set of private data and the second private data of the second set of private data.
7. The boolean circuit according to claim 6, wherein the preset comparison relationship includes at least one of:
less than, less than or equal to, greater than or equal to, greater than.
8. The boolean circuit according to claim 1, wherein the boolean circuit employs an implementation of an obfuscation circuit.
9. A computer-readable storage medium, on which a computer program is stored, which, when executed in a computer, causes the computer to implement the boolean circuit according to any one of claims 1 to 8.
10. A computing device comprising a memory having executable code stored therein and a processor that, when executing the executable code, implements the boolean circuit of any one of claims 1-8.
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