CN113812124B - Predistortion parameter updating device and method and predistortion processing system - Google Patents
Predistortion parameter updating device and method and predistortion processing system Download PDFInfo
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Abstract
A predistortion parameter updating device (10) comprises at least two storage units (12), a control unit (13) and a processing unit (14), wherein each storage unit (12) is used for storing a sub-lookup table, each sub-lookup table stores a plurality of lines of predistortion parameters, all the sub-lookup tables are used for jointly forming a master lookup table, and each line of predistortion parameters in each sub-lookup table corresponds to one line of predistortion parameters in the master lookup table. The control unit (13) is used for controlling the processing unit (14) to read the predistortion parameters from the sub-lookup tables in the corresponding storage unit (12) according to the row numbers of the predistortion parameters to be updated in the parent lookup tables. The processing unit (14) is used for calculating the read predistortion parameters to obtain updated predistortion parameters and a write original address. The processing unit (14) asynchronously performs the read operation and the write operation of the same sub-lookup table, so that the read-write conflict in the predistortion parameter updating process is effectively avoided.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a predistortion parameter updating device and method, and a predistortion processing system.
Background
In a wireless communication system, a Power Amplifier (PA) is a key component of a transmitter system, and is mainly used for amplifying a modulated frequency band signal to a transmission Power required by an antenna for transmission, so as to ensure that a receiver can obtain a sufficiently strong signal. However, the power amplifier is the most dominant nonlinear source in the transmitter, on one hand, the nonlinearity can distort the transmitted signal, resulting in an increase in the system error rate; on the other hand, nonlinearity reduces the operating efficiency of the power amplifier, which tends to increase power consumption.
Digital Pre-Distortion (DPD) is one of the main approaches to solve the nonlinearity of power amplifiers. The digital predistortion technology achieves the purpose of counteracting nonlinearity brought by a power amplifier by compensating an input signal. When DPD is used for compensation, a predistortion parameter LUT (LUT) to be updated is read from a Look-Up Table (LUT) in a memory m (n-1) and then obtaining an updated predistortion parameter LUT m (n) and updating the LUT m (n) writing the original address in the lookup table. Thus, according to the above steps, the predistortion parameters corresponding to the (m+1) th row in the lookup table are obtained, and the nth iteration of all LUTs is completed. However, in the process of updating the predistortion parameters, if the predistortion parameters being updated are read, read-write collision is caused, and errors occur, so that the digital predistortion processing state is unstable.
Disclosure of Invention
The technical problem to be solved by the embodiments of the present application is to provide a predistortion parameter updating device and method for improving predistortion processing stability, and a predistortion processing system.
In order to achieve the above object, the embodiments of the present application adopt the following technical solutions:
in a first aspect, an embodiment of the present application provides a predistortion parameter updating apparatus, including at least two storage units, a control unit and a processing unit. Each storage unit is used for storing a sub-lookup table, each sub-lookup table stores a plurality of lines of predistortion parameters, all the sub-lookup tables are used for jointly forming a mother lookup table, and each line of predistortion parameters in each sub-lookup table corresponds to one line of predistortion parameters and one line number in the mother lookup table. The control unit is used for outputting a read enabling signal and a read address signal according to the predistortion parameters to be updated corresponding to the row numbers in the master lookup table, and the processing unit is used for reading the predistortion parameters from the sub lookup table where the predistortion parameters to be updated are located according to the read enabling signal and the read address signal. The processing unit is used for calculating the read predistortion parameters to obtain updated predistortion parameters, the control unit is used for outputting a write enabling signal and a write address signal according to the line numbers of the read predistortion parameters in the mother lookup table, the processing unit writes the updated predistortion parameters into the original addresses of the read predistortion parameters in the corresponding sub lookup tables according to the write enabling signal and the write address signal, and the processing unit asynchronously performs the read operation and the write operation of the same sub lookup table.
In this embodiment, an existing lookup table is divided into a plurality of sub-lookup tables, that is, sub-lookup tables stored in all storage units are used to jointly form a master lookup table, each row of predistortion parameters in each sub-lookup table corresponds to a row of predistortion parameters and a row number in the master lookup table, and the processing unit asynchronously performs reading and writing of the same sub-lookup table, so that reading and writing conflicts generated when reading and writing are performed on the sub-lookup table in the process of updating the predistortion parameters can be avoided, and stability and processing speed of predistortion processing are improved.
In an embodiment, the at least two storage units include a first storage unit and a second storage unit, the first storage unit is configured to store the first sub-lookup table, the second storage unit is configured to store a second sub-lookup table, the first sub-lookup table stores a first predistortion parameter, the second sub-lookup table stores a second predistortion parameter, and the first predistortion parameter is a LUT 2j (n) the second predistortion parameter is LUT 2j+1 (n) the LUT 2j (n) corresponding predistortion parameter LUT m An even line number predistortion parameter in (n), said LUT 2j+1 (n) corresponding predistortion parameter LUT m An odd-numbered line predistortion parameter of (n), wherein M is the line number, M = 0 … M-1; n is the iteration number, n= … N;2j is an even number of rows, (2j+1)For odd line numbers, j=0, 1,2 …, the processing unit is configured to read a first predistortion parameter from the first sub-lookup table, calculate according to the read first predistortion parameter to obtain a first updated predistortion parameter, and write the first updated predistortion parameter into the original address of the first sub-lookup table where the read first predistortion parameter is located; the processing unit is used for reading a second predistortion parameter from a second sub-lookup table where the predistortion parameter to be updated is located, calculating according to the read second predistortion parameter to obtain a second updated predistortion parameter, and writing the second updated predistortion parameter into the original address of the read second sub-lookup table where the second predistortion parameter is located.
In this embodiment, the processing unit is configured to perform the predistortion operation according to the predistortion parameter LUT m The alternate use of the first sub-lookup table and the second sub-lookup table for the row number in (n) is beneficial to reducing the computational cost while saving the computational resources.
In one embodiment, the processing unit is spaced an odd number of clock cycles between read and write operations for predistortion parameters of the same row in the same sub-lookup table to avoid collisions between read and write operations in the same sub-lookup table.
In an embodiment, when the processing unit reads a row of first predistortion parameters from the first sub-lookup table, writing the acquired row of second updated predistortion parameters into a second sub-lookup table; and when the processing unit reads a row of second predistortion parameters from the second sub-lookup table, writing the acquired row of first updated predistortion parameters into the first sub-lookup table.
In this embodiment, the processing unit performs a read operation on the first sub-lookup table and performs a write operation on the second sub-lookup table at the same time, and the processing unit performs a read operation on the second sub-lookup table at the same time as performing a write operation on the first sub-lookup table, which is beneficial to improving the processing speed of the predistortion parameter update.
In an embodiment, when the processing unit reads a row of first predistortion parameters from the first sub-lookup table, reads a row of second predistortion parameters from the first sub-lookup table, and when the processing unit writes the acquired row of first update predistortion parameters into the first sub-lookup table, writes the acquired row of second update predistortion parameters into the second sub-lookup table.
In this embodiment, the processing unit performs a read operation on the first sub-lookup table and performs a read operation on the second sub-lookup table at the same time, and the processing unit performs a write operation on the second sub-lookup table at the same time as performing a write operation on the first sub-lookup table, which is beneficial to improving the processing speed of the predistortion parameter update.
In one embodiment, the memory cell is a single-port random access memory and the memory cell is a single-port random access memory. Because the single-port random access memory occupies a small space, the occupied space of the predistortion parameter updating device is reduced, the area of an application specific integrated circuit (chip) is reduced, and the power consumption and the use cost of the predistortion parameter updating device are reduced.
In an embodiment, the memory units are dual-port random access memories, so that the efficiency of reading and updating the predistortion parameters can be further improved.
In an embodiment, one of the first memory cell and the second memory cell is a single-port random access memory, and the other of the first memory cell and the second memory cell is a dual-port random access memory, and the dual-port random access memory can improve the efficiency of reading and updating predistortion parameters due to the small occupied space of the single-port random access memory.
In a second aspect, an embodiment of the present application provides a predistortion system, including a predistortion parameter updating device, a predistortion compensation device and a power amplifier as described above, where the processing unit is configured to calculate a predistortion parameter to be updated to obtain an updated predistortion parameter, and includes: the processing unit is used for according to LUT m (n)＝LUT m (n-1) +alpha.e (n). X (n-m) to obtain updated predistortion parameter LUT m (n), wherein x (n) is an input signal, e (n) is an error between the input signal x (n) and a feedback signal y (n), the feedback signal y (n) is a sampling signal coupled back through the power amplifier, and LUT m (n-1) predistortion parameters to be updated, said predistortion compensation means being for using an updated predistortion parameter LUT provided from said predistortion parameter updating means m (n) pre-distorting the input signal x (n) to obtain a compensated output signal, and the power amplifier is further configured to power amplify the compensated output signal to achieve a required transmit power.
In a third aspect, an embodiment of the present application provides a predistortion parameter updating method, configured to update predistortion parameters stored in at least two sub-lookup tables, where all the sub-lookup tables are configured to together form a mother lookup table, and each row of predistortion parameters in each sub-lookup table corresponds to a row of predistortion parameters and a row number in the mother lookup table, where the method includes the following steps: outputting a read enabling signal and a read address signal according to the line number of the predistortion parameter to be updated in the mother lookup table; reading predistortion parameters from the corresponding sub-lookup tables according to the reading enabling signals and the reading address signals; calculating according to the read predistortion parameters to obtain updated predistortion parameters; outputting a write enabling signal and a write address signal according to the read predistortion parameters in the row number of the mother lookup table; and writing the updated predistortion parameters into original addresses of the read predistortion parameters in the corresponding sub-lookup tables according to the write enabling signals and the write address signals, wherein the read operation and the write operation of the same sub-lookup table are performed asynchronously.
In an embodiment, the at least two sub-lookup tables include a first sub-lookup table and a second sub-lookup table, the first sub-lookup table stores a first predistortion parameter, the second sub-lookup table stores a second predistortion parameter, and the first predistortion parameter is a LUT 2j (n) the second predistortion parameter is LUT 2j+1 (n) the LUT 2j (n) corresponding predistortion parameter LUT m An even line number predistortion parameter in (n), said LUT 2j+1 (n) corresponding predistortion parametersLUT m An odd-numbered line predistortion parameter of (n), wherein M is the line number, M = 0 … M-1; n is the iteration number, n= … N;2j is an even line number, (2j+1) is an odd line number, j=0, 1,2 …, and the reading the predistortion parameters from the sub-lookup table where the predistortion parameters to be updated are located according to the read enable signal and the read address signal includes: reading a first predistortion parameter from a first sub-lookup table in which the predistortion parameter to be updated is located according to the read enable signal and the read address signal, and reading a second predistortion parameter from a second sub-lookup table in which the predistortion parameter to be updated is located according to the read enable signal and the read address signal, wherein the calculating according to the read predistortion parameter to obtain the updated predistortion parameter includes: and calculating according to the read first predistortion parameters to obtain first updated predistortion parameters, and calculating according to the read second predistortion parameters to obtain second updated predistortion parameters. The controlling writing the updated predistortion parameters to the original address in the corresponding sub-lookup table includes: writing the first updated predistortion parameters into the original address of a first sub-lookup table where the first predistortion parameters are located, and writing the second updated predistortion parameters into the original address of a second sub-lookup table where the second predistortion parameters are located.
In one embodiment, the method further comprises: the read and write operations for predistortion parameters for the same row in the same sub-lookup table are separated by an odd number of clock cycles.
In one embodiment, the method further comprises: when a row of first predistortion parameters are read from the first sub-lookup table, writing the acquired row of second updated predistortion parameters into a second sub-lookup table; and when a row of second predistortion parameters are read from the second sub-lookup table, writing the acquired row of first updated predistortion parameters into the first sub-lookup table.
In an embodiment, the method further comprises reading a row of first predistortion parameters from the first sub-lookup table, reading a row of second predistortion parameters from the second sub-lookup table, and writing the acquired row of second update predistortion parameters into the second sub-lookup table when writing the acquired row of first update predistortion parameters into the first sub-lookup table.
In a fourth aspect, an apparatus is provided. The apparatus provided herein has means (means) for performing the steps or functions described by the method aspects described above. The steps or functions may be implemented in software, or in hardware (e.g., circuitry), or in a combination of hardware and software.
In one possible design, the apparatus includes one or more processors.
Optionally, the apparatus may further comprise one or more memories for coupling with the processor, which holds the program instructions and/or data necessary for the apparatus. The one or more memories may be integrated with the processor or may be separate from the processor. The present application is not limited thereto.
The device may be an intelligent terminal or a wearable device, etc.
The device may also be a chip.
In another possible design, the apparatus includes a processor and a memory, where the memory is configured to store a set of program codes, and the processor is configured to invoke the program codes stored in the memory, so that the apparatus performs the method performed in the possible implementation manner of the third aspect.
In a fifth aspect, a computer readable storage medium is provided for storing a computer program comprising instructions for performing the method in a possible implementation of the third aspect.
In a sixth aspect, there is provided a computer program product comprising: computer program code which, when run on a computer, causes the computer to perform the method of the third aspect and any of the possible implementations of the third aspect.
Drawings
Fig. 1 is a schematic diagram of an operating state of a predistortion processing system provided in the present application.
Fig. 2 is a schematic diagram of a mother lookup table formed by a first sub-lookup table and a second sub-lookup table according to an embodiment of the present application.
Fig. 3 is a schematic diagram of partial predistortion parameter updating of a first sub-lookup table and a second sub-lookup table according to an embodiment of the present application.
FIG. 4a is a schematic diagram showing the comparison of the area of two single-port random access memories with that of a conventional dual-port random access memory.
FIG. 4b is a diagram showing the comparison of power consumption of two single-port random access memories with that of a conventional dual-port random access memory.
Fig. 5 is a schematic diagram of partial predistortion parameter updating of a first sub-lookup table and a second sub-lookup table according to an embodiment of the present application.
Fig. 6 is a flowchart of a predistortion processing method according to an embodiment of the present application.
Fig. 7 is a schematic diagram of a composition of another predistortion parameter updating apparatus according to an embodiment of the present application.
Detailed Description
Referring to fig. 1, fig. 1 is a schematic diagram illustrating an operation state of a predistortion processing system 100 provided in the present application. The predistortion processing system 100 includes a predistortion parameter updating device 10, a predistortion compensation device 20 and a power amplifier 40. The predistortion parameter updating device 10 obtains predistortion parameters according to the input signal (x (n)) and the feedback signal (z (n)), and the predistortion compensation device 20 performs predistortion processing (i.e. compensation) on the input signal by using the predistortion parameters provided by the predistortion parameter updating device 10 to obtain a compensated output signal (y (n)), thereby achieving the purpose of counteracting the nonlinearity of the power amplifier. The power amplifier 40 is also used to power amplify the compensated output signal to achieve the required transmit power.
The predistortion processing system 100 is applied to the field of communication, wherein the input signal refers to a signal that is input to the predistortion processing system 100 for predistortion processing, and the feedback signal is a sampling signal coupled back through the power amplifier 40. The predistortion process is a digital predistortion process (DPD process for short). It will be appreciated that the predistortion processing system 100 may be applied to other fields where predistortion processing of signals is desired, such as artificial intelligence, financial prediction, natural weather modeling, and the like. For example, the field of neural networks, and the like.
The predistortion processing system 100 further comprises a digital-to-analog converter 30 and an analog-to-digital converter 50, wherein the digital-to-analog converter 30 performs digital-to-analog conversion on the compensation output signal, and the analog-to-digital converter 50 performs digital-to-analog conversion on the feedback signal.
The predistortion parameter updating device 10 comprises at least two storage units 12, a control unit 13 and a processing unit 14.
Each memory unit 12 is adapted to store a sub-look-up table, each sub-look-up table holding a plurality of rows of predistortion parameters. Each sub-lookup table stores a plurality of lines of predistortion parameters, and all the sub-lookup tables are used for jointly forming a mother lookup table, and each line of predistortion parameters in each sub-lookup table corresponds to one line of predistortion parameters and one line number in the mother lookup table.
The control unit 13 is configured to output a read enable signal and a read address signal according to a row number of the predistortion parameter to be updated in the mother lookup table, and the processing unit 14 is configured to read the predistortion parameter from the sub lookup table in the corresponding storage unit 12 according to the read enable signal and the read address signal.
The processing unit 14 is configured to calculate the read predistortion parameters to obtain updated predistortion parameters. The control unit is configured to output a write enable signal and a write address signal according to a line number of the read predistortion parameter in the mother lookup table, and the processing unit 14 writes the updated predistortion parameter into an original address of the read predistortion parameter in the corresponding child lookup table according to the write enable signal and the write address signal. The processing unit 14 performs the read and write operations asynchronously for the same sub-lookup table.
Because each storage unit 12 stores one sub-lookup table, all the sub-lookup tables are used to jointly form one mother lookup table, and each row of predistortion parameters in each sub-lookup table corresponds to one row of predistortion parameters in the mother lookup table, the update speed of the predistortion parameters and the stability of predistortion processing are improved. The processing unit 14 asynchronously performs the read operation and the write operation on the same sub-lookup table, so that the read-write conflict generated when the sub-lookup table is read and written in the predistortion parameter updating process is avoided, and the stability of predistortion processing is improved.
In the present embodiment, the processing unit 14 performs the read operation and the write operation to the same sub-lookup table in different clock cycles. In one clock cycle, the processing unit 14 reads a row of predistortion parameters in one sub-lookup table, or the processing unit 14 writes corresponding updated predistortion parameters obtained according to the read row of predistortion parameters in the sub-lookup table into the same sub-lookup table. I.e. for one sub-look-up table, the processing unit 14 only performs read operations or the processing unit 14 only performs write operations in one clock cycle.
The compensated output signal y (n) is expressed as the following equation:
wherein w is m,q For predistortion coefficients, LUT m (|x (n-m) |) is a predistortion parameter, and m is LUT m (|x (n-m is the line number in the middle, n is the iteration number).
According to LMSE algorithm, let
LUT m (|x(n-m)|)＝LUT m (n) (3)
LUT (look-up table) m (n)＝LUT m (n-1)+α·e(n)·x(n-m),m＝0…M-1 (4)
Where e (n) represents the error between the input signal x (n) and the feedback signal z (n), α being an adjustable parameter.
According to LUT m Line number m of (n), decomposing the formula (3) into:
LUT 2j (n)＝LUT 2j (n-1)+α·e(n)·x(n-m)，j＝0,1,2… (5)
LUT 2j+1 (n)＝LUT 2j+1 (n-1)+α·e(n)·x(n-m)，j＝0,1,2… (6)
in other words, m may be 2j or (2j+1), i.e., dividing the line number m into an even line number 2j and an odd line number (2j+1), and dividing the predistortion parameter LUT m (n) decomposition into a first predistortion parameter LUT 2j (n), and a second predistortion parameter LUT 2j+1 (n). In other words, LUT 2j (n) corresponding predistortion parameter LUT m Even line number predistortion parameters in (n), LUT 2j+1 (n) corresponding predistortion parameter LUT m Odd-numbered line-numbered predistortion parameters in (n).
The storage unit 12 includes a first storage unit 122 and a second storage unit 124, the first storage unit 122 is used for storing a first sub-lookup table, the second storage unit 124 is used for storing a second sub-lookup table, and the first sub-lookup table stores a first predistortion parameter LUT with even line numbers 2j (n) the second sub-lookup table stores the odd-numbered predistortion parameters LUT 2j+1 (n). j is the row number of the first sub-lookup table and the second sub-lookup table. The first and second sub-lookup tables together form a mother lookup table (shown in FIG. 2), m is the line number of the mother lookup table, and the predistortion parameters in the mother lookup table are expressed as LUTs m (n). Each row of predistortion parameters in each sub-lookup table corresponds to a row of predistortion parameters in the parent lookup table, e.g. when j=1, i.e. the first predistortion parameter LUT of row 2 in the first sub-lookup table 2 (n) corresponding to the predistortion parameter LUT with line number 3 in the mother lookup table 2 (n)。
The processing unit 14 is used for obtaining the first predistortion parameters as LUT 2j (n) performing a calculation to obtain a first updated predistortion parameter as a LUT 2j (n+1) and updating the first predistortion parameter LUT 2j (n+1) writing a first predistortion parameter LUT 2j (n) the source address of the first sub-lookup table where it is located.
The processing unit 14 is used for obtaining the second predistortion parameters as LUT 2j+1 (n) performing a calculation to obtain a second updated predistortion parameter LUT 2j+1 (n+1) and updating the predistortion parameters LUT 2j+1 (n+1) writing the first predistortionParameter LUT 2j+1 (n) the source address of the second sub-lookup table where it is located. In one iteration, the first updated predistortion parameters of the first sub-lookup table are written as the first predistortion parameters to be replaced for the next iteration, and the loop is performed. And writing a second updated predistortion parameter of a second sub-lookup table in one iteration as a second predistortion parameter to be replaced of the next iteration.
Wherein, for the same sub-lookup table, the read operation and the write operation of the processing unit 14 are performed in different clock cycles, respectively.
And the reading and writing of the first sub-lookup table and the reading and writing of the second sub-lookup table are performed asynchronously, so that the reading and writing conflict between the first sub-lookup table and the second sub-lookup table is avoided, and the stability of predistortion processing is improved.
When the first storage unit 122 where the first sub-lookup table is located provides the predistortion parameters to the processing unit 14, the processing unit 14 updates the second predistortion parameters in the second sub-lookup table. After the predistortion parameters stored in the second sub-lookup table of the second storage unit 124 are updated, the second storage unit 124 provides the second predistortion parameters stored in the second sub-lookup table to the processing unit 14. The processing unit 14 updates the first predistortion parameters stored in the first sub-lookup table while the processing unit 14 reads the second predistortion parameters stored in the second sub-lookup table. After the first predistortion parameters stored in the first sub-lookup table of the first storage unit 122 are updated, the first storage unit 122 provides the first predistortion parameters stored in the first sub-lookup table to the processing unit 14, and the process loops.
Further, the processing unit 14 includes a first sub-processing unit 141, a second sub-processing unit 142, a third sub-processing unit 143, a fourth sub-processing unit 144, a fifth sub-processing unit 145, and a sixth sub-processing unit 146.
The first sub-processing unit 141 is configured to obtain an error e (n) between the input signal x (n) and the feedback signal z (n).
The second sub-processing unit 142 is configured to obtain the current iteration number output by the control unit 13, the line number of the predistortion parameter to be updated, and select x (n-M) from x (n), x (n-1) … x (n-M-1).
The third sub-processing unit 143 is configured to obtain a product of e (n) ·x (n-m) according to the selected x (n-m).
The fourth sub-processing unit 144 is configured to obtain a product α·e (n) ·x (n-m).
The fifth sub-processing unit 145 is used for reading LUT according to the read enable signal and the read address signal m (n-1) and obtaining the updated predistortion parameter LUT according to equation (4) m (n). The fifth sub-processing unit 145 is used for updating the predistortion parameter LUT according to the write enable signal and the write address signal m (n) writing the original address in the corresponding sub-lookup table. Wherein, when m is 2j, the fifth sub-processing unit 145 is configured to read the first predistortion parameter LUT 2j (n-1) and obtaining a first updated predistortion parameter LUT in accordance with equation (5) 2j (n) and updating the first predistortion parameter LUT 2j (n) writing a first predistortion parameter LUT 2j (n-1) the original address. When m is (2j+1), the fifth sub-processing unit 145 is configured to read the second predistortion parameter LUT 2j+1 (n-1) and obtaining a second updated predistortion parameter LUT in accordance with equation (6) 2j+1 (n) and updating the second predistortion parameter LUT 2j+1 (n) writing to LUT 2j+1 (n-1) the original address.
The sixth sub-processing unit 146 is configured to delay the processing of the predistortion parameters in the sub-lookup table by the fifth sub-processing unit 145. For example, at clock cycle 0, the fifth sub-processing unit 145 reads the LUT in the first sub-lookup table 0 (n); at clock cycle 1, the fifth sub-processing unit 145 is not operating, and at clock cycle 2, the fifth sub-processing unit 145 reads the LUT in the first sub-lookup table 2 (n), i.e. the sixth sub-processing unit 146 delays the fifth sub-processing unit 145 from reading the LUT 2 (n)。
The processing unit 14 further comprises a seventh processing unit, for example the seventh processing unit is a delay unit. The processing unit 14 may include an eighth processing unit for performing down-conversion frequency, filtering, image removal, amplitude adjustment, phase adjustment processing, and the like on the feedback signal.
The predistortion parameter updating apparatus 10 further comprises a delay alignment unit 16. The delay alignment unit 16 is configured to delay the input signal (x (n)) to ensure that the input signal (x (n)) and the feedback signal (z (n)) are aligned in time, so that the error signal (e (n)) is correctly calculated.
To read predistortion parameter LUT from first sub-lookup table 2j (n-1) is described for simplicity. The control unit 13 updates the predistortion parameters LUT according to the required update 2j (n-1) outputting a read enable signal and a read address signal at the row number 2j in the mother lookup table, and the processing unit 14 reads the first predistortion parameter LUT to be updated stored in the first storage unit 122 according to the read enable signal and the read address signal 2j (n-1) the processing unit 14 generates a first predistortion parameter LUT based on the read first predistortion parameter LUT 2j (n-1), the input signal (x (n)) and the feedback signal z (n) are processed to obtain a corresponding first updated predistortion parameter LUT 2j (n). The control unit 13 generates a predistortion parameter LUT based on the read predistortion parameter LUT 2j (n-1) outputting a write enable signal and a write address signal at row number 2j in the mother lookup table. The processing unit 14 updates the obtained first updated predistortion parameter LUT according to the write enable signal and the write address signal 2j (n) writing a first predistortion parameter LUT 2j (n-1) updating the predistortion parameters corresponding to the row number 2j in the mother lookup table at the original address in the first child lookup table. Predistortion compensation means 20 extracts predistortion parameter LUT in predistortion parameter updating means 10 2j (n) predistortion processing is performed on the input signal x (n) to obtain a compensated input signal y (n). The digital-to-analog converter 30 performs digital-to-analog conversion on the compensated output signal y (n), and the power amplifier 40 amplifies the digital-to-analog converted compensated output signal y (n) to achieve the required transmission power.
Referring to fig. 3, fig. 3 is a schematic diagram illustrating the alternate operation of the first sub-lookup table and the second sub-lookup table according to the embodiment of the present application. The first memory unit 122 is a single-port random access memory, and is denoted as SP-RAM0; the second memory unit 124 is also a single-port random access memory, denoted as SP-RAM1; clock is the clock period. The single-port random access memory generally has only one set of data lines and address lines, and cannot be read and written at the same time.
At the 0 th timeThe processing unit 14 reads the first predistortion parameter LUT stored in the first sub-lookup table 0 (n) the processing unit 14 does not perform read and write operations on the second sub-lookup table.
At clock cycle 1, the processing unit 14 reads the second predistortion parameter LUT stored in the second sub-lookup table 1 (n) the processing unit 14 does not perform read and write operations on the first sub-lookup table.
At clock cycle 2, the processing unit 14 reads the first predistortion parameter LUT stored in the first sub-lookup table 2 (n) the processing unit 14 does not perform read and write operations on the second sub-lookup table.
At clock cycle 3, the processing unit 14 will read the first predistortion parameter LUT 0 (n) the acquired first updated predistortion parameter LUT 0 (n+1) writing a first predistortion parameter LUT 0 (n) implementing the first predistortion parameter LUT stored in the first sub-lookup table at the original address in the first sub-lookup table 0 (n) updating to LUT 0 (n+1) reading a second predistortion parameter LUT stored in the second sub-lookup table 3 (n)。
At clock cycle 4, the processing unit 14 reads the first predistortion parameter LUT stored in the first sub-lookup table 4 (n) the processing unit 14 updates the predistortion parameter LUT with the obtained second update predistortion parameter LUT 1 (n+1) writing a second predistortion parameter LUT 1 (n) the original address … … in the second sub-lookup table, and the processing unit 14 reads the first predistortion parameter LUT stored in the first sub-lookup table at the ith clock cycle 2j (n) the processing unit 14 updates the predistortion parameter LUT with the obtained second update predistortion parameter LUT 2j-3 (n+1) writing a second predistortion parameter LUT 2j-3 (n) the original address in the second sub-lookup table.
In this way, the processing unit 14 acquires the corresponding updated predistortion parameters from the predistortion parameters read from each sub-lookup table, and writes the acquired updated predistortion parameters to the original addresses in the corresponding sub-lookup table.
In some embodiments, the read and write operations alternate in clock cycle order in the same sub-lookup table.
In this embodiment, the read-write collision is avoided for the 3 clock cycles between the read and write operations of the predistortion parameters of the same row in the same sub-lookup table. It will be appreciated that the same sub-lookup table corresponds to an odd number of clock cycles, e.g. 1,5,7, …, etc., between read and write operations of the predistortion parameters.
In the present embodiment, since the first memory unit 122 and the second memory unit 124 are both single-port random access memories, the chip area is reduced, the power consumption is reduced, and the chip cost and the usage cost are reduced without increasing the memory size.
It is understood that the memory cell 12 is not limited to a random access memory, and the memory cell 12 may be other types of memory, such as nonvolatile memory types, e.g., ferroelectric memory, phase change memory, magnetic memory, resistive memory, and so forth.
Referring to fig. 4a and 4b, fig. 4a is a schematic diagram comparing the area of two single-port random access memories with that of a conventional dual-port random access memory, and fig. 4b is a schematic diagram comparing the power consumption of two single-port random access memories with that of a conventional dual-port random access memory. Compared with the existing dual-port access memory capable of simultaneously reading and writing, the memory occupation area can be effectively reduced by 40% by adopting two single-port random access memories; at 491MHz clock, the total power consumption of the memory used by predistortion parameter updating apparatus 10 is reduced by 14%, thus facilitating a reduction in chip cost and usage cost in application specific integrated circuit (Application Specific Integrated Circuit, abbreviated as ASIC) applications.
In one embodiment, the first memory unit 122 is a dual-port random access memory, and the second memory unit 124 is a dual-port random access memory. Referring to fig. 5, fig. 5 is a schematic diagram illustrating partial predistortion parameter updating of a first sub-lookup table and a second sub-lookup table according to another embodiment of the present application. The processing unit 14 reads and writes the first sub-lookup table stored in the first storage unit 122 and reads and writes the second sub-lookup table stored in the second storage unit 124, similar to fig. 3, and will not be described herein.
In one embodiment, one of the first memory cell 122 and the second memory cell 124 is a single-port random access memory, and the other is a dual-port random access memory. The dual-port random access memory generally has two sets of data lines and address lines, and can perform reading and writing at the same time.
It can be understood that the number of the sub-lookup tables is not limited, and three or more sub-lookup tables, i.e. LUTs, can be arranged m (n) dividing into a plurality of parts corresponding to the number of sub-lookup tables, each sub-lookup table storing LUTs m Predistortion parameters for part of the number of lines in (n).
Referring to fig. 6, fig. 6 is a flow chart of a predistortion parameter updating method according to an embodiment of the present application.
A predistortion parameter updating method for updating predistortion parameters stored in at least two sub-lookup tables, all sub-lookup tables being used to jointly form a mother lookup table, each row of predistortion parameters in each sub-lookup table corresponding to a row of predistortion parameters in the mother lookup table, the method comprising the steps of:
In an embodiment, the at least two sub-lookup tables include a first sub-lookup table and a second sub-lookup table, the first sub-lookup table stores a first predistortion parameter, the second sub-lookup table stores a second predistortion parameter, and the first predistortion parameter is a LUT 2j (n) the second predistortion parameter is LUT 2j+1 (n) the LUT 2j (n) corresponding predistortion parameter LUT m An even line number predistortion parameter in (n), said LUT 2j+1 (n) corresponding predistortion parameter LUT m An odd-numbered line predistortion parameter of (n), wherein M is the line number, M = 0 … M-1; n is the iteration number, n= … N;2j is an even line number, (2j+1) is an odd line number, j=0, 1,2 ….
The reading the predistortion parameters from the sub-lookup table where the predistortion parameters to be updated are located according to the read enable signal and the read address signal comprises: reading a first predistortion parameter from a first sub-lookup table where the predistortion parameter to be updated is located according to the reading enabling signal and the reading address signal, and reading a second predistortion parameter from a second sub-lookup table where the predistortion parameter to be updated is located according to the reading enabling signal and the reading address signal.
The calculating according to the read predistortion parameters to obtain updated predistortion parameters comprises: and calculating according to the read first predistortion parameters to obtain first updated predistortion parameters, and calculating according to the read second predistortion parameters to obtain second updated predistortion parameters.
The controlling writing the updated predistortion parameters to the original address in the corresponding sub-lookup table includes: writing the first updated predistortion parameters into the original address of a first sub-lookup table where the first predistortion parameters are located, and writing the second updated predistortion parameters into the original address of a second sub-lookup table where the second predistortion parameters are located.
In one embodiment, the method further comprises: the read and write operations for predistortion parameters for the same row in the same sub-lookup table are separated by an odd number of clock cycles.
In one embodiment, the method further comprises: when a row of first predistortion parameters are read from the first sub-lookup table, writing the acquired row of second updated predistortion parameters into a second sub-lookup table; and when a row of second predistortion parameters are read from the second sub-lookup table, writing the acquired row of first updated predistortion parameters into the first sub-lookup table.
In one embodiment, the method further comprises; reading a row of first predistortion parameters from the first sub-lookup table, reading a row of second predistortion parameters from the second sub-lookup table, and writing the acquired row of second update predistortion parameters into the second sub-lookup table when writing the acquired row of first update predistortion parameters into the first sub-lookup table.
Fig. 7 is a schematic diagram of another predistortion parameter updating apparatus according to an embodiment of the present application. As shown in fig. 7, the predistortion parameter updating apparatus 200 may include a processor 210 and a memory 220. The memory 220 is configured to store instructions, and the processor 210 is configured to execute the instructions stored in the memory 220 to implement the steps performed by the predistortion parameter updating apparatus in the method corresponding to fig. 1.
The processor 210 is configured to execute the instructions stored in the memory 220 to perform the steps performed by the predistortion parameter updating apparatus in the method described above. The memory 220 may be integrated into the processor 210 or may be provided separately from the processor 210.
As an implementation, the processor 210 may be considered to be implemented by a dedicated processing chip, a processing circuit, a processor, or a general-purpose chip.
As another implementation manner, a manner of using a general purpose computer may be considered to implement the terminal provided in the embodiments of the present application.
The concepts related to the technical solutions provided in the embodiments of the present application, explanation and detailed description and other steps related to the predistortion parameter updating device refer to the descriptions of these contents in the foregoing methods or other embodiments, and are not repeated herein.
Those skilled in the art will appreciate that only one memory and processor is shown in fig. 7 for ease of illustration. In an actual controller, there may be multiple processors and memories. The memory may also be referred to as a storage medium or storage device, etc., and embodiments of the present application are not limited in this regard.
It should be appreciated that in embodiments of the present application, the processor may be a central processing unit (Central Processing Unit, CPU for short), other general purpose processor, digital signal processor (Digital Signal Processing, DSP for short), application specific integrated circuit (Application Specific Integrated Circuit, ASIC for short), off-the-shelf programmable gate array (Field-Programmable Gate Array, FPGA for short) or other programmable logic device, discrete gate or transistor logic device, discrete hardware components, or the like.
The memory may include read only memory and random access memory and provide instructions and data to the processor. A portion of the memory may also include non-volatile random access memory.
In implementation, the steps of the above method may be performed by integrated logic circuits of hardware in a processor or by instructions in the form of software. The steps of a method disclosed in connection with the embodiments of the present application may be embodied directly in a hardware processor for execution, or in a combination of hardware and software modules in the processor for execution. The software modules may be located in a random access memory, flash memory, read only memory, programmable read only memory, or electrically erasable programmable memory, registers, etc. as well known in the art. The storage medium is located in a memory, and the processor reads the information in the memory and, in combination with its hardware, performs the steps of the above method. To avoid repetition, a detailed description is not provided herein.
In various embodiments of the present application, the sequence number of each process does not mean the sequence of execution, and the execution sequence of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.
Those of ordinary skill in the art will appreciate that the various illustrative logical blocks (illustrative logical block, abbreviated ILBs) and steps described in connection with the embodiments disclosed herein can be implemented in electronic hardware, or in combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.
In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, produces a flow or function in accordance with embodiments of the present application, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by a wired (e.g., coaxial cable, fiber optic, digital subscriber line), or wireless (e.g., infrared, wireless, microwave, etc.). The computer readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that contains an integration of one or more available media. The usable medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid state disk), etc.
The foregoing is merely specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present application, and the changes and substitutions are intended to be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (11)
1. A predistortion parameter updating device is characterized by comprising at least two storage units, a control unit and a processing unit,
each memory unit is used for storing a sub-lookup table, each sub-lookup table stores a plurality of lines of predistortion parameters, all the sub-lookup tables are used for jointly forming a mother lookup table, each line of predistortion parameters in each sub-lookup table corresponds to one line of predistortion parameters in the mother lookup table,
the control unit is used for outputting a read enabling signal and a read address signal according to the line number of the predistortion parameter to be updated in the master lookup table, the processing unit is used for reading the predistortion parameter from the sub lookup table in the corresponding storage unit according to the read enabling signal and the read address signal,
the processing unit is used for calculating the read predistortion parameters to obtain updated predistortion parameters, the control unit is used for outputting write enabling signals and write address signals according to the line numbers of the read predistortion parameters in the mother lookup table, the processing unit writes the updated predistortion parameters into the original addresses of the read predistortion parameters in the corresponding sub lookup tables according to the write enabling signals and the write address signals,
The at least two storesThe unit comprises a first storage unit and a second storage unit, wherein the first storage unit is used for storing a first sub-lookup table, the second storage unit is used for storing a second sub-lookup table, the first sub-lookup table stores a first predistortion parameter, the second sub-lookup table stores a second predistortion parameter, and the first predistortion parameter is
The second predistortion parameter is +.>
Said->
Corresponding predistortion parameters->
The even line number predistortion parameters of +.>
Corresponding predistortion parameters->
The odd number of the predistortion parameters in (a), wherein m is the line number,
n is the iteration number, < >>
The method comprises the steps of carrying out a first treatment on the surface of the 2j is even line number, (2j+1) is odd line number, +.>
，
The processing unit is used for reading a first predistortion parameter from the first sub-lookup table, calculating according to the read first predistortion parameter to obtain a first updated predistortion parameter, and writing the first updated predistortion parameter into the original address of the first sub-lookup table where the read first predistortion parameter is located;
the processing unit is configured to read a second predistortion parameter from a second sub-lookup table where the predistortion parameter to be updated is located, calculate the second predistortion parameter according to the read second predistortion parameter to obtain a second updated predistortion parameter, and write the second updated predistortion parameter into a source address of the second sub-lookup table where the read second predistortion parameter is located, where the processing unit performs the reading operation and the writing operation of the same sub-lookup table asynchronously and in different clock cycles, and according to the predistortion parameter 
The first sub-lookup table and the second sub-lookup table are alternately used for the line numbers in the table.
2. The predistortion parameter updating apparatus according to claim 1, wherein said processing unit is spaced an odd number of clock cycles between read and write operations for predistortion parameters of the same row in the same sub-lookup table.
3. The predistortion parameter updating apparatus according to claim 1, wherein,
when the processing unit reads a row of first predistortion parameters from the first sub-lookup table, writing the acquired row of second updated predistortion parameters into the second sub-lookup table;
and when the processing unit reads a row of second predistortion parameters from the first sub-lookup table, writing the acquired row of first updated predistortion parameters into the first sub-lookup table.
4. The predistortion parameter updating apparatus according to claim 1, wherein,
when the processing unit reads a row of first predistortion parameters from the first sub-lookup table, a row of second predistortion parameters from the second sub-lookup table,
when the processing unit writes the acquired first updated predistortion parameters of one row into the first sub-lookup table, the processing unit writes the acquired second updated predistortion parameters of one row into the second sub-lookup table.
5. The predistortion parameter updating apparatus according to claim 1, wherein said memory cell is a single-port random access memory.
6. A predistortion system, characterized in that it comprises predistortion parameter updating means, predistortion compensation means and a power amplifier according to any one of claims 1 to 5,
the processing unit is configured to calculate a predistortion parameter to be updated to obtain an updated predistortion parameter, and includes: the processing unit is used for processing according to
Calculating to obtain updated predistortion parameters>
Wherein->
For inputting signals +.>
For input signal +.>
And feedback signal->
Error between, said feedback signal +.>
For the sampling signal coupled back via the power amplifier +.>
For the predistortion parameters to be updated, +.>
In order to adjust the parameters of the device,
the predistortion compensation means is for updating predistortion parameters provided by the predistortion parameter updating means
For the input signal->
The predistortion process is performed to obtain a compensated output signal,
the power amplifier is also used for amplifying the power of the compensation output signal to reach the required transmitting power.
7. A predistortion parameter updating method is used for updating predistortion parameters stored in at least two sub-lookup tables and is characterized in that all the sub-lookup tables are used for jointly forming a mother lookup table, each row of predistortion parameters in each sub-lookup table corresponds to one row of predistortion parameters in the mother lookup table, the at least two sub-lookup tables comprise a first sub-lookup table and a second sub-lookup table, the first sub-lookup table stores a first predistortion parameter, the second sub-lookup table stores a second predistortion parameter, and the first predistortion parameter is that 
The second predistortion parameter is +.>
Said->
Corresponding predistortion parameters->
Even-numbered line number predistortion parameters in (a)Said->
Corresponding predistortion parameters->
The odd number of the predistortion parameters in (a), wherein m is the line number,/a->
n is the iteration number, < >>
The method comprises the steps of carrying out a first treatment on the surface of the 2j is even line number, (2j+1) is odd line number, +.>
The method comprises the following steps:
outputting a read enabling signal and a read address signal according to the line number of the predistortion parameter to be updated in the mother lookup table;
reading predistortion parameters from the corresponding sub-lookup tables according to the read enable signal and the read address signal, including: reading a first predistortion parameter from a first sub-lookup table where the predistortion parameter to be updated is located according to the reading enabling signal and the reading address signal, and reading a second predistortion parameter from a second sub-lookup table where the predistortion parameter to be updated is located according to the reading enabling signal and the reading address signal;
calculating according to the read predistortion parameters to obtain updated predistortion parameters, including: calculating according to the read first predistortion parameters to obtain first updated predistortion parameters, and calculating according to the read second predistortion parameters to obtain second updated predistortion parameters;
Outputting a write enabling signal and a write address signal according to the read predistortion parameters in the row number of the mother lookup table;
writing the updated predistortion parameters into the original addresses of the read predistortion parameters in the corresponding sub-lookup tables according to the write enabling signals and the write address signals, wherein the method comprises the following steps: writing the first updated predistortion parameters into the original address of a first sub-lookup table where the first predistortion parameters are located, and writing the second updated predistortion parameters into the original address of a second sub-lookup table where the second predistortion parameters are located;
wherein the read and write operations to the same sub-lookup table are performed asynchronously and in different clock cycles, and in accordance with the predistortion parameters
The first sub-lookup table and the second sub-lookup table are alternately used for the line numbers in the table.
8. The predistortion parameter updating method according to claim 7, characterized in that said method further comprises: the read and write operations for predistortion parameters for the same row in the same sub-lookup table are separated by an odd number of clock cycles.
9. The predistortion parameter updating method according to claim 8, characterized in that said method further comprises:
When a row of first predistortion parameters are read from the first sub-lookup table, writing the acquired row of second updated predistortion parameters into a second sub-lookup table;
and when a row of second predistortion parameters are read from the second sub-lookup table, writing the acquired row of first updated predistortion parameters into the first sub-lookup table.
10. The predistortion parameter updating method according to claim 7, characterized in that said method further comprises;
reading a row of first predistortion parameters from the first sub-lookup table, reading a row of second predistortion parameters from the second sub-lookup table,
when writing the acquired first updated predistortion parameters of one row into the first sub-lookup table, writing the acquired second updated predistortion parameters of one row into the second sub-lookup table.
11. A predistortion parameter updating apparatus, comprising a processor and a memory, wherein the memory is adapted to store a set of program code, and the processor is adapted to invoke the program code stored in the memory to perform the steps of any of claims 7-10.
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