CN113794532B - Block coding method and device - Google Patents
Block coding method and device Download PDFInfo
- Publication number
- CN113794532B CN113794532B CN202110919702.XA CN202110919702A CN113794532B CN 113794532 B CN113794532 B CN 113794532B CN 202110919702 A CN202110919702 A CN 202110919702A CN 113794532 B CN113794532 B CN 113794532B
- Authority
- CN
- China
- Prior art keywords
- vectors
- modulation
- sequence
- preset
- coded
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0057—Block codes
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0041—Arrangements at the transmitter end
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0071—Use of interleaving
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Error Detection And Correction (AREA)
Abstract
The application provides a packet coding method and a device, which relate to the technical field of digital communication, and the method comprises the following steps: acquiring a bit sequence to be coded, and repeating the bit sequence to be coded for L times by taking the length N of the bit sequence to be coded as a period to obtain L bit sequences, wherein L and N are positive integers; inputting each bit sequence into a corresponding interleaver in preset L interleavers for interleaving; sequentially taking out K multiplied by J bits from the interleaved sequence, constructing K J-dimensional first vectors, and respectively carrying out linear block code coding on each first vector to output K M-dimensional second vectors, wherein K, J and M are positive integers, and KJ is less than or equal to LN; and carrying out differential processing and modulation on the K second vectors in sequence according to a preset modulation mechanism, and sending modulation signals obtained after modulation to a receiving end. The method solves the problem of initial phase ambiguity during the demodulation of the communication system, and has stronger burst error resistance.
Description
Technical Field
The present application relates to the field of digital communication technologies, and in particular, to a packet coding method and apparatus.
Background
In the field of communication technology, there are various channel coding techniques, such as Turbo code, Low Density Parity Check (LDPC) code, and repeat-accumulate (RA) code, which can improve the reliability of information transmission. The RA code can adopt a Turbo code-like coding structure and can also adopt an LDPC code iterative decoding algorithm, so that the RA code has the advantages of simple coding implementation and low decoding complexity.
In the related technology, the encoding step of the RA code mainly comprises repetition, interleaving, combination and accumulation with a code rate of 1/q. The applicant finds that, since the channel is often interfered by noise in practical applications, the channel coding technique in the related art may not obtain all correct information sequences on the receiving side, and the burst error resistance is weak. In addition, when the communication system performs coherent demodulation, two possible phases, namely, a 0 phase and a pi phase, exist in the carrier signal extracted from the received signal, and the demodulation result is in phase or in phase opposition to the baseband signal of the originating terminal, which easily causes the initial phase ambiguity of the system.
Disclosure of Invention
The present application is directed to solving, at least to some extent, one of the technical problems in the related art.
Therefore, a first objective of the present application is to provide a block coding method, in which a whole data block to be coded is taken as a cycle to perform repeated processing, each sequence output by the repeated processing is interleaved respectively, so that the interleaving depth is smaller, the diversification of information bits is realized to a greater extent, the sequences output by the interleaved processing are divided into a plurality of groups, and the groups are independently coded to obtain a plurality of short code blocks which can be independently modulated and transmitted, so that the burst error resistance is higher, and when a communication system is in coherent demodulation, each short code block is differentially processed according to a modulation mode, so that the initial phase ambiguity problem can be overcome.
A second object of the present application is to propose an apparatus for block coding.
A third object of the present application is to propose a non-transitory computer-readable storage medium.
To achieve the above object, a first aspect of the present application provides a packet coding method, including the following steps:
acquiring a bit sequence to be coded, and repeating the bit sequence to be coded for L times by taking the length N of the bit sequence to be coded as a period to obtain L bit sequences, wherein L and N are positive integers;
inputting each bit sequence into a corresponding interleaver in preset L interleavers for interleaving;
sequentially taking out K multiplied by J bits from the interleaved sequence, constructing K J-dimensional first vectors, and respectively carrying out linear block code coding on each first vector to output K M-dimensional second vectors, wherein K, J and M are positive integers, and KJ is less than or equal to LN;
and carrying out differential processing and modulation on the K second vectors in sequence according to a preset modulation mechanism, and sending a modulation signal obtained after modulation to a receiving end.
Optionally, in an embodiment of the present application, in the block coding method, the parameter of the interleaver
Optionally, in an embodiment of the present application, the block coding method performs linear block code coding on each first vector through the following formula:
r k ＝G k c k
wherein r is k Is any one of the K second vectors, c k Is any one of K first vectors, G is a positive integer less than or equal to K k Is a generator matrix of linear block codes corresponding to the kth encoding, G k Is a sparse matrix of dimension M × J.
Optionally, in an embodiment of the present application, in the block coding method, the sequentially performing differential processing and modulation on the K second vectors according to a preset modulation scheme includes:
if the preset modulation mechanism is differential modulation, sequentially carrying out differential modulation on the K second vectors;
if the preset modulation mechanism is non-differential modulation, the K second vectors are subjected to differential encoding in sequence, and after the K second vectors are converted into K relative code vectors, the K relative code vectors are subjected to non-differential modulation in sequence.
Optionally, in an embodiment of the present application, according to the block coding method, the K second vectors are differentially coded by the following formula:
wherein the content of the first and second substances,
is any bit of the second vector,
is a relative code vector and
corresponding bit, M-0, 1 … M-1, initial value
Is a preset arbitrary value.
To achieve the above object, a second aspect of the present application proposes that the present invention is based on a packet coding apparatus, including the following modules:
a repeating module, configured to obtain a bit sequence to be encoded, and repeat the bit sequence to be encoded L times with a length N of the bit sequence to be encoded as a period to obtain L bit sequences, where L and N are positive integers;
the interleaving module is used for inputting each bit sequence to a corresponding interleaver in the preset L interleavers for interleaving;
the block coding module is used for sequentially taking out K multiplied by J bits from the interleaved sequence, constructing K J-dimensional first vectors, and respectively carrying out linear block code coding on each first vector to output K M-dimensional second vectors, wherein K, J and M are positive integers, and KJ is less than or equal to LN;
and the modulation module is used for sequentially carrying out differential processing and modulation on the K second vectors according to a preset modulation mechanism and sending modulation signals obtained after modulation to a receiving end.
Optionally, in an embodiment of the present application, in the block coding apparatus, the parameter of the interleaver
Optionally, in an embodiment of the present application, in the block coding apparatus, the block coding module is specifically configured to perform linear block code coding on each first vector according to the following formula:
r k ＝G k c k
wherein r is k Is any one of K of said second vectors, c k Is any one of K first vectors, K is a positive integer less than or equal to K, G k Is a generator matrix of linear block codes corresponding to the kth encoding, G k Is a sparse matrix of dimension M × J.
Optionally, in an embodiment of the present application, the block coding apparatus performs differential processing on a signal through a modulation module, where the modulation module is specifically configured to:
if the preset modulation mechanism is differential modulation, sequentially carrying out differential modulation on the K second vectors;
if the preset modulation mechanism is non-differential modulation, the K second vectors are subjected to differential encoding in sequence, and after the K second vectors are converted into K relative code vectors, the K relative code vectors are subjected to non-differential modulation in sequence.
The technical scheme provided by the embodiment of the application at least has the following beneficial effects: this application is earlier with the whole data block of treating the code to carry out the reprocessing as the cycle, interweave respectively to each sequence of reprocessing output, make the depth of interweaving littleer, furthest's realization the diversification of information bit, divide into a plurality of groups to the sequence of reprocessing output again, independent coding between each group, obtain a plurality of short code blocks that can independently modulate and send, thereby possess stronger anti burst error ability, and when communication system coherent demodulation, carry out difference processing to every short code block according to the modulation mode, can overcome the initial phase ambiguity problem.
In order to implement the foregoing embodiments, the third aspect of the present application further provides a non-transitory computer-readable storage medium, on which a computer program is stored, and the computer program, when executed by a processor, implements the block coding method and apparatus in the foregoing embodiments.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
The foregoing and/or additional aspects and advantages of the present application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
fig. 1 is a flowchart of a block coding method according to an embodiment of the present application;
fig. 2 is a block diagram of a digital communication system according to an embodiment of the present application;
fig. 3 is a schematic structural diagram of a block coding apparatus according to an embodiment of the present application.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are illustrative and intended to be illustrative of the invention and are not to be construed as limiting the invention.
A method and apparatus for block coding according to an embodiment of the present invention will be described with reference to the accompanying drawings.
Fig. 1 is a flowchart of a block coding method according to an embodiment of the present application, as shown in fig. 1, the method includes the following steps:
step 101, obtaining a bit sequence to be coded, and repeating the bit sequence to be coded L times with the length N of the bit sequence to be coded as a period to obtain L bit sequences, where L and N are positive integers.
In an embodiment of the present application, if the code block length of the data block to be coded is N, the bit sequence to be coded is b 0 ,b 1 …b N-1 Repeating the bit sequence to be coded L times with the length N of the bit sequence to be coded as a period to obtain L sequences, and further forming a sequence (b) 0 ,b 1 …b N-1 ,b 0 ,b 1 …b N-1 ……b 0 ,b 1 …b N-1 ). Wherein, L and N can be any preset positive integer.
And 102, inputting each bit sequence into a corresponding interleaver in the preset L interleavers for interleaving.
In one embodiment of the present application, the parameters of the interleaver are preset
I.e. parameters of the interleaver 1
Parameters of the interleaver 2
By analogy, L interleavers corresponding to the repeated sequence number are arranged. Further, the L bit sequences are interleaved by corresponding interleavers of the L interleavers, and the order of elements in each sequence is disturbed, so as to obtain an interleaved information sequence. For example, in a first sequence (b) 0 ,b 1 …b N-1 ) In other words, the sequence input to the interleaver 1 for interleaving is
It should be noted that the interleaving order of the L interleavers may be set according to actual needs, for example, the interleaving order of the L interleavers may be set to be different from each other, and the interleaving order of some of the interleavers may also be set to be the same. Further, after each sequence is input to a corresponding interleaver for L interleaving, a sequence with the length of L multiplied by N is output:
103, sequentially taking out K multiplied by J bits from the interleaved sequence, constructing K J-dimensional first vectors, and respectively performing linear block code coding on each first vector to output K M-dimensional second vectors, wherein K, J and M are positive integers, and KJ is less than or equal to LN;
in an embodiment of the present application, K times J bits are sequentially extracted from a first bit in an interleaved sequence, and redundant LN-KJ bits after the extraction are discarded, so that K groups of sequences of J bits each are obtained, and K J-dimensional first vectors are constructed according to the extracted grouped bits, where the first vector may be represented as:
for example, a first vector is constructed based on the first set of J bits,
wherein the content of the first and second substances,
is J bits in the first group.
Further, each first vector is subjected to linear block code encoding respectively, and K second vectors with M dimensions are output, wherein the second vectors can be expressed as
For example, the first and second vectors may be expressed as
r 1 Is to c 1 Obtained after linear block code encoding, r after block encoding 1 Is converted from the J dimension to the M dimension.
As one of the possible implementations, each first vector may be encoded by a linear block code according to the following formula:
r k ＝G k c k
wherein r is k Is any one of the K second vectors, c k Is any one of K first vectors, K is a positive integer less than or equal to K, namely, each first vector is sequentially subjected to block coding through the formula to obtain a corresponding second vector, wherein G k Is the generating matrix of the linear block code corresponding to the kth encoding, i.e. the matrix of the current linear block code is generated when the kth first vector is encoded, G k An M × J dimensional sparse matrix is shown, for example, in the following matrix, the number of elements with a value of 0 in the matrix is much larger than the number of elements other than 0, and the elements in the matrix are linear block codes during encoding.
From the matrix, after the first vector is encoded by linear block code, the dimension of the vector is converted from J dimension to M dimension.
In addition, G is k May be set according to coding requirements, for example, M and J may be set to M greater than J, equal to J, or less than J, so that the dimension of the encoded second vector may be adjusted as required.
And step 104, sequentially carrying out differential processing and modulation on the K second vectors according to a preset modulation mechanism, and sending modulation signals obtained after modulation to a receiving end.
In one embodiment of the present application, if the modulation mechanism of the preset modulator employs differential modulation, the K second vectors r are subjected to differential modulation k Directly modulating one by one; if the preset modulation mechanism adopts non-differential modulation, firstly K vectors r are subjected to differential modulation k Differentially encoding one by one to convert into K relative codevectors
Wherein
Where rmk is any bit of the second vector, amk is a bit corresponding to rmk of the corresponding code vector, M is 0,1 … M-1, and the initial value is
Is a preset arbitrary value, and then the relative codes a are paired one by one k Non-differential modulation is performed. It should be noted that, in the present application, a plurality of short code blocks capable of being modulated and transmitted independently are obtained by independently encoding between groups, each modulated signal after modulation can be transmitted as a burst unit, and even if some burst units have strong interference in the channel transmission process, the burst units receive the modulated signalOn the other hand, all correct information sequences can be obtained by jointly demodulating and decoding the K modulated signals.
To sum up, the block coding method according to the embodiment of the present application performs repeated processing with the whole data block to be coded as a period, interleaves each sequence output by the repeated processing, so that the interleaving depth is smaller, and the diversification of information bits is realized to a greater extent.
In order to more clearly illustrate the specific implementation process of the block coding method of the present application, the following detailed description is made with reference to fig. 2 in a specific embodiment:
as shown in fig. 2, the digital communication system proposed by the present application includes an encoder and a modulator on the transmitting side, and a demodulator and a decoder on the receiving side.
The encoder on the transmitting side adopts the block coding method described in the above embodiments, and inputs an information sequence of N bits each time, and outputs K M-dimensional vectors r if the modulator is differential modulation k If the modulator is not differential modulation, K M + 1-dimensional relative code vectors a are output k . The modulator may convert the sequence of K vectors into K vectors of modulated signals, which are then transmitted over the channel. Since the channel is typically subject to noise interference, on the receiving side, the received signal is used by a demodulator and decoder to estimate the transmitted information sequence.
In one non-limiting example of the present application, the parameters N-4800, L-14, J-128, M-32, K-512 are selected.
First, a bit sequence to be coded (b) having a code block length N of 4800 is input 0 ,b 1 …b N-1 ) Then, a block coding process for the bit sequence to be coded includes the following steps:
step 1, repeating L ═ 14 times for a bit sequence to be coded with the whole data block as a period: (b 0 ,b 1 …b N-1 ,b 0 ,b 1 …b N-1 ,…b 0 ,b 1 …b N-1 )。
step 2, the 14 sequences repeatedly output in the step 1 are respectively subjected to parameters of
Interleaver of l Is a randomly generated N integer which is not repeated between 0 and N-1, and the information sequence after interleaving is as follows:
the interleaving order of the 14 interleavers may be set according to actual needs, for example, the interleaving order of the L interleavers may be set to be different from each other, and after 14 times of interleaving, a sequence with a length of 67200 (14 × 4800) is output:
step 3, in this embodiment, K groups of J bits each are sequentially extracted from the interleaved sequence of step 2, that is, 512 groups of 128 bits each are extracted, KJ, that is, 65536 bits are extracted, the last redundant LN-KJ, that is, 1664 bits are discarded, and K J-dimensional, that is, 512 128-dimensional information bit vectors are constructed
For each information bit vector c separately k And (J, M) linear block code encoding is carried out, in the embodiment, the linear block code adopts a randomly generated sparse matrix, and the number of elements with the numerical value of 0 in the matrix is far more than the number of elements with the numerical value of non-0. Generating matrix G for e.g. kth linear block code k Each row and each column has a small amount of elements 1 and the rest 0.
The kth encoded input is a vector of information bits c k The output is an M-dimensional vector,
r k ＝G k ·c k
the K-time encoding outputs a total of K M-dimensional vectors, 512-dimensional vectors, and 16384 bits.
In addition, G is k May be set according to coding requirements, for example, M and J may be set to M greater than J, equal to J, or less than J, so that the dimension of the encoded second vector may be adjusted as required.
And 4, carrying out difference processing. Modulation methods that may be employed in digital communication systems include, but are not limited to, differential coherent binary phase shift keying (DBPSK), which is a type of differential modulation, and Minimum Shift Keying (MSK), which is a type of non-differential modulation. If DBPSK modulation is adopted, K vectors r which are output by encoding in step 3 are processed, namely 512 vectors r k Directly modulating one by one; if MSK modulation is used, first the K vectors r are aligned k Differentially encoding one by one to convert into K relative codevectors
Wherein
Initial value
Can be set arbitrarily, and then the relative codes a are paired one by one k MSK modulation is performed.
In the present application, no matter which modulation method is adopted, the phase of the modulation signal does not directly represent the baseband signal through the self-carried differential characteristic or the addition of differential coding, and the relative phase of the front and rear code elements determines the information symbol, so that the correct original data can be obtained even if the initial phase ambiguity exists as long as no error exists in transmission.
Simulation verification shows that the encoding method can overcome phase ambiguity, although the encoding output is a plurality of short code blocks, the association length between each bit in the short codes is longer, through iterative decoding, the association between each bit in all the code blocks can be fully utilized to improve the decoding accuracy, and the characteristics of a burst channel are fully utilized. The system demodulation threshold can reach 1.4-1.5 dB, and is superior to a common channel coding scheme.
In order to implement the above embodiments, the present application also proposes an apparatus for block coding,
fig. 3 is a schematic structural diagram of a block coding apparatus according to an embodiment of the present disclosure.
As shown in fig. 3, the block coding apparatus includes a repetition module 100, an interleaving module 200, a block coding module 300, and a modulation module 400.
The repetition module 100 is configured to obtain a bit sequence to be encoded, and repeat the bit sequence to be encoded L times with a length N of the bit sequence to be encoded as a period to obtain L bit sequences, where L and N are positive integers;
an interleaving module 200, configured to input each bit sequence to a corresponding interleaver of the preset L interleavers for interleaving;
a block coding module 300, configured to sequentially extract K times J bits from the interleaved sequence, construct K J-dimensional first vectors, and perform linear block code coding on each of the first vectors to output K M-dimensional second vectors, where K, J and M are positive integers, and KJ is less than or equal to LN;
and the modulation module 400 is configured to perform difference processing and modulation on the K second vectors sequentially according to a preset modulation mechanism, and send a modulated signal obtained after modulation to a receiving end.
Optionally, in an embodiment of the present application, in the block coding apparatus, the parameter of the interleaver
The interleaving order of the L interleavers may be set according to actual needs, for example, the interleaving order of the L interleavers may be set to be different from each other, or the interleaving order of a plurality of interleavers may be set to be the same.
Optionally, in an embodiment of the present application, in the block coding apparatus, the block coding module is specifically configured to perform linear block code coding on each first vector according to the following formula:
r k ＝G k c k
wherein r is k Is any one of K second vectors, c k Is any one of K first vectors, K is a positive integer less than or equal to K, G k Is a generator matrix of linear block codes corresponding to the kth code, G k Is a sparse matrix of dimension M × J.
To sum up, the block coding apparatus according to the embodiment of the present application performs repeated processing with the whole data block to be coded as a cycle, and interleaves each sequence output by the repeated processing, so that the interleaving depth is smaller, the diversification of information bits is realized to a greater extent, and then the sequences output by the interleaved processing are divided into a plurality of groups, and the groups are independently coded to obtain a plurality of short code blocks that can be independently modulated and transmitted, thereby having a stronger burst error resistance.
In order to implement the above embodiments, the present invention further provides a non-transitory computer-readable storage medium, on which a computer program is stored, the computer program, when being executed by a processor, implementing a packet coding method according to an embodiment of the first aspect of the present application
In the description herein, reference to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or to implicitly indicate the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present application, "plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing steps of a custom logic function or process, and alternate implementations are included within the scope of the preferred embodiment of the present application in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the present application.
The logic and/or steps represented in the flowcharts or otherwise described herein, e.g., an ordered listing of executable instructions that can be considered to implement logical functions, can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. For the purposes of this description, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium would include the following: an electrical connection (electronic device) having one or more wires, a portable computer diskette (magnetic device), a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium could even be paper or another suitable medium upon which the program is printed, as the program can be electronically captured, via for instance optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner if necessary, and then stored in a computer memory.
It should be understood that portions of the present application may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the various steps or methods may be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. If implemented in hardware, as in another embodiment, any one or combination of the following techniques, which are known in the art, may be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.
It will be understood by those skilled in the art that all or part of the steps carried by the method for implementing the above embodiments may be implemented by hardware related to instructions of a program, which may be stored in a computer readable storage medium, and when the program is executed, the program includes one or a combination of the steps of the method embodiments.
In addition, functional units in the embodiments of the present application may be integrated into one processing module, or each unit may exist alone physically, or two or more units are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. The integrated module, if implemented in the form of a software functional module and sold or used as a stand-alone product, may also be stored in a computer readable storage medium.
The storage medium mentioned above may be a read-only memory, a magnetic or optical disk, etc. Although embodiments of the present application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present application, and that variations, modifications, substitutions and alterations may be made to the above embodiments by those of ordinary skill in the art within the scope of the present application.
Claims (10)
1. A block coding method, comprising the steps of:
acquiring a bit sequence to be coded, and repeating the bit sequence to be coded for L times by taking the length N of the bit sequence to be coded as a period to obtain L bit sequences, wherein L and N are positive integers;
inputting each bit sequence into a corresponding interleaver in preset L interleavers for interleaving;
sequentially taking out K multiplied by J bits from the interleaved sequence, constructing K J-dimensional first vectors, and respectively carrying out linear block code coding on each first vector to output K M-dimensional second vectors, wherein K, J and M are positive integers, and KJ is less than or equal to LN;
and carrying out differential processing and modulation on the K second vectors in sequence according to a preset modulation mechanism, and sending a modulation signal obtained after modulation to a receiving end.
2. The block coding method according to claim 1, wherein the interleaver parameter
3. A block coding method according to claim 1 or 2, characterized in that each of said first vectors is linear block code coded by the following formula:
r k ＝G k c k
wherein r is k Is any one of the K second vectors, c k Is any one of K first vectors, K is a positive integer less than or equal to K, G k Is a generator matrix of linear block codes corresponding to the kth encoding, G k Is a sparse matrix of dimension M × J.
4. The block coding method according to claim 1, wherein the sequentially performing differential processing and modulation on the K second vectors according to a preset modulation scheme comprises:
if the preset modulation mechanism is differential modulation, sequentially carrying out differential modulation on the K second vectors;
if the preset modulation mechanism is non-differential modulation, the K second vectors are subjected to differential encoding in sequence, and after the K second vectors are converted into K relative code vectors, the K relative code vectors are subjected to non-differential modulation in sequence.
5. The block coding method according to claim 4, wherein the K second vectors are differentially encoded by the following formula:
wherein the content of the first and second substances,
is any bit of the second vector,
is a relative code vector and
corresponding bit, M-0, 1 … M-1, initial value
Is a preset arbitrary value.
6. A packet coding apparatus, comprising:
the device comprises a repeating module, a coding module and a decoding module, wherein the repeating module is used for acquiring a bit sequence to be coded, repeating the bit sequence to be coded for L times by taking the length N of the bit sequence to be coded as a period to obtain L bit sequences, and L and N are positive integers;
the interleaving module is used for inputting each bit sequence into a corresponding interleaver in the preset L interleavers for interleaving;
the block coding module is used for sequentially taking out K multiplied by J bits from the interleaved sequence, constructing K J-dimensional first vectors, and respectively carrying out linear block code coding on each first vector to output K M-dimensional second vectors, wherein K, J and M are positive integers, and KJ is less than or equal to LN;
and the modulation module is used for sequentially carrying out differential processing and modulation on the K second vectors according to a preset modulation mechanism and transmitting a modulated signal obtained after modulation to a receiving end.
7. The block coding device according to claim 6, wherein the interleaver parameter
8. The block coding device according to claim 6 or 7, wherein the block coding module is specifically configured to perform linear block code coding on each of the first vectors by using the following formula:
r k ＝G k c k
wherein r is k Is any one of the K second vectors, c k Is the first vector, G k Is a generator matrix of linear block codes corresponding to the kth encoding, G k Is a sparse matrix of dimension M × J.
9. The block coding device according to claim 6, wherein the modulation module is specifically configured to:
if the preset modulation mechanism is differential modulation, sequentially carrying out differential modulation on the K second vectors;
if the preset modulation mechanism is non-differential modulation, the K second vectors are subjected to differential encoding in sequence, and after the K second vectors are converted into K relative code vectors, the K relative code vectors are subjected to non-differential modulation in sequence.
10. A non-transitory computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, implements the block coding method according to any one of claims 1 to 5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110919702.XA CN113794532B (en) | 2021-08-11 | 2021-08-11 | Block coding method and device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110919702.XA CN113794532B (en) | 2021-08-11 | 2021-08-11 | Block coding method and device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113794532A CN113794532A (en) | 2021-12-14 |
| CN113794532B true CN113794532B (en) | 2022-09-16 |
Family
ID=78875986
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110919702.XA Active CN113794532B (en) | 2021-08-11 | 2021-08-11 | Block coding method and device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113794532B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101841339A (en) * | 2009-03-17 | 2010-09-22 | 大唐移动通信设备有限公司 | Encoder, decoder and encoding and decoding methods |
| CN102025451A (en) * | 2010-12-08 | 2011-04-20 | 北京理工大学 | Turbo code differential frequency hopping method for cooperative communication |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102075487B (en) * | 2009-11-25 | 2013-02-27 | 清华大学 | Multidimensional constellation mapping based coding and modulating method, demodulating and decoding method and system |
| CN103718490A (en) * | 2013-04-26 | 2014-04-09 | 华为技术有限公司 | De-interleaver method and communication system |
| CN108400838B (en) * | 2017-02-06 | 2021-05-18 | 华为技术有限公司 | Data processing method and device |
| CN106972865B (en) * | 2017-03-20 | 2020-05-08 | 中山大学 | Recursive packet Markov superposition coding method |
| CN108900463B (en) * | 2018-08-27 | 2021-02-19 | 南京邮电大学 | APSK constellation mapping-based coding modulation system |
| CN110445582B (en) * | 2019-08-12 | 2020-10-23 | 广东工业大学 | Code interleaving method, system, device and computer readable storage medium |
-
2021
- 2021-08-11 CN CN202110919702.XA patent/CN113794532B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101841339A (en) * | 2009-03-17 | 2010-09-22 | 大唐移动通信设备有限公司 | Encoder, decoder and encoding and decoding methods |
| CN102025451A (en) * | 2010-12-08 | 2011-04-20 | 北京理工大学 | Turbo code differential frequency hopping method for cooperative communication |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113794532A (en) | 2021-12-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101039119B (en) | Encoding and decoding methods and systems | |
| CN106888026B (en) | Segmented polarization code coding and decoding method and system based on LSC-CRC (least significant likelihood-Cyclic redundancy check) decoding | |
| CN101842992B (en) | Transmission device | |
| RU2450442C2 (en) | Method and apparatus for channel encoding and decoding in communication system using low-density parity-check codes | |
| CN103888148A (en) | LDPC hard decision decoding method for dynamic threshold value bit-flipping | |
| WO2008034289A1 (en) | Bit mapping scheme for an ldpc coded 32apsk system | |
| WO2014017102A1 (en) | Transmission method, reception method, transmitter, and receiver | |
| KR20090086893A (en) | Apparatus and method for channel encoding and decoding in communication system using low-density parity-check codes | |
| CN101636914A (en) | Method and apparatus for encoding and decoding data | |
| KR20120079922A (en) | Method and apparatus for channel encoding and decoding in a communication system with low density parity-check codes | |
| CA2521041C (en) | Methods and apparatus for interleaving in a block-coherent communication system | |
| CN106936541B (en) | RS coding and byte interleaving method and system | |
| CN113794532B (en) | Block coding method and device | |
| CN109412752B (en) | Non-coherent detection receiver, system and method for polarization code | |
| CN114884784B (en) | Constellation point mapping relation generation method, signal transmission method and related device | |
| CN111726123B (en) | Rate-free multi-user coding method suitable for interweaving multi-address access system | |
| Boiko et al. | Features of code redundancy formation in information transmission channels | |
| US8196000B2 (en) | Methods and apparatus for interleaving in a block-coherent communication system | |
| Chen et al. | Multiplicative repetition‐based spinal codes with low computational complexity | |
| KR102535853B1 (en) | Apparatus and method for low-complexity ldpc decoding for ofdm index modulation | |
| EP1901436A2 (en) | Bit mapping scheme for an LDPC coded 16APSK system | |
| CN110190925B (en) | Data processing method and device | |
| CN117938308A (en) | Optical transmission method, device and system based on polarization code embedded irregular QC-LDPC cascade TCM (quasi-cyclic Low Density parity check) encoding and decoding | |
| Shi et al. | A novel spinal codes based on chaotic Kent mapping | |
| Torrieri | Modulations and Channel Codes |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |