CN113776766A - Voltage drop test device and method for IR46 electric meter calibrating device - Google Patents
Voltage drop test device and method for IR46 electric meter calibrating device Download PDFInfo
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Abstract
The invention discloses a voltage drop test device and a method for an IR46 electric meter calibrating device, wherein the device comprises a voltage sampling circuit 1, a voltage drop circuit, a voltage sampling circuit 2, a zero-crossing detection circuit, a power supply circuit, a TCP/IP network communication module and a main controller, and the method finishes the detection of input and output voltage signals by controlling the voltage sampling circuits 1 and 2 through the main controller; controlling the voltage drop circuit to complete the simulation of the voltage drop event in the R46 standard; controlling a zero-crossing detection circuit to complete the detection of the frequency of the input voltage signal; controlling the TCP/IP network communication module to complete real-time communication with an upper computer; a voltage drop test of the IR46 meter was achieved. The invention has a plurality of simulation scenes, and the automatic test result is efficient, rapid and accurate, and manual test is not needed, thereby saving the labor and time cost.
Description
Technical Field
The invention relates to the technical field of electric power, in particular to a voltage drop test device and method for an IR46 electric meter calibrating device.
Background
With the continuous progress of society and the vigorous development of national economy, electric energy plays an increasingly important role in the life of people. The quality of the electric energy directly influences the overall benefit of national economy. In recent years, with the increasing nonlinear and impact loads, the power quality problem is worsened, and some power quality problems which are not paid attention to before are gradually developed, such as voltage sag, short-time interruption and the like.
The recent international proposal of the R46 electric energy meter gives clear definition and standard for voltage sag and interruption, so that the verification device of the R46 electric energy meter needs to artificially simulate voltage sag (sag and interruption) events to verify whether the R46 electric energy meter is immune to the voltage sag.
The traditional voltage drop device influences the distortion degree of a voltage signal, has long switching time and cannot meet the R46 standard.
Disclosure of Invention
In order to overcome the defects or shortcomings in the prior art, the invention provides a voltage drop test device and method for an IR46 electric meter verification device, which are used for verifying an IR46 electric meter by simulating a voltage drop event in an R46 standard, and can simulate other types of drop events according to actual needs, so that automatic test is realized, input voltage and output voltage waveforms are monitored in real time, time and labor cost are saved, and the test result is efficient and accurate.
In order to achieve the purpose, the invention provides a voltage drop test device for an IR46 electric meter calibrating device, which comprises a voltage sampling circuit 1, a voltage drop circuit, a voltage sampling circuit 2, a zero-crossing detection circuit, a power supply circuit, a TCP/IP network communication module and a main controller, wherein:
a voltage sampling circuit 1 for detecting a waveform signal of an input voltage in real time;
the voltage sag circuit is used for simulating voltage sag and interruption events in the R46 standard, including a voltage sag test a, which is reduced to 30% and lasts for 0.5 period; testing voltage sag, namely b, reducing the voltage sag to 60 percent for 1 period; voltage sag test c, down to 60% for 25 cycles (50Hz) or 30 cycles (60 Hz); the voltage was interrupted and tested, reduced to 0%, for 250 cycles (50Hz) or 300 cycles (60 Hz); the voltage reduction is repeated 10 times at intervals of at least 10 seconds;
the voltage sampling circuit 2 is used for monitoring the waveform signal of the output voltage of the voltage drop circuit in real time and judging whether the waveform signal meets the R46 standard and the actual requirement;
the zero-crossing detection circuit is used for quickly and accurately detecting the zero crossing point of the input voltage;
the power circuit is used for providing electric energy for the whole device, and the influence of the voltage drop device on an input voltage signal is reduced by adopting a linear multi-path isolation power supply, so that the control complexity is reduced;
the TCP/IP network communication module is connected with an external PC, receives a control command sent by the upper computer, sends the control command to the main controller, and sends a waveform signal monitored by the voltage sampling circuit 2 to the upper computer; (ii) a
The main controller controls the voltage dropping circuit and the voltage sampling circuits 1 and 2 to work, monitors a voltage zero-crossing signal, receives a control command from an external PC (personal computer) and uploads waveform signals of input and output voltages to the PC;
the input end of the voltage sampling circuit 1 is connected with an external power source and a zero-crossing detection circuit, and the output end of the voltage sampling circuit is connected with a voltage drop circuit; the input end of the voltage sampling circuit 2 is connected with the voltage drop circuit, and the output end of the voltage sampling circuit is connected with an external IR46 electric meter; the main controller is respectively connected with the voltage sampling circuits 1 and 2, the voltage drop circuit, the zero-crossing detection circuit, the power supply circuit and the TCP/IP network communication module.
A voltage droop circuit comprising double pole double throw relays S1, S2 and S3; single pole double throw relays S4, S5, N-MOSFETs Q1, Q2, Q3, Q4, Q5 and Q6; resistors R1, R2, R3, R101, R102, R103, R201, R202, and R203; capacitors C1, C2, C3, C201, C202 and C203 and transformer T1; according to the standard of R46, the transformer T1 has two taps, which are respectively positioned at 30% and 60%, and different transformers can be configured according to actual requirements.
A channel formed by double-pole double-throw relays S1 and S2 is a main loop; a channel consisting of a double-pole double-throw relay S3, an N-MOSFET Q1 and a Q2 is a secondary loop 1; a channel consisting of the single-pole double-throw relay S4, the N-MOSFET Q3 and the Q4 is a secondary loop 2; the channel consisting of the single-pole double-throw relay S5, the N-MOSFETs Q5 and Q6 is the secondary loop 3. The main loop adopts a mode that double-pole double-throw relays S1 and S2 are connected in parallel, so that the impedance of the main loop is reduced; the auxiliary loops 1, 2 and 3, N-MOSFET adopt a series connection mode, and the purpose is to realize bidirectional cut-off of voltage signals under the condition that the auxiliary loops are not communicated by using N-MOSFET body diodes.
A voltage drop test method for an IR46 electric meter calibrating device specifically comprises the following steps:
step 1: the power source outputs voltage which is input to the voltage drop test device through the power line;
step 2: the input voltage enters a voltage sampling circuit 1, the voltage sampling circuit 1 monitors a waveform signal of the input voltage in real time, whether the output voltage of the power source is normal is judged, if the output voltage of the power source is normal, the step 4 is carried out, and if not, the voltage drop test is ended;
and step 3: the input voltage enters a zero-crossing detection circuit, and the zero-crossing detection circuit detects the zero crossing point of the input voltage;
and 4, step 4: the main controller identifies the zero crossing point of the voltage detected by the zero crossing detection circuit, calculates the signal frequency of the zero crossing point and collects the voltage signals of the voltage sampling circuits 1 and 2;
and 5: the main controller receives a control command sent by the PC, simultaneously uploads the collected voltage signal to the PC, and sends the control command to the voltage drop circuit in an optical coupling isolation mode
Step 6: the voltage sampling circuit 1 outputs a waveform signal to the voltage drop circuit, the voltage drop circuit simulates a voltage sag event or a voltage interruption event according to a command issued by the main controller and outputs voltage to the voltage sampling circuit 2;
and 7: the voltage sampling circuit 2 monitors the waveform signal of the voltage output by the voltage drop circuit in real time, judges whether the waveform signal meets the R46 standard and the actual requirement, if the waveform signal meets the R46 standard and the actual requirement, the step 8 is carried out, otherwise, the voltage drop test is ended;
and 8: the voltage sampling circuit 2 transmits the output voltage of the voltage drop circuit to the IR46 ammeter to be tested through a power line, the total electric quantity and each rate electric quantity of the tested meter are read through an RS485 interface before a drop test, the total electric quantity and each rate electric quantity of the tested meter are read through the RS485 interface after the drop test, and the test conclusion of the tested meter is calculated and judged, so that the IR46 ammeter drop test is completed.
Further, the simulation of the voltage sag event or the voltage interruption event has the following specific working principle:
1. voltage sag event:
after the voltage drop test device is electrified, the relay keeps a default state, the N-MOSFET control signal is at a low level, the main loop is on, the auxiliary loops 1, 2 and 3 are not on, the voltage signal is input from UA _ IN, passes through S1 and S2 and is output from UA _ OUT; when the upper computer sends a command for preparing a voltage sag test, IN the first step, S3, S4 and S5 are switched to a conducting state from a default state, a main loop is connected, secondary loops 1, 2 and 3 are disconnected, a voltage signal is input from UA _ IN and is output from UA _ OUT after passing through S1 and S2; secondly, the UA _ TRY is changed into high level, the main loop and the auxiliary loop are communicated with each other by 1, the auxiliary loops are not communicated by 2 and 3, a voltage signal is input by the UA _ IN and is divided into two paths, one path passes through S1 and S2 and is output from the UA _ OUT, and the other path passes through S3_ A, Q1, Q2, S3_ B and R101 and is output from the UA _ OUT; and thirdly, switching S1 and S2 from a default state to a conducting state, not conducting the main loop, conducting the auxiliary loop 1, not conducting the auxiliary loops 2 and 3, inputting a voltage signal from UA _ IN, passing through S3_ A, Q1, Q2, S3_ B and R101, and outputting the voltage signal from UA _ OUT, wherein the voltage sag loop is established.
After the voltage sag loop is established, the upper computer sends a command for starting a voltage sag test, and the voltage sag circuit can perform the voltage sag test according to the R46 standard or user definition; UA _ OUT outputs of UA30, UA60 and UA _ IN are realized by controlling signal levels of UA _30_ TRY, UA _60_ TRY and UA _ TRY, when UA _30_ TRY is IN a high level, UA _60_ TRY and UA _ TRY are IN a low level, a main loop is not communicated, auxiliary loops 1 and 2 are not communicated, an auxiliary loop 3 is communicated, a voltage signal is input by UA30, passes through S5, Q5, Q6, S3_ B and R101 and is output from UA _ OUT; when UA _60_ TRY is at high level, UA _30_ TRY and UA _ TRY are at low level, the main loop is not communicated, the auxiliary loops 1 and 3 are not communicated, the auxiliary loop 2 is communicated, a voltage signal is input from UA60, passes through S4, Q3, Q4, S3_ B and R101 and is output from UA _ OUT; when UA _ TRY is high, UA _30_ TRY and UA _60_ TRY are low, the main circuit is disabled, the sub-circuit 1 is enabled, the sub-circuits 2 and 3 are disabled, and a voltage signal is input from UA _ IN, passes through S3_ A, Q1, Q2, S3_ B, and R101, and is output from UA _ OUT.
When the upper computer sends OUT a command for finishing the voltage sag test, IN the first step, no matter what state the UA _30_ TRY, the UA _60_ TRY and the UA _ TRY are IN at the moment, the voltage sag circuit can force the UA _ TRY to be IN a high level, the UA _30_ TRY and the UA _60_ TRY to be IN a low level, the main loop is not communicated, the auxiliary loop 1 is communicated, the auxiliary loops 2 and 3 are not communicated, a voltage signal is input by the UA _ IN and is output from the UA _ OUT after passing through the S3_ A, Q1, the Q2, the S3_ B and the R101; secondly, S1, S2, S4 and S5 are switched from a conducting state to a default state, a main loop and an auxiliary loop 1 are communicated, auxiliary loops 2 and 3 are not communicated, a voltage signal is input from UA _ IN and divided into two paths, one path passes through S1 and S2 and is output from UA _ OUT, and the other path passes through S3_ A, Q1, Q2, S3_ B and R101 and is output from UA _ OUT; and thirdly, changing the UA _ TRY into a low level, enabling the main loop, disabling the auxiliary loops 1, 2 and 3, inputting a voltage signal from the UA _ IN, outputting the voltage signal from the UA _ OUT through S1 and S2, and finishing the voltage sag test.
2. A voltage interrupt event:
after the voltage drop test device is electrified, the relay keeps a default state, the N-MOSFET control signal is at a low level, the main loop is on, the auxiliary loops 1, 2 and 3 are not on, the voltage signal is input from UA _ IN, passes through S1 and S2 and is output from UA _ OUT; when the upper computer sends OUT a test command IN the prepared voltage, IN the first step, S3 is switched to a conducting state from a default state, a main loop is connected, secondary loops 1, 2 and 3 are disconnected, a voltage signal is input from UA _ IN and is output from UA _ OUT after passing through S1 and S2; secondly, the UA _ TRY is changed into high level, the main loop and the auxiliary loop are communicated with each other by 1, the auxiliary loops are not communicated by 2 and 3, the voltage signal is input by the UA _ IN and is divided into two paths, the path 1 passes through S1 and S2 and is output from the UA _ OUT, and the other path passes through S3_ A, Q1, Q2, S3_ B and R101 and is output from the UA _ OUT; thirdly, S1 and S2 are switched from the default state to the conducting state, the main loop is not conducted, the auxiliary loop 1 is conducted, the auxiliary loops 2 and 3 are not conducted, the voltage signal is input from UA _ IN, passes through S3_ A, Q1, Q2, S3_ B and R101 and is output from UA _ OUT, and the voltage interruption loop is established.
After the voltage interruption loop is established, the upper computer sends a command for starting a voltage interruption test, and the voltage drop circuit can perform the voltage interruption test according to the R46 standard or user-defined conditions; the UA _ OUT output is UN and UA _ IN by controlling the signal levels of UA _30_ TRY, UA _60_ TRY and UA _ TRY, when UA _30_ TRY and UA _60_ TRY are IN high level, UA _ TRY is IN low level, the main loop and the auxiliary loop 1 are not communicated, the auxiliary loop 2 and 3 are communicated, the voltage signal is input by UN and divided into two paths, and one path passes through resistors R103, S5, Q5, Q6, S3_ B and R101 and is output from UA _ OUT; the other path is output from UA _ OUT through resistors R102, S4, Q5, Q6, S3_ B and R101; when UA _ TRY is high, UA _30_ TRY and UA _60_ TRY are low, the main circuit is disabled, the sub-circuit 1 is enabled, the sub-circuits 2 and 3 are disabled, and a voltage signal is input from UA _ IN, passes through S3_ A, Q1, Q2, S3_ B, and R101, and is output from UA _ OUT.
When the upper computer sends OUT a command for ending voltage interruption test, IN the first step, no matter what state UA _30_ TRY, UA _60_ TRY and UA _ TRY are IN at the moment, the voltage drop circuit forces UA _ TRY to be IN a high level, UA _30_ TRY and UA _60_ TRY to be IN a low level, the main loop is not communicated, the auxiliary loop 1 is communicated, the auxiliary loops 2 and 3 are not communicated, a voltage signal is input by UA _ IN and is output from UA _ OUT after passing through S3_ A, Q1, Q2, S3_ B and R101; secondly, S1 and S2 are switched from a conducting state to a default state, a main loop and an auxiliary loop are communicated with each other, the auxiliary loops are not communicated with each other 2 and 3, a voltage signal is input from UA _ IN and is divided into two paths, one path passes through S1 and S2 and is output from UA _ OUT, and the other path passes through S3_ A, Q1, Q2, S3_ B and R101 and is output from UA _ OUT; and thirdly, the UA _ TRY is changed into low level, the main loop is switched on, the auxiliary loops 1, 2 and 3 are switched off, a voltage signal is input from the UA _ IN and is output from the UA _ OUT through S1 and S2 until the voltage interruption test is completed.
The invention has the beneficial effects that: the method has the advantages that the distortion degree of the voltage signal is not influenced, the switching time is short, the voltage signal is received and monitored in real time through the main controller, the IR46 ammeter drop test is automatically realized, the test result is accurate, and the labor and time cost are saved.
Drawings
Fig. 1 is a structural block diagram of a voltage drop test device for an IR46 electric meter verification device according to the present invention.
Fig. 2 is a voltage drop circuit diagram of a voltage drop test device for an IR46 electric meter verification device according to the present invention.
Fig. 3 is a flow chart of a voltage drop test method for an IR46 electric meter verification device according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and do not limit the invention.
As shown in fig. 1, the voltage drop detection circuit comprises a voltage sampling circuit 1, a voltage dropping circuit, a voltage sampling circuit 2, a zero-crossing detection circuit, a power supply circuit, a TCP/IP network communication module and a main controller, wherein:
a voltage sampling circuit 1 for detecting a waveform signal of an input voltage in real time;
and the voltage dropping circuit is used for simulating voltage sag and interruption events in the R46 standard. Testing the voltage sag, namely, reducing the voltage sag to 30 percent for 0.5 period; testing voltage sag, namely b, reducing the voltage sag to 60 percent for 1 period; voltage sag test c, down to 60% for 25 cycles (50Hz) or 30 cycles (60 Hz); the voltage was interrupted and tested, reduced to 0%, for 250 cycles (50Hz) or 300 cycles (60 Hz); the voltage reduction is repeated 10 times at intervals of at least 10 seconds;
the voltage sampling circuit 2 is used for monitoring the waveform signal of the output voltage of the voltage drop circuit in real time and judging whether the waveform signal meets the R46 standard and the actual requirement;
the zero-crossing detection circuit is used for quickly and accurately detecting the zero crossing point of the input voltage;
the power circuit is used for providing electric energy for the whole device, and the influence of the voltage drop device on an input voltage signal is reduced by adopting a linear multi-path isolation power supply, so that the control complexity is reduced;
the TCP/IP network communication module is connected with an external PC, receives a control command sent by the upper computer, sends the control command to the main controller, and sends a waveform signal monitored by the voltage sampling circuit 2 to the upper computer;
the main controller controls the voltage dropping circuit and the voltage sampling circuits 1 and 2 to work, monitors a voltage zero-crossing signal, receives a control command from an external PC (personal computer) and uploads waveform signals of input and output voltages to the PC;
the input end of the voltage sampling circuit 1 is connected with an external power source and a zero-crossing detection circuit, and the output end of the voltage sampling circuit is connected with a voltage drop circuit; the input end of the voltage sampling circuit 2 is connected with the voltage drop circuit, and the output end of the voltage sampling circuit is connected with an external IR46 electric meter; the main controller is respectively connected with the voltage sampling circuits 1 and 2, the voltage drop circuit, the zero-crossing detection circuit, the power supply circuit and the TCP/IP network communication module; the TCP/IP network communication module is also connected with an external PC.
As shown in fig. 2, the voltage dropping circuit includes double pole double throw relays S1, S2, and S3; single pole double throw relays S4, S5, N-MOSFETs Q1, Q2, Q3, Q4, Q5 and Q6; resistors R1, R2, R3, R101, R102, R103, R201, R202, and R203; capacitors C1, C2, C3, C201, C202 and C203 and transformer T1; according to the standard of R46, the transformer T1 has two taps, which are respectively positioned at 30% and 60%, and different transformers can be configured according to actual requirements.
The components are connected with each other IN a manner shown IN fig. 2, wherein UA _ IN represents an input voltage signal, UA _ OUT represents an output voltage signal, UN represents a voltage signal reference level, UA30 and UA60 represent voltage signals at 30% and 60% outputs of a transformer T1, UA _30_ TRY, UA _60_ TRY and UA _ TRY represent corresponding N-MOSFET control signals, and a broken line represents a default state of a relay. A channel formed by double-pole double-throw relays S1 and S2 is a main loop; a channel consisting of a double-pole double-throw relay S3, an N-MOSFET Q1 and a Q2 is a secondary loop 1; a channel consisting of the single-pole double-throw relay S4, the N-MOSFET Q3 and the Q4 is a secondary loop 2; the channel consisting of the single-pole double-throw relay S5, the N-MOSFETs Q5 and Q6 is the secondary loop 3. The main loop adopts a mode that double-pole double-throw relays S1 and S2 are connected in parallel, so that the impedance of the main loop is reduced; the auxiliary loops 1, 2 and 3, N-MOSFET adopt a series connection mode, and the purpose is to realize bidirectional cut-off of voltage signals under the condition that the auxiliary loops are not communicated by using N-MOSFET body diodes.
As shown in fig. 3, a voltage drop test method for an IR46 electric meter calibrating device specifically includes the following steps:
step 1: the power source outputs voltage which is input to the voltage drop test device through the power line;
step 2: the input voltage enters a voltage sampling circuit 1, the voltage sampling circuit 1 monitors a waveform signal of the input voltage in real time, whether the output voltage of the power source is normal is judged, if the output voltage of the power source is normal, the step 4 is carried out, and if not, the voltage drop test is ended;
and step 3: the input voltage enters a zero-crossing detection circuit, and the zero-crossing detection circuit detects the zero crossing point of the input voltage;
and 4, step 4: the main controller identifies the zero crossing point of the voltage detected by the zero crossing detection circuit, calculates the signal frequency of the zero crossing point and collects the voltage signals of the voltage sampling circuits 1 and 2;
and 5: the main controller receives a control command sent by the PC, simultaneously uploads the collected voltage signal to the PC, and sends the control command to the voltage drop circuit in an optical coupling isolation mode
Step 6: the voltage sampling circuit 1 outputs a waveform signal to the voltage drop circuit, the voltage drop circuit simulates a voltage sag event or a voltage interruption event according to a command issued by the main controller and outputs voltage to the voltage sampling circuit 2;
and 7: the voltage sampling circuit 2 monitors the waveform signal of the voltage output by the voltage drop circuit in real time, judges whether the waveform signal meets the R46 standard and the actual requirement, if the waveform signal meets the R46 standard and the actual requirement, the step 8 is carried out, otherwise, the voltage drop test is ended;
and 8: the voltage sampling circuit 2 transmits the output voltage of the voltage drop circuit to the IR46 ammeter to be tested through a power line, the total electric quantity of the tested meter is read through an RS485 interface before the drop test, the total electric quantity of the tested meter is read through the RS485 interface after the drop test, and the test conclusion of the tested meter is judged, so far, the IR46 ammeter drop test is completed.
Further, the simulation of the voltage sag event or the voltage interruption event has the following specific working principle:
1. voltage sag event:
after the voltage drop test device is electrified, the relay keeps a default state, the N-MOSFET control signal is at a low level, the main loop is on, the auxiliary loops 1, 2 and 3 are not on, the voltage signal is input from UA _ IN, passes through S1 and S2 and is output from UA _ OUT; when the upper computer sends a command for preparing a voltage sag test, IN the first step, S3, S4 and S5 are switched to a conducting state from a default state, a main loop is connected, secondary loops 1, 2 and 3 are disconnected, a voltage signal is input from UA _ IN and is output from UA _ OUT after passing through S1 and S2; secondly, the UA _ TRY is changed into high level, the main loop and the auxiliary loop are communicated with each other by 1, the auxiliary loops are not communicated by 2 and 3, a voltage signal is input by the UA _ IN and is divided into two paths, one path passes through S1 and S2 and is output from the UA _ OUT, and the other path passes through S3_ A, Q1, Q2, S3_ B and R101 and is output from the UA _ OUT; and thirdly, switching S1 and S2 from a default state to a conducting state, not conducting the main loop, conducting the auxiliary loop 1, not conducting the auxiliary loops 2 and 3, inputting a voltage signal from UA _ IN, passing through S3_ A, Q1, Q2, S3_ B and R101, and outputting the voltage signal from UA _ OUT, wherein the voltage sag loop is established.
After the voltage sag loop is established, the upper computer sends a command for starting a voltage sag test, and the voltage sag circuit can perform the voltage sag test according to the R46 standard or user definition; UA _ OUT outputs of UA30, UA60 and UA _ IN are realized by controlling signal levels of UA _30_ TRY, UA _60_ TRY and UA _ TRY, when UA _30_ TRY is IN a high level, UA _60_ TRY and UA _ TRY are IN a low level, a main loop is not communicated, auxiliary loops 1 and 2 are not communicated, an auxiliary loop 3 is communicated, a voltage signal is input by UA30, passes through S5, Q5, Q6, S3_ B and R101 and is output from UA _ OUT; when UA _60_ TRY is at high level, UA _30_ TRY and UA _ TRY are at low level, the main loop is not communicated, the auxiliary loops 1 and 3 are not communicated, the auxiliary loop 2 is communicated, a voltage signal is input from UA60, passes through S4, Q3, Q4, S3_ B and R101 and is output from UA _ OUT; when UA _ TRY is high, UA _30_ TRY and UA _60_ TRY are low, the main circuit is disabled, the sub-circuit 1 is enabled, the sub-circuits 2 and 3 are disabled, and a voltage signal is input from UA _ IN, passes through S3_ A, Q1, Q2, S3_ B, and R101, and is output from UA _ OUT.
When the upper computer sends OUT a command for finishing the voltage sag test, IN the first step, no matter what state the UA _30_ TRY, the UA _60_ TRY and the UA _ TRY are IN at the moment, the voltage sag circuit can force the UA _ TRY to be IN a high level, the UA _30_ TRY and the UA _60_ TRY to be IN a low level, the main loop is not communicated, the auxiliary loop 1 is communicated, the auxiliary loops 2 and 3 are not communicated, a voltage signal is input by the UA _ IN and is output from the UA _ OUT after passing through the S3_ A, Q1, the Q2, the S3_ B and the R101; secondly, S1, S2, S4 and S5 are switched from a conducting state to a default state, a main loop and an auxiliary loop 1 are communicated, auxiliary loops 2 and 3 are not communicated, a voltage signal is input from UA _ IN and divided into two paths, one path passes through S1 and S2 and is output from UA _ OUT, and the other path passes through S3_ A, Q1, Q2, S3_ B and R101 and is output from UA _ OUT; and thirdly, changing the UA _ TRY into a low level, enabling the main loop, disabling the auxiliary loops 1, 2 and 3, inputting a voltage signal from the UA _ IN, outputting the voltage signal from the UA _ OUT through S1 and S2, and finishing the voltage sag test.
2. A voltage interrupt event:
after the voltage drop test device is electrified, the relay keeps a default state, the N-MOSFET control signal is at a low level, the main loop is on, the auxiliary loops 1, 2 and 3 are not on, the voltage signal is input from UA _ IN, passes through S1 and S2 and is output from UA _ OUT; when the upper computer sends OUT a test command IN the prepared voltage, IN the first step, S3 is switched to a conducting state from a default state, a main loop is connected, secondary loops 1, 2 and 3 are disconnected, a voltage signal is input from UA _ IN and is output from UA _ OUT after passing through S1 and S2; secondly, the UA _ TRY is changed into high level, the main loop and the auxiliary loop are communicated with each other by 1, the auxiliary loops are not communicated by 2 and 3, the voltage signal is input by the UA _ IN and is divided into two paths, the path 1 passes through S1 and S2 and is output from the UA _ OUT, and the other path passes through S3_ A, Q1, Q2, S3_ B and R101 and is output from the UA _ OUT; thirdly, S1 and S2 are switched from the default state to the conducting state, the main loop is not conducted, the auxiliary loop 1 is conducted, the auxiliary loops 2 and 3 are not conducted, the voltage signal is input from UA _ IN, passes through S3_ A, Q1, Q2, S3_ B and R101 and is output from UA _ OUT, and the voltage interruption loop is established.
After the voltage interruption loop is established, the upper computer sends a command for starting a voltage interruption test, and the voltage drop circuit can perform the voltage interruption test according to the R46 standard or user-defined conditions; the UA _ OUT output is UN and UA _ IN by controlling the signal levels of UA _30_ TRY, UA _60_ TRY and UA _ TRY, when UA _30_ TRY and UA _60_ TRY are IN high level, UA _ TRY is IN low level, the main loop and the auxiliary loop 1 are not communicated, the auxiliary loop 2 and 3 are communicated, the voltage signal is input by UN and divided into two paths, and one path passes through resistors R103, S5, Q5, Q6, S3_ B and R101 and is output from UA _ OUT; the other path is output from UA _ OUT through resistors R102, S4, Q5, Q6, S3_ B and R101; when UA _ TRY is high, UA _30_ TRY and UA _60_ TRY are low, the main circuit is disabled, the sub-circuit 1 is enabled, the sub-circuits 2 and 3 are disabled, and a voltage signal is input from UA _ IN, passes through S3_ A, Q1, Q2, S3_ B, and R101, and is output from UA _ OUT.
When the upper computer sends OUT a command for ending voltage interruption test, IN the first step, no matter what state UA _30_ TRY, UA _60_ TRY and UA _ TRY are IN at the moment, the voltage drop circuit forces UA _ TRY to be IN a high level, UA _30_ TRY and UA _60_ TRY to be IN a low level, the main loop is not communicated, the auxiliary loop 1 is communicated, the auxiliary loops 2 and 3 are not communicated, a voltage signal is input by UA _ IN and is output from UA _ OUT after passing through S3_ A, Q1, Q2, S3_ B and R101; secondly, S1 and S2 are switched from a conducting state to a default state, a main loop and an auxiliary loop are communicated with each other, the auxiliary loops are not communicated with each other 2 and 3, a voltage signal is input from UA _ IN and is divided into two paths, one path passes through S1 and S2 and is output from UA _ OUT, and the other path passes through S3_ A, Q1, Q2, S3_ B and R101 and is output from UA _ OUT; and thirdly, the UA _ TRY is changed into low level, the main loop is switched on, the auxiliary loops 1, 2 and 3 are switched off, a voltage signal is input from the UA _ IN and is output from the UA _ OUT through S1 and S2 until the voltage interruption test is completed.
Claims (2)
1. The utility model provides a be used for IR46 ammeter calibrating installation voltage drop test device, contains voltage sampling circuit 1, voltage drop circuit, voltage sampling circuit 2, zero passage detection circuit, power supply circuit, TCP/IP network communication module and master controller, its characterized in that:
a voltage sampling circuit 1 for detecting a waveform signal of an input voltage in real time;
the voltage sag circuit is used for simulating voltage sag and interruption events in an R46 standard, and specifically comprises the following components: testing the voltage sag, namely, reducing the voltage sag to 30 percent for 0.5 period; testing voltage sag, namely b, reducing the voltage sag to 60 percent for 1 period; voltage sag test c, down to 60% for 25 cycles (50Hz) or 30 cycles (60 Hz); the voltage was interrupted and tested, reduced to 0%, for 250 cycles (50Hz) or 300 cycles (60 Hz); the voltage reduction is repeated 10 times at intervals of at least 10 seconds;
the voltage sampling circuit 2 is used for monitoring the waveform signal of the output voltage of the voltage drop circuit in real time and judging whether the waveform signal meets the R46 standard and the actual requirement;
the zero-crossing detection circuit is used for quickly and accurately detecting the zero crossing point of the input voltage;
the power circuit is used for providing electric energy for the whole device, and the influence of the voltage drop device on an input voltage signal is reduced by adopting a linear multi-path isolation power supply, so that the control complexity is reduced;
the TCP/IP network communication module is connected with an external PC, receives a control command sent by the upper computer, sends the control command to the main controller, and sends a waveform signal monitored by the voltage sampling circuit 2 to the upper computer;
the main controller controls the voltage dropping circuit and the voltage sampling circuits 1 and 2 to work, monitors a voltage zero-crossing signal, receives a control command from an external PC (personal computer) and uploads waveform signals of input and output voltages to the PC;
the input end of the voltage sampling circuit 1 is connected with an external power source and a zero-crossing detection circuit, and the output end of the voltage sampling circuit is connected with a voltage drop circuit; the input end of the voltage sampling circuit 2 is connected with the voltage drop circuit, and the output end of the voltage sampling circuit is connected with an external IR46 electric meter; the main controller is respectively connected with the voltage sampling circuits 1 and 2, the voltage drop circuit, the zero-crossing detection circuit, the power supply circuit and the TCP/IP network communication module.
2. A voltage drop test method for an IR46 electric meter calibrating device is characterized by comprising the following steps:
step 1: the power source outputs voltage which is input to the voltage drop test device through the power line;
step 2: the input voltage enters a voltage sampling circuit 1, the voltage sampling circuit 1 monitors a waveform signal of the input voltage in real time, whether the output voltage of the power source is normal is judged, if the output voltage of the power source is normal, the step 4 is carried out, and if not, the voltage drop test is ended;
and step 3: the input voltage enters a zero-crossing detection circuit, and the zero-crossing detection circuit detects the zero crossing point of the input voltage;
and 4, step 4: the main controller identifies the zero crossing point of the voltage detected by the zero crossing detection circuit, calculates the signal frequency of the zero crossing point and collects the voltage signals of the voltage sampling circuits 1 and 2;
and 5: the main controller receives a control command sent by the PC, simultaneously uploads the collected voltage signal to the PC, and sends the control command to the voltage drop circuit in an optical coupling isolation mode
Step 6: the voltage sampling circuit 1 outputs a waveform signal to the voltage drop circuit, the voltage drop circuit simulates a voltage sag event or a voltage interruption event according to a command issued by the main controller and outputs voltage to the voltage sampling circuit 2;
and 7: the voltage sampling circuit 2 monitors the waveform signal of the voltage output by the voltage drop circuit in real time, judges whether the waveform signal meets the R46 standard and the actual requirement, if the waveform signal meets the R46 standard and the actual requirement, the step 8 is carried out, otherwise, the voltage drop test is ended;
and 8: the voltage sampling circuit 2 transmits the output voltage of the voltage drop circuit to the IR46 ammeter to be tested through a power line, the total electric quantity and each rate electric quantity of the tested meter are read through an RS485 interface before a drop test, the total electric quantity and each rate electric quantity of the tested meter are read through the RS485 interface after the drop test, and the test conclusion of the tested meter is calculated and judged, so that the IR46 ammeter drop test is completed.
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