CN113767368A

CN113767368A - Resource acquisition method, related device and computer storage medium

Info

Publication number: CN113767368A
Application number: CN201980095065.XA
Authority: CN
Inventors: 齐元吉·查克拉博蒂; 谢时岳; 张建明
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2019-04-29
Filing date: 2019-04-29
Publication date: 2021-12-07
Also published as: WO2020220225A1

Abstract

The embodiment of the invention discloses a resource acquisition method, a related device and a computer storage medium, wherein the method comprises the following steps: receiving at least one resource request, and storing the at least one resource request in a logic stack, wherein each resource request is sent by one processor core, the resource requests are in one-to-one correspondence with the processor cores, and the resource requests are used for requesting logic resources for the corresponding processor cores; the target resource request is a resource request with the highest priority and located in the logic stack, and the target logic resource is further allocated to the target resource request, and only one resource request is allowed to allocate the logic resource in one working clock cycle. By adopting the embodiment of the invention, the problems that a certain resource request is difficult to be allocated to the logic resource in the existing multi-thread parallel logic resource allocation scheme for the resource request, so that the service and the service performance corresponding to the resource request are influenced and the like can be solved.

Description

Resource acquisition method, related device and computer storage medium

Technical Field

The present invention relates to the field of internet technologies, and in particular, to a resource acquisition method, a related apparatus, and a computer storage medium.

Background

With the increase of process and the increase of internet business requirements, the design of a System On Chip (SOC) becomes more complex, and the number of CPUs integrated on the same chip is more and more. For the reasons of cost and power consumption, the number of resources supported by a Central Processing Unit (CPU) is limited, and multiple CPUs support the same resource. The resource may be a data resource provided by a preset resource module, such as a key resource generated by a key generator, an algorithm resource provided by an algorithm engine module, and so on. In consideration of the information security problem of the CPUs, different CPUs are isolated by adopting a hardware lock. For each CPU, when an application program needs to use resources, the CPU needs to inquire idle resources and configure a command for preempting a hardware lock, and the hardware lock is used for locking and protecting the idle resources. And releasing the hardware lock after the idle resource is used up, so as to carry out the next re-robbing of the lock.

For each CPU, it goes through the processes of command parsing-execution-response-result return, etc. The duty cycle of each CPU is typically on the order of hundreds of microseconds or even milliseconds. In a scenario where multiple CPUs operate in parallel through multiple threads, each CPU operates independently through a respective thread to preempt idle resources and hardware locks of the idle resources for the CPU. In practical application, due to the limitation of CPU hardware, etc., the preemption speed of a certain CPU may be slower than that of another CPU, which may cause the CPU to be difficult to preempt resources, thereby affecting the normal service communication and service performance of the CPU.

Disclosure of Invention

The embodiment of the invention discloses a resource acquisition method, a related device and a computer storage medium, which can solve the problems that data resources are difficult to seize, normal service communication and service performance are influenced and the like in the prior art.

In a first aspect, an embodiment of the present invention discloses a resource obtaining method, where the method includes: the logic stack can receive and store at least one resource request, wherein each resource request is sent by one processor core, the resource request and the processor cores are in one-to-one correspondence, and the resource request is used for requesting logic resources for the corresponding processor cores. When the target resource request is popped from the logic stack, the resource allocation logic circuit may allocate the target logic resource for the target resource request, and may allocate the logic resource for only one resource request within one working clock cycle, where the target resource request is a resource request with the highest priority in the logic stack.

By implementing the embodiment of the invention, at least one resource request can be stored by using the logic stack, the logic stack can only process one resource request in one working clock cycle, and each resource request stored in the logic stack can be processed, so that the resource request of each processor core can be guaranteed to be finally robbed to the resource. And the problem that the normal service communication and the service performance of the individual CPU are influenced because the individual CPU can not always snatch the resources when the multi-thread is adopted to allocate the resources for the multi-CPU in the traditional technology can be solved.

With reference to the first aspect, in some possible embodiments, the resource allocation logic may query whether there is an idle resource for the target processor core after receiving the target resource request, where the target processor core is the processor core that sends the target resource request. When the resource allocation logic circuit inquires that the idle resource exists, the idle resource can be used as the target logic resource to be allocated to the target processor core. The free resources refer to resources that are unused or unoccupied.

By implementing the step, the resource allocation logic circuit can select idle resources as target logic resources to be allocated to the target processor core for use, so that the phenomenon that the target processor core cannot be used due to the fact that some occupied logic resources which are currently used are allocated to the target processor core is avoided, and the reasonability and the reliability of resource allocation are improved.

With reference to the first aspect, in some possible embodiments, after the resource allocation logic allocates the target processor core, the resource allocation logic may further automatically preempt a target protection lock corresponding to the target logic resource according to the target resource request, so that the target processor core may access the target logic resource based on the target protection lock. Further, the resource allocation logic may report a pre-lock result to the target processor core in response to the interrupt, the pre-lock result indicating successful preemption of the target dongle. The target processor core can obtain the target protection lock after receiving the lock robbing result, and then the target logic resource is accessed and used based on the target protection lock.

By implementing the steps, the resource allocation logic circuit can allocate the target logic resource for the target processor core according to the target resource request, and meanwhile, successfully preempts the target protection lock of the target logic resource, compared with the prior art that the CPU needs to issue a lock preemption command again after inquiring the target logic resource, the resource allocation logic circuit can greatly reduce the flow steps of resource acquisition and improve the convenience and the efficiency of resource acquisition. In addition, after any processor Core (CPU) sends the resource request of the processor core, the control right or the occupation right of the processor core can be automatically released, and then the resource allocation logic circuit inquires idle resources according to the resource request of the processor core and automatically occupies a protection lock corresponding to the idle resources after finding the idle resources, so that the occupation of the CPU can be reduced, and the utilization rate of the CPU is improved.

With reference to the first aspect, in some possible embodiments, each resource request carries an identifier, where the identifier is used to indicate a processor core to which the corresponding resource request belongs. After receiving any resource request, the logic stack may determine the identifier carried in the resource request. And determining whether to store the resource request in the logic stack according to the identification.

By implementing the step, the logic stack can determine whether to store the resource request of the processor core in the logic stack according to the identifier of the processor core so as to ensure that at least one resource request of each processor core is stored in the logic stack, thereby ensuring that resources can be allocated to at least one resource request of each processor core in the subsequent process, avoiding the problem that a plurality of resource requests of some processor cores enter the logic stack, so that the resource requests of other processor cores cannot be stacked after the logic stack is full, providing a fair stacking opportunity for the resource request of each processor core, and avoiding the problem that the CPU of some processor cores is difficult to occupy the resources in the traditional technology, thereby influencing the normal service communication and the service performance of the CPU, and the like.

With reference to the first aspect, in some possible embodiments, the storage capacity of the logic stack supports storing n resource requests, the total number of processor cores is m, and n ═ m, then the logic stack only allows one resource request of each of the m processor cores to be stored in the logic stack.

With reference to the first aspect, in some possible embodiments, the storage capacity of the logical stack supports storing m resource requests, and the total number of processor cores is m, then the logical stack allows only one resource request of the plurality of resource requests having the same identifier to be stored in the logical stack.

With reference to the first aspect, in some possible embodiments, the storage capacity of the logical stack supports storing n resource requests, the total number of processor cores is m, and n > m, then the logical stack allows at least two resource requests of a first processor core to be stored in the logical stack, the first processor core being any one of the m processor cores.

In combination with the first aspect, in some possible embodiments, the logical stack is a first-in-first-out unit FIFO logical stack.

In combination with the first aspect, in some possible embodiments, the resource allocation logic is deployed independently of the processor core.

With reference to the first aspect, in some possible embodiments, the processor cores are disposed in the communication device, that is, the communication device further includes the processor cores, and the number of the processor cores is not limited.

In combination with the first aspect, in some possible embodiments, the logical stack receives an undo command for a first resource request, the first resource request being any of the at least one resource request. Further, the logical stack may perform dequeue processing on the first resource request according to the undo command, so as to delete the first resource request stored in the logical stack.

By implementing the step, the logic stack supports providing a queue-insertion and stack-popping mechanism so as to undo the first resource request to be undone, and the flexibility of resource acquisition is improved.

With reference to the first aspect, in some possible embodiments, after deleting the first resource request, the resource allocation logic may report an undo result to the processor core corresponding to the first resource request through an interrupt response, where the undo result is used to indicate that the logical stack has completed the undo of the first resource request.

By implementing the step, the revocation result is sent to the processor core to which the first resource request belongs in an interruption mode so as to inform that revocation aiming at the first resource request is completed, and the flexibility of resource acquisition is improved.

In a second aspect, an embodiment of the present invention provides a communications apparatus, including a logic stack and a resource allocation logic, wherein,

the logic stack is used for receiving at least one resource request and storing the at least one resource request to the logic stack, wherein each resource request is sent by a processor core, the resource requests are in one-to-one correspondence with the processor cores, and the resource requests are used for requesting logic resources for the corresponding processor cores;

the resource allocation logic circuit is configured to allocate a target logic resource for a target resource request, and allocate a logic resource for only one resource request in one working clock cycle, where the target resource request is a resource request located in the logic stack and having the highest priority.

With reference to the second aspect, in some possible embodiments, the resource allocation logic is specifically configured to, after receiving the target resource request, query whether there is a free resource for the target processor core to use; and when inquiring that idle resources exist, allocating the idle resources to a target processor core as the target logic resources, wherein the target processor core is the processor core which sends the target resource request.

With reference to the second aspect, in some possible embodiments, after the resource allocation logic allocates the idle resource as the target logical resource to the target processor core, the resource allocation logic is further configured to automatically preempt a target dongle corresponding to the target logical resource according to the target resource request, where the target processor core accesses the target logical resource based on the target dongle; reporting a rob lock result to the target processor core through an interrupt response, wherein the rob lock result is used for indicating that the target protection lock is successfully robed.

With reference to the second aspect, in some possible embodiments, each resource request carries an identifier, where the identifier is used to indicate a processor core to which the corresponding resource request belongs, and the logic stack is further configured to determine, after receiving one resource request, the identifier carried in the resource request; and determining whether to store the resource request into the logic stack according to the identifier carried by the resource request.

With reference to the second aspect, in some possible embodiments, the storage capacity of the logic stack supports storing n resource requests, the total number of processor cores is m, and n is m, then the logic stack only allows one resource request of each processor core in the m processor cores to be stored in the logic stack.

With reference to the second aspect, in some possible embodiments, the storage capacity of the logical stack supports storage of m resource requests, and the total number of processor cores is m, then the logical stack only allows one resource request of the multiple resource requests having the same identifier to be stored in the logical stack.

With reference to the second aspect, in some possible embodiments, the storage capacity of the logic stack supports storing n resource requests, the total number of processor cores is m, and n is greater than m, then the logic stack allows at least two resource requests of a first processor core to be stored in the logic stack, where the first processor core is any one of the m processor cores.

In combination with the second aspect, in some possible embodiments, the logical stack is a first-in-first-out unit FIFO logical stack.

In combination with the second aspect, in some possible embodiments, the resource allocation logic is independent of the processor core.

In combination with the second aspect, in some possible embodiments, the apparatus further includes: a plurality of the processor cores.

In combination with the second aspect, in some possible embodiments, the logical stack is further configured to receive an undo command for a first resource request, the first resource request being any of the at least one resource request; and deleting the first resource request stored in the logic stack according to the withdrawal command.

With reference to the second aspect, in some possible embodiments, after the logic stack deletes the first resource request, the resource allocation logic is configured to report an undo result to a processor core corresponding to the first resource request through an interrupt response, where the undo result is used to indicate that the logic stack has completed the undo of the first resource request.

For the content that is not shown or not described in the embodiment of the present invention, reference may be made to the related description in the method embodiment described in the foregoing first aspect, and details are not repeated here.

In a third aspect, an embodiment of the present invention provides a communication system, including m processor cores, a logic stack, and a resource allocation logic circuit. Optionally, a dongle and resources may also be included. Wherein, the processor core can be arranged in the host device, and the logic stack, the resource allocation logic circuit, the protection lock and the resource can be arranged in the slave device. Accordingly, the communication system may comprise m master devices and slave devices, which by means of the components disposed in the own device may be adapted to perform the method as described in the first aspect above. Illustratively, a communication system includes m master devices and slave devices, wherein,

the master device is used for sending a resource request to the slave device;

the slave device is used for receiving at least one resource request and storing the at least one resource request into a logic stack of the slave device, each resource request is sent by one processor core, the resource requests are in one-to-one correspondence with the processor cores, and the resource requests are used for requesting logic resources for the corresponding processor cores;

the slave device is further configured to allocate a target logic resource for a target resource request, and allocate a logic resource for only one resource request in one working clock cycle, where the target resource request is a resource request located in the logic stack and having the highest priority.

With reference to the third aspect, in some possible embodiments, the slave device is specifically configured to, after receiving the target resource request, query whether there is an idle resource for the target processor core; and when the idle resources are inquired, allocating the idle resources as target logic resources to a target processor core, wherein the target processor core is the processor core which sends the target resource request.

With reference to the third aspect, in some possible embodiments, after the slave device allocates an idle resource as a target logical resource to the target processor core, the slave device is further configured to automatically preempt a target dongle corresponding to the target logical resource according to a target resource request, where the target processor core accesses the target logical resource based on the target dongle; and reporting a locking result to the target processor core through the interrupt response, wherein the locking result is used for indicating that the target protection lock is successfully preempted.

With reference to the third aspect, in some possible embodiments, each resource request carries an identifier, where the identifier is used to indicate a processor core to which the corresponding resource request belongs, and the slave device is further configured to determine, after receiving one resource request, the identifier carried in the resource request; and determining whether the resource request is stored in the logic stack or not according to the identifier carried by the resource request.

With reference to the third aspect, in some possible embodiments, the storage capacity of the logic stack supports storing n resource requests, the total number of processor cores is m, and n ═ m, then the logic stack allows only one resource request of each of the m processor cores to be stored in the logic stack.

With reference to the third aspect, in some possible embodiments, the storage capacity of the logical stack supports storing m resource requests, and the total number of processor cores is m, the logical stack allows only one resource request of the plurality of resource requests having the same identification to be stored in the logical stack.

With reference to the third aspect, in some possible embodiments, the storage capacity of the logical stack supports storing n resource requests, the total number of processor cores is m, and n > m, the logical stack allows at least two resource requests of a first processor core to be stored in the logical stack, the first processor core being any one of the m processor cores.

In combination with the third aspect, in some possible embodiments, the logical stack is a first-in-first-out unit FIFO logical stack.

With reference to the third aspect, in some possible embodiments, the slave device is further configured to receive a withdrawal command for a first resource request, where the first resource request is any one of the at least one resource request; and deleting the first resource request stored in the logic stack according to the undo command.

With reference to the third aspect, in some possible embodiments, after deleting the first resource request, the slave device is further configured to report, by an interrupt response, a revocation result to the host device corresponding to the first resource request, where the revocation result is used to indicate that the logical stack has completed revocation of the first resource request.

In a fourth aspect, there is provided a communications device comprising a processor arranged with a logic stack and resource allocation logic circuitry, the processor being arranged, in actual runtime, to perform the method as described in the first aspect above. Optionally, any one or a combination of more of the following may also be included in the communication device: a logic resource, a dongle, and at least one processor core.

In a fifth aspect, a computer-readable storage medium is provided, the computer-readable storage medium being configured to execute the instructions of the method described in the first aspect above.

In a sixth aspect, there is provided a chip product for carrying out the method of the first aspect or any possible embodiment of the first aspect.

The invention can be further combined to provide more implementation modes on the basis of the implementation modes provided by the aspects.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below.

Fig. 1 is a schematic diagram of a scenario in which a CPU preempts data resources according to the prior art.

Fig. 2 is a schematic diagram of another scenario in which a CPU preempts data resources according to the prior art.

Fig. 3 is a schematic structural diagram of a communication system according to an embodiment of the present invention.

Fig. 4 is a schematic diagram of a logical stack storage according to an embodiment of the present invention.

Fig. 5 is a schematic structural diagram of another communication system according to an embodiment of the present invention.

Fig. 6 is a flowchart illustrating a resource obtaining method according to an embodiment of the present invention.

Fig. 7 is a schematic diagram of a logic stack according to an embodiment of the present invention.

Fig. 8 is a flowchart illustrating another resource obtaining method according to an embodiment of the present invention.

Fig. 9 is a schematic diagram of a change of a logic stack according to an embodiment of the present invention.

Fig. 10 is a schematic structural diagram of a communication device according to an embodiment of the present invention.

Fig. 11 is a schematic structural diagram of a communication device according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be described in detail below with reference to the accompanying drawings of the present invention.

Fig. 1 is a schematic diagram illustrating a scenario in which a CPU preempts a data resource. The schematic diagram of fig. 1 includes 3 lock preemption requests, N resources, and N hardware locks. And each hardware lock correspondingly protects one resource and is used for carrying out encryption protection on the resource. Each lock robbing request is generated by one CPU when the resources are needed to be used, and different lock robbing requests correspond to different CPUs. The figure respectively shows the lock-robbing requests generated by 3 CPUs, specifically, a CPU1request, a CPU2request and a CPU3 request; the N resources are respectively resources 1-N, and the N hardware locks are respectively Lock 1-Lock N.

When an application program on the device needs to use resources, a query request may be generated, and further, the CPU invokes a loop query program to query available idle data resources (hereinafter referred to as idle resources), for example, the CPU queries respective state information of each resource by invoking a loop query degree, where the state information includes occupation or idle. When the state information is occupied, it indicates that the resource is being occupied, e.g., used by other applications. When the state information is idle, it indicates that the resource is not occupied currently, and is idle, and the application program can use the idle resource at this time. When the CPU inquires that the state information is the idle resource, the resource is indicated as the idle resource currently available for the application program.

Accordingly, after inquiring the free resources, the CPU can send out a lock robbing command. The lock preemption command is used for preempting a hardware lock corresponding to the idle resource so as to unlock the idle resource by using the hardware lock, thereby obtaining the idle resource. When the application program can not inquire the available free resources through the CPU, a sleep waiting program can be run to wait for continuously searching the available free resources.

However, in practice, it has been found that in the case of sufficient resources, the application can query the available free resources each time it passes through the CPU. In the case of resource shortage, all resources may be fully occupied, and the CPU cannot inquire available free resources. However, in the case of no available free resources, the application will still go through the process of query request parsing- > query request execution- > query request response- > result return. In practical applications, there is a certain delay consumption in the transmission of the lock preemption request on the chip bus, so the query period of an idle resource usually reaches the order of hundreds of microseconds or even milliseconds. In addition, when an asynchronous multithreading scheduling scenario is considered, at least one sleep waiting function needs to be inserted between every two query requests, and the time consumed for completing one query of idle resources under the scenario is usually in the order of milliseconds or even tens of milliseconds. In the time interval of tens of milliseconds, the query speed of the CPU may be slower than that of another CPU, so that the CPU is difficult to query and seize available idle resources, thereby affecting normal traffic communication and affecting the quality of service.

Fig. 2 is a schematic diagram illustrating a process of preempting data resources by a CPU. Wherein the horizontal axis represents time, the figure shows that three CPUs perform the specific implementation process of preempting the data resource by the respective CPUs along the time axis. As shown in fig. 2, the time sequence of the query requests sent by the three CPUs for the idle resources is as follows: CPU2> CPU1> CPU 3. As shown, for a device that provides limited free resources, the inquiry request sent by the CPU2 is preferably processed to inquire whether there are available free resources in the device. When the idle resource is found, the CPU2 may preempt the hardware lock corresponding to the idle resource, so that the CPU may unlock the idle resource through the hardware lock to use the idle resource. Optionally, the CPU2 may also report a query result indicating that the available free resources were queried by the CPU2 or indicating that the available free resources were not queried by the CPU 2. Alternatively, after CPU2 runs out of the free resources, the free resources may be released for use by other CPUs.

As shown in the diagram during the process of the CPU2 querying for free resources, the CPU1 also has a demand for free resource usage by sending a query request to query for available free resources in the device. As shown, the time that the CPU1 sends the query request is later than the time that the CPU2 sends the query request. When the CPU1 queries for an idle resource through the query request, since the idle resource is preempted by the query of the CPU2, the CPU1 may return a query result at this time, where the query result indicates that the idle resource is preempted by the CPU2 and there is no available idle resource currently, so as to notify the CPU1 to wait for re-query or end the process. Alternatively, CPU1 may run a sleep wait program that continues to query for and preempt available idle resources with the query request after waiting a preset length of time. Similarly, while the CPU1 waits, the CPU2 has used and released the free resources, and the CPU3 sends a query request to satisfy its own use requirement of the free resources. Accordingly, the CPU3 queries for and preempts idle resources through query requests. After CPU1 runs the sleep wait program, it can continue to query whether there are free resources in the device through its query request. Since the idle resource is preempted by the CPU3 at this time, the CPU1 may report a corresponding query result, where the query result is used to indicate that the idle resource is preempted by the CPU3 and there is no available idle resource currently.

As can be seen from the figure, in a scenario where the number of CPUs is large, it is difficult for the CPUs to seize idle resources, which easily causes that the CPUs cannot seize idle resources, thereby affecting the normal service communication of the CPUs and affecting the service performance.

In order to solve the above problems, the present application provides a resource acquisition method, and a related apparatus and system to which the method is applicable. Fig. 3 is a schematic structural diagram of a communication system according to an embodiment of the present invention. The communication system 300 as shown in fig. 3 includes m processor cores 302, a logic stack 304, and resource allocation logic 306. Optionally, the communication system may also include dongle 308 and resource 310. The number of the dongle 308 and the resource 310 is not limited, and may be one or more, and a plurality of the dongle 308 and a plurality of the resource 310 are illustrated as an example. m is a positive integer. Wherein the content of the first and second substances,

the processor core 302 is configured to send a resource request to obtain free resources required to be used by the processor core when detecting that the resources are required to be used. The idle resource refers to a resource that is not used by other processor cores, and includes, but is not limited to, a computing resource, a storage resource, a network resource, and the like, for example, the resource may be a key derivation module deployed in a communication system, and the key derivation module is configured to provide a communication key to ensure secure transmission of data. In an optional case, the resource is a hardware logic resource, and the processor core performs corresponding logic operation or completes a corresponding function through the hardware logic resource.

The logical stack 304 is configured to cache a resource request (i.e., a query request of the present application) sent by the processor core 302, the resource request requesting to obtain free resources for use by the processor core 302. The number of storage resource requests supported in the logical stack 304 is not limited and depends on the storage capacity of the logical stack 304. The logical stack 304 supports the storage of one or more resource requests sent by the same processor core 302. Specifically, when the storage capacity of the logic stack 304 supports storing n resource requests, and n ═ m, only one resource request of each of the m processor cores 302 is allowed to be stored in the logic stack 304. When n is greater than m, at least two resource requests of a first processor core, which is any one of the m processor cores, are allowed to be stored in the logic stack 304; in other words, when the logical stack 304 supports a number n of memory resource requests greater than the total number m of processor cores, at least two free resources storing the same processor core 302 are supported in the logical stack 304.

Optionally, each resource request carries an identifier, where the identifier is used to indicate a processor core that sends the resource request, and the identifier may include, but is not limited to, a name of the processor core, an identity ID, and other information. Accordingly, after receiving the resource request sent by the processor core 302, the logic stack 304 can automatically identify the identifier carried in the resource request, so as to record the identifier of the processor core corresponding to the resource request. Further, the logic stack 304 may determine whether to store the resource request in the logic stack 304 according to the identifier carried in the resource request, which may be specifically described in the foregoing related description of storing according to the storage capacity of the logic stack 304. The number n of the storage resource requests supported in the logical stack 304, which may also be referred to as the depth (or length) of the logical stack 304, is not limited.

In view of the reasonableness of resource request processing, the depth n of the logical stack 304 and the total number m of processor cores are generally equal, and only one resource request of a plurality of resource requests with the same identification is allowed to be pushed into the logical stack 304 for storage. Specifically, when a plurality of resource requests are sent by the same processor core, each resource request carries an identifier (cpu _ id) of the same processor core. Accordingly, after receiving the resource request sent by the same processor core for the first time, the logic stack 304 may automatically recognize and record the identifier (cpu _ id) carried in the resource request, and store the resource request in the logic stack. If the logical stack 304 subsequently receives the resource request sent by the same processor core again, the resource request may be directly discarded, and an exception notification message is sent to the same processor core, where the exception notification message is used to notify that the logical stack 304 cannot currently process the resource request.

The storage order of the resource requests in the logical stack 304 is not limited. Illustratively, the storage order of the resource requests in the logical stack 304 is related to the sequence in which the logical stack 304 receives the resource requests, and the specific implementation of the logical stack 304 storing the resource requests is not limited. For example, the logical stack 304 may be stored according to the time of receipt of each resource request, illustratively the earliest received resource request may be stored preferentially in the logical stack 304 and the latest received resource request may be stored last in the logical stack 304. Alternatively, the logical stack 304 may store the resource requests according to their priorities, such as the resource request with the higher priority being stored first in the logical stack 304 and the resource request with the lower priority being stored second. Alternatively, the logical stack 304 may store the resource requests according to the service levels of the resource requests, for example, the resource requests with higher service levels are preferentially stored in the logical stack 304, and then the resource requests with lower service levels are stored, which is not limited in this application.

In practical applications, the logic stack 304 may specifically include, but is not limited to, a first in first out unit (FIFO) logic stack, a last in first out unit (LIFO) logic stack, a low latency logic stack, a customized logic stack, and the like. In the application, the logic stack is taken as an FIFO logic stack as an example to explain relevant contents, wherein the design of the FIFO can ensure that the resource request which enters first in the logic stack 304 is preferentially popped out of the stack, thereby realizing fairness of polling and processing the resource request.

To ensure the logical nature of the processing of resource requests, the communication system (specifically, the logic stack 304 or the resource allocation logic 306) supports the processing of a single resource request in the same working clock cycle. Specifically, in the same working clock cycle, the logic stack 304 supports only pushing or popping of one resource request, and the resource allocation logic circuit 306 supports allocating a logic resource for one resource request. Where a working clock cycle refers to the period of time a single resource request needs to be processed to consume. Referring to fig. 4, a storage diagram of a logic stack 304 is shown. The logical stack 304 shown in fig. 4 stores resource requests of 4 CPUs, specifically, one resource request of each of the CPUs 1 to 4. In the same working clock cycle, the logic stack 304 only allows the resource request of one CPU to be pushed or popped, so as to implement the pushing storage or popping processing of the resource request.

The resource allocation logic 306 is configured to process a resource request in the logic stack 304, and allocate an available free resource for the resource request. Optionally, the resource allocation logic 306 is further configured to query whether there are free resources available in the k resources 310. Specifically, when the resource allocation logic 306 detects that the target resource request is popped from the logic stack 304, the resource allocation logic 306 may receive the popped target resource request in the logic stack 304, further may query whether there is an available idle resource currently, and if so, may use the queried idle resource as the target logic resource to be allocated to the target processor core that sent the target resource request.

In practical applications, the resource allocation logic 306 may be implemented by, for example, an application-specific integrated circuit (ASIC), or a Programmable Logic Device (PLD), which may be a Complex Programmable Logic Device (CPLD), a field-programmable gate array (FPGA), a General Array Logic (GAL), or a combination thereof. When the actual product is deployed, the resource allocation logic 306 is hardware logic independent of the m processor cores, that is, the resource allocation logic 306 can be deployed independently of the m processor cores.

Optionally, the resource request sent by the processor core may also carry attribute information of the processor core. The attribute information refers to information for describing attributes of the processor core, which may include, but is not limited to, an identification of the processor core, a type of service supported by the processor core, a quality of service (QOS) indicator, a service level or other attribute information, and the like, for example. The quality of service indicators include, but are not limited to, latency, throughput, loss rate, priority, or other indicators for affecting the quality of service communication. The service levels include, but are not limited to, QOS levels and class of service (COS) levels, which may also be referred to as QOS service levels and COS service levels for short. The QOS service level is mainly divided according to bandwidth or transmission time, for example, the larger the bandwidth required by the processor core during service communication, the higher the QOS service level of the processor core; conversely, the smaller the bandwidth required by the processor core for service communication, the lower the QOS service level of the processor core. The COS service level generally refers to the transmission priority of traffic, where, for example, the COS service level of a processor core may be the priority of data required to be transmitted while the processor core supports traffic.

Accordingly, after receiving the resource request sent by the processor core, the resource allocation logic 306 may allocate the idle resource matched with the resource request for the processor core according to the attribute information in the resource request. For example, when the attribute information is a service type supported by the processor core, after receiving the resource request, the resource allocation logic 306 may query whether there is an idle resource corresponding to a communication service supporting processing of the service type in the k resources 310, so as to be used by the processor core. When the attribute information is other attribute information of the processor core, the resource allocation logic 306 may query whether there is an idle resource satisfying the requirement of the other attribute information in the k resources 310 for the processor core to use after receiving the resource request.

The protection lock 308 is used to protect the resource 310, and is specifically used to lock the resource 310, for example, to lock a communication entry accessing the resource. The number of the dongle 308 is not limited, and a particular same dongle may be used to lock one or more resources 310, and each resource 310 may be protected using one dongle 308. The illustration takes k resources 310 as an example for performing locking protection on k application protectors 308, where the resources 310 and the protectors 308 are in a one-to-one correspondence, that is, one resource locks one protector.

In practical applications, the dongle 308 may be a software lock or a hardware lock. Wherein the software lock is implemented by software or program code. The hardware lock may be implemented by a hardware logic circuit, a dedicated hardware integrated circuit, or a hardened hardware core, etc.

The resource 310 is a resource provided by the communication system 300 for the m processor cores, and the resource may be a hardware logic resource, or a data resource, without limitation. The number of the resources is not limited, and may be one or more, and k resources are illustrated as an example in the figure, and each resource needs a protection lock for security protection. In practical applications, when the resource allocation logic 306 receives a resource request sent by the processor core, it may query whether there is an unused or unoccupied idle resource from the k resources. If the idle resource is found, the resource allocation logic 306 may automatically issue a lock preemption command to preempt the corresponding protection lock of the idle resource. The protection lock is convenient for unlocking the idle resources subsequently, so that the processor core corresponding to the resource request can use the unlocked idle resources. In other words, the processor core may access and use the free resources based on the dongle.

Optionally, resource allocation logic 306 may also send a result of the preempting to the processor core in an interrupt response after preempting the dongle to notify that the dongle has been successfully preempted currently. Optionally, after the resource allocation logic 306 processes the resource request sent by the processor core, the resource allocation logic 306 may also send a resource response to the processor core, where the resource response is used to notify whether the idle resource (or the corresponding dongle for the idle resource) is currently successfully preempted. Specifically, when the resource allocation logic circuit 306 queries that there is an idle resource corresponding to the resource request, the resource allocation logic circuit 306 may return a first resource response to the processor core in an interrupt manner, where the first resource response is used to notify that the idle resource is successfully preempted currently, and optionally, may also be used to notify that a corresponding dongle is successfully preempted currently to the idle resource. When the resource allocation logic 306 does not inquire that there is an idle resource corresponding to the resource request, the resource allocation logic 306 may end the process; or returning a second resource response to the processor core in an interrupt mode, wherein the second resource response is used for notifying that the idle resource cannot be preempted successfully currently and waiting for next re-preemption.

In practical applications, any one or more of the m processor cores 302 may be deployed individually or in the same device. For example, taking the individual deployment of m processor cores as an example, the m processor cores may be respectively and correspondingly deployed in m host devices, and one processor core is deployed in each host device. Taking the example that at least two processing cores of the m processor cores are deployed together, the at least two processor cores may be deployed in the same host device. The host device includes, but is not limited to, a processor CPU, a controller, a mobile phone, a tablet computer (tablet personal computer), a Personal Digital Assistant (PDA), a Mobile Internet Device (MID), a wearable device (wearable device), a vehicle-mounted device, and other devices supporting network communication.

The logic stack 304 and the resource allocation logic 306 may be deployed in the same device, specifically, in the same device as the processor core, or in another device different from the processor core. Illustratively, taking the example that the logic stack 304 and the resource allocation logic 306 are deployed in a slave device other than m processor cores, the logic stack 304 and the resource allocation logic 306 may be deployed in a slave device, and the slave device includes, but is not limited to, a mobile phone, a tablet computer (tablet personal computer), a Personal Digital Assistant (PDA), a Mobile Internet Device (MID), a wearable device (wearable device), a vehicle-mounted device, and other devices supporting network communication.

Dongle 308 and resource 310 may be deployed in the same device, which may be a device different from the device deployed in logic stack 304 and resource allocation logic 306, or may be deployed in the same device deployed in logic stack 304 and resource allocation logic 306, and the invention is not limited thereto. Illustratively, the dongle 308 and the resource 310 may be deployed in the above slave device, and particularly, refer to fig. 5 to illustrate another communication system of the present invention. The communication system shown in fig. 5 includes m host devices 502 and slave devices 504, where each host device 502 has one processor core 302 deployed therein, and each slave device 404 has a logic stack 304, a resource allocation logic circuit 306, k locks 308, and k resources 310 deployed therein, and for each hardware or component deployed therein, reference may be specifically made to the relevant explanation in the embodiment shown in fig. 3, which is not described herein again.

Based on the foregoing embodiments, specific embodiments of the present invention relating to resource acquisition are set forth below. Fig. 6 is a schematic flow chart illustrating a resource obtaining method according to an embodiment of the present invention. The method as shown in fig. 6 may comprise the following implementation steps:

in step S602, the processor core 302 sends a resource request to the logical stack 304, where the resource request is used to request a logical resource for the processor core 302. Accordingly, the logical stack 304 receives the resource request.

In this application, any processor core 302 of the m processor cores may send a resource request when there is a resource usage requirement. For example, when a certain application program needs to use logic resources, a resource request can be sent by a processor core CPU where the application program is operated, and after the resource request is sent, the control right or the occupation right of the processor core CPU can be automatically released, so that the occupation of the application program on the CPU is reduced, and the utilization rate of the CPU is improved.

Step S604, the logical stack 304 receives at least one resource request and stores the at least one resource request in the logical stack 304. Each resource request is sent by one processor core, and the resource requests and the processor cores are in one-to-one correspondence.

The logical stack 304 may receive a resource request sent by any of the m processor cores. Similarly, when there are multiple processor cores in the m processor cores to send resource requests, the logic stack 304 may receive at least one resource request sent by at least one of the m processor cores, where each resource request is sent by one processor core, and the same processor core may send one or more resource requests. Further, the logical stack 304 may deposit the received at least one resource request into the logical stack 304. The invention is not limited with respect to the specific embodiment in which the resource request is stored in the logical stack 304.

For example, after the logical stack 304 receives the resource request sent by any processor core 302, the resource request of any processor core 302 may be stored in the logical stack 304 according to a preset storage rule. The preset storage rule is set by the system in a self-defined manner and is used for determining information such as a storage location and a storage order of the resource request in the logical stack 304, for example, the preset storage rule may be a receiving time order of the resource request, or a priority order of transmission of the resource request, and the like.

For example, fig. 7 shows a specific storage diagram of the logic stack 304. As shown in fig. 7, for example, 4 processor Cores (CPUs) send a resource request, and the four CPUs are CPU1 to CPU 4. The sequence of the four CPU resource requests is as follows: CPU1, CPU3, CPU4, and CPU 2. Accordingly, the logic stack 304 may store the resource requests of the four CPUs in the logic stack 304 according to the sequence of the resource request receiving times. For example, the logical stack 304 receives the resource request of the CPU1 first, and writes the resource request of the CPU1 into the logical stack 304 for storage; then, when receiving the resource request of the CPU3, the logic stack 304 writes the resource request of the CPU3 into the logic stack 304 for storage, and so on, the logic stack 304 finally receives the resource request of the CPU2, and writes the resource request of the CPU2 into the logic stack 304 for storage.

Optionally, any resource request carries an identifier, where the identifier is used to indicate a processor core to which the resource request belongs, that is, a processor core that sends the resource request. After the logical stack 304 receives any resource request, the identifier carried in the resource request can be obtained by parsing the resource request. And further determine whether to store the resource request in the logic stack 304 according to the identifier carried by the resource request. Specifically, when the storage capacity of the logic stack 304 supports storing m resource requests, after the logic stack 304 identifies the identifier carried in the resource request, only one resource request with the identifier is allowed to be stored in the logic stack 304. If a resource request for the identification is already stored in the logical stack 304, the received resource request may be discarded directly at this time, and an exception message may be sent to the processor core to which the resource request belongs to notify that the logical stack 304 cannot currently store or process the resource request. If any resource requests for the identification are not stored in the logical stack 304, the received resource request may be stored in the logical stack 304.

When the storage capacity of the logical stack 304 supports storing n resource requests, where n is greater than m, the logical stack 304 may determine whether to store the received resource request according to its own storage capacity, for example, if there is still enough storage capacity remaining in the logical stack 304 to support storing the received resource request, the received resource request may be stored in the logical stack 304. In this case, at least two resource requests stored in the logical stack 304 for a certain processor core (e.g., a first processor core) are supported, the first processor core being any one of the m processor cores.

In step S606, after the target resource request is popped from the logic stack 304, the resource allocation logic 306 allocates the target logic resource to the target resource request. In which only one resource request is allocated a logical resource in one working clock cycle, and the target resource request refers to the resource request with the highest priority located in the logical stack 304.

In this application, after the logic stack 304 stores any received resource request in the logic stack 304, the resource request in the logic stack 304 may be processed according to a preset mechanism. The default mechanism may be system-defined, such as a FIFO mechanism, and the logical stack 304 supports the push store and pop process of a resource request every operating clock cycle. The present application uses a target resource request in the logical stack 304 as an example for illustration, and the target resource request may be a resource request with the highest priority in the logical stack 304. Specifically, when a target resource request is popped from the logical stack 304, the resource allocation logic 306 may allocate a target logical resource for the target resource request for use by the target processor core that sent the target resource request.

In a specific implementation, the logic stack 304 may perform pop processing on the target resource request according to a preset rule, so as to send the target resource request to the resource allocation logic 306 for processing. Accordingly, after receiving the target resource request, the resource allocation logic 306 may query whether there are idle resources for the target processor core in response to the target resource request, and the specific resource allocation logic 306 may query whether there are idle resources from the k resources 310, where the idle resources are resources that are not used or are not preempted. If there are free resources, the resource allocation logic 306 may allocate the free resources to the target processor core as the target logical resource.

Optionally, the resource referred to in this application may refer to a resource that meets requirements of different communication services. After receiving the target resource request, the resource allocation logic 306 needs to allocate a corresponding target logic resource to the target processor core according to the actual service requirement of the target processor core. Illustratively, the target resource request carries attribute information of the target processor core, where the attribute information is information for describing an attribute of the target processor core, and may include, but is not limited to, information such as a quality of service QOS indicator, a QOS service level, a COS service level, an identifier, and a service type. After receiving the target resource request, the resource allocation logic 306 may respond to the target resource request to query whether there is an idle resource matching the attribute information of the target processor core. If so, the resource allocation logic 306 may allocate the free resources as target logical resources for use by the target processor core. If not, the resource allocation logic 306 may end the flow; alternatively, a notification message is sent to the target processor core, where the notification message is used to notify the resource allocation logic 306 that the target processor core cannot be allocated the target logical resource currently, and that no free resources are available.

For example, the attribute information of the target processor core is taken as the network delay of 100 ms. After the resource allocation logic 306 receives the resource request sent by the target processor core, the network delay is 100ms carried in the resource request of the target processor core. The resource allocation logic 306 may respond to the resource request, query whether there is an idle resource within 100ms of network latency supporting processing of the communication service currently, and if there is an idle resource, allocate the idle resource to the target processor core, that is, the idle resource is used as the target logic resource allocated by the resource allocation logic 306 to the target processor core.

Optionally, the resource allocation logic 306 may send a resource response to the target processor core after responding to the target resource request, where the resource response may be used to notify whether the target processor core has been successfully preempted or allocated the target logical resource.

Step S608, the resource allocation logic 306 automatically preempts a target protection lock corresponding to the target logic resource according to the target resource request, wherein the target processor core accesses the target logic resource based on the target protection lock, and the target processor core refers to a processor core that sends the target resource request.

Step S610, the resource allocation logic 306 reports a lock snatching result to the target processor core in response to the interrupt, where the lock snatching result is used to indicate that the target protection lock is successfully preempted.

In order to improve the processing efficiency of resource acquisition, the resource allocation logic circuit 306 may also automatically preempt the target protection lock corresponding to the target logic resource after allocating the target logic resource to the target processor core, so that the target processor core can access the target logic resource based on the target protection lock, and then use the target logic resource. Further, the resource allocation logic 306 may report a pre-lock result to the target processor core in response to the interrupt, the pre-lock result indicating successful preemption of the target dongle.

And step S612, the target processor core receives the lock robbing result and obtains a target protection lock according to the lock robbing result so as to access and use the target logic resource based on the target protection lock.

The target processor core receives the result of the lock preemption reported by the resource allocation logic 306, and further reads the target protection lock indicated by the result of the lock preemption from a preset register based on the result of the lock preemption, and accesses the target logic resource based on the target protection lock to use the target logic resource. In other words, after receiving the result of the preempting lock, the target processor core may directly utilize the target dongle to access and use the target logic resource, and there is no need to configure a command for preempting the dongle through the target processor core (e.g., CPU) to preempt the dongle as in the conventional technique. Compared with the traditional technology, the method can greatly simplify the resource acquisition process, save time, reduce occupation of the CPU and improve the utilization rate of the CPU.

Optionally, during the process that the target processor core uses the target logic resource, the target processor core may update the state of the target logic resource, for example, update the state of the target logic resource to occupied, which indicates that the target logic resource is currently being used and is in an occupied state. When the target processor core finishes using the target logic resource, the target logic resource can be released, and the state of the target processor is updated to be idle, which indicates that the target logic resource is not used and is in an idle state.

In consideration of application scenarios of resource request withdrawal, such as scenarios of misoperation or temporary non-request of idle resources for the host device, the present application proposes another flow of resource acquisition method. Please refer to fig. 8, which illustrates a resource obtaining method, comprising the following steps:

at step S802, the processor core 302 sends an undo command for a first resource request to the logical stack 304, where the first resource request is any one of the at least one resource request. Accordingly, the logical stack 304 receives an undo command for the first resource request.

In this application, after any one of the m processor cores sends a corresponding resource request, if the processor core does not want to apply for a logical resource for the processor core any more, the processor core may send a revoke command to the logical stack 304, where the revoke command is used to request to revoke the resource request of the processor core, that is, to revoke the processing of the resource request of the processor core by the logical stack 304. The present application takes the first resource request as an example for detailed description of relevant contents. Specifically, after the processor core 302 to which the first resource request belongs sends the first resource request, the processor core wants to temporarily cancel the processing of the first resource request due to a special reason, and in order to implement the temporary cancellation of the first resource request, the present invention adds a new queue popping mechanism in the logic stack 304, where the queue popping mechanism can only be initiated by a cancel command for the first resource request. For example, when the processor core 302 to which the first resource request belongs wants to revoke the first resource request, a revoke command for the first resource request may be sent to the logical stack 304. Accordingly, the logical stack 304 may receive the undo command, and the first resource request may be any one of at least one resource request sent by the m processor cores. And deleting the resource request corresponding to the undo command according to the undo command, and inserting and queuing the resource request out of the stack regardless of the storage sequence of the resource request in the logic stack.

Step S804, the logical stack 304 performs queue insertion and stack removal processing on the first resource request stored in the logical stack 304 according to the undo command, so as to delete the first resource request.

In step S806, after deleting the first resource request, the resource allocation logic 306 may report the cancel result to the processor core 302 corresponding to the first resource request through an interrupt response. Wherein the retraction result is used to indicate that the logical stack 304 has completed the retraction of the first resource request.

After receiving the undo command, the logical stack 304 may perform a dequeuing on the first resource request stored in the logical stack 304 in response to the undo command, so as to delete the first resource request from the logical stack 304, so as to stop performing the allocation processing of the logical resource on the first resource request. Alternatively, after deleting the first resource request, the resource allocation logic 306 may report a revocation result to the processor core to which the first resource request belongs via an interrupt response, wherein the revocation result indicates that the logical stack 304 has successfully completed the revocation of the first resource request.

For example, referring to the example described in FIG. 7, assume that after CPU3 sends the resource request of CPU3, it wants to temporarily revoke the resource request of CPU 3. The CPU3 may send a CPU3 undo command to the logical stack 304 requesting that the resource request of the CPU3 be undone, the logical stack 304 is not processing the resource request of the CPU 3. Accordingly, after receiving the undo command of the CPU3, the logic stack 304 needs to update the resource requests of the 4 CPUs stored in the logic stack 304, to perform queue-inserting and unstacking on the resource request of the CPU3, and delete and undo the resource request of the CPU3, which may be specifically shown in fig. 9 as a schematic diagram of queue-inserting and unstacking of the logic stack 304.

By implementing the embodiment of the invention, the problems that in the prior art, a certain CPU is difficult to seize resources in the process of seizing the resources by multiple threads of the multiple CPUs, so that the normal service communication and service performance of the CPU are influenced and the like can be solved. The invention adopts the logic stack to process the resource request of each CPU in the stack one by one, so as to ensure the fairness and rationality of CPU resource occupation and avoid the problems that some CPUs are difficult to occupy the resources in the traditional technology.

The following describes the related apparatus and system according to the present invention, in conjunction with the related explanations in the embodiments described in fig. 1-9. Fig. 10 is a schematic structural diagram of a communication device 1000 according to an embodiment of the present invention. The communications apparatus 1000 as shown in fig. 10 includes a logic stack 1004 and resource allocation logic 1006. Optionally, the communication device may further include processor cores 1002, and the number of the processor cores 1002 is not limited, and may be one or more. Wherein:

the logic stack 1004 is configured to receive at least one resource request and store the at least one resource request in the logic stack 1004, where each resource request is sent by a processor core 1002, the resource requests are in one-to-one correspondence with the processor cores, and the resource requests are used to request logic resources for the corresponding processor cores;

the resource allocation logic 1006 is configured to allocate a target logic resource for a target resource request, and allocate a logic resource for only one resource request in one working clock cycle, where the target resource request is the resource request located in the logic stack 1004 and having the highest priority.

In some possible embodiments, the resource allocation logic 1006 is specifically configured to query whether there are free resources for the target processor core after receiving the target resource request; and when inquiring that idle resources exist, allocating the idle resources to a target processor core as the target logic resources, wherein the target processor core is the processor core which sends the target resource request.

In some possible embodiments, after the resource allocation logic 1006 allocates the idle resource as the target logical resource to a target processor core, the resource allocation logic 1006 is further configured to automatically preempt a target dongle corresponding to the target logical resource according to the target resource request, wherein the target processor core accesses the target logical resource based on the target dongle; reporting a rob lock result to the target processor core through an interrupt response, wherein the rob lock result is used for indicating that the target protection lock is successfully robed.

In some possible embodiments, each resource request carries an identifier, where the identifier is used to indicate a processor core to which the corresponding resource request belongs, and the logic stack 1004 is further configured to determine, after receiving one resource request, the identifier carried in the resource request; and determining whether to store the resource request into the logic stack according to the identifier carried by the resource request.

In some possible embodiments, the storage capacity of the logical stack 1004 supports storing n resource requests, the total number of processor cores is m, and n ═ m, then the logical stack 1004 allows only one resource request of each of the m processor cores to be stored in the logical stack 1004.

In some possible embodiments, the storage capacity of the logical stack 1004 supports storing m resource requests, and the total number of processor cores is m, then the logical stack 1004 allows only one resource request of the resource requests with the same identifier to be stored in the logical stack.

In some possible embodiments, the storage capacity of the logical stack 1004 supports storing n resource requests, the total number of processor cores is m, and n is greater than m, then the logical stack 1004 allows at least two resource requests of a first processor core to be stored in the logical stack, the first processor core being any one of the m processor cores.

In some possible embodiments, the logical stack 1004 is a first-in-first-out unit FIFO logical stack.

In some possible embodiments, the resource allocation logic 1006 is independent of the processor core 1002.

In some possible embodiments, the processor core 1002 is deployed in the communication device 1000.

In some possible embodiments, the logical stack 1004 is further configured to receive an undo command for a first resource request, the first resource request being any of the at least one resource request; and deleting the first resource request stored in the logic stack according to the withdrawal command.

In some possible embodiments, after deleting the first resource request, the resource allocation logic 1006 is further configured to report an undo result to a processor core corresponding to the first resource request through an interrupt response, wherein the undo result is used to indicate that the logical stack has completed the undo of the first resource request.

In practical applications, the components related to the communication device in the embodiments of the present invention may be implemented by hardware, for example, it may be implemented by an application-specific integrated circuit (ASIC), or a Programmable Logic Device (PLD), where the PLD may be a Complex Programmable Logic Device (CPLD), a field-programmable gate array (FPGA), a General Array Logic (GAL), or any combination thereof, and the present invention is not limited thereto.

It should be noted that fig. 10 is only one possible implementation manner of the embodiment of the present application, and in practical applications, the communication apparatus may further include more or less components, which is not limited herein. For the content that is not shown or described in the embodiment of the present invention, reference may be made to the relevant explanation in the foregoing method embodiment, which is not described herein again.

By implementing the embodiment of the invention, the problems that a certain CPU is difficult to seize resources in the prior art, so that the normal service communication and service performance of the CPU are influenced and the like can be solved.

Fig. 11 is a schematic structural diagram of a communication device according to an embodiment of the present invention. The communication device 110 as shown in fig. 11 includes one or more processors 1101, a communication interface 1102, and memory 1103. The processor 1101 is disposed with a logic stack and a resource allocation logic circuit. Optionally, any one or more processor cores (not shown) of the m processor cores may also be disposed in the processor 1101, and in practical applications, the processor cores may also be disposed outside the processor 1101, without limitation. The processor 1101, the communication interface 1102 and the memory 1103 may be connected by a bus, or may realize communication by other means such as wireless transmission. The embodiment of the present invention is exemplified by being connected through a bus 1104, wherein the memory 1103 is used for storing instructions, and the processor 1101 is used for executing the instructions stored by the memory 1103. The memory 1103 stores program codes, and the processor 1101 may call the program codes stored in the memory 1103 to implement the implementation steps in the embodiment of the method shown in fig. 1 to 9 and/or other contents described in the text, which are not described herein again.

Alternatively, processor 1101 may be comprised of one or more general purpose processors, such as a controller, Central Processing Unit (CPU). The processor 1101 is configured to execute relevant program codes by calling relevant hardware disposed to implement relevant descriptions in the embodiments shown in fig. 1 to fig. 9, which are not described herein again.

It is to be understood that the communication interface 1102 may be a wired interface (e.g., an ethernet interface) or a wireless interface (e.g., a wireless fidelity (WiFi) interface) for communicating with other modules or equipment devices. For example, in this embodiment of the application, the communication interface 1102 may be specifically configured to receive a resource request sent by a processor core, and the like.

The Memory 1103 may include a Volatile Memory (Volatile Memory), such as a Random Access Memory (RAM); the Memory may also include a Non-Volatile Memory (Non-Volatile Memory), such as a Read-Only Memory (ROM), a Flash Memory (Flash Memory), a Hard Disk (Hard Disk Drive, HDD), or a Solid-State Drive (SSD); the memory 1103 may also comprise a combination of memories of the kind described above. The memory may be configured to store a set of program code to facilitate the processor in invoking the program code stored in the memory to implement the associated steps involved in embodiments of the present invention.

It should be noted that fig. 11 is only one possible implementation manner of the embodiment of the present application, and in practical applications, the communication device may further include more or less components, which is not limited herein. For the content that is not shown or described in the embodiment of the present invention, reference may be made to the relevant explanation in the foregoing method embodiment, which is not described herein again.

The embodiment of the invention also provides a communication system which comprises m processor cores, a logic stack and a resource allocation logic circuit. Optionally, a dongle and resources may also be included. When the processor core is deployed in the master device and the logic stack, the resource allocation logic circuit, the dongle and the resources are deployed in the slave device, the communication system may specifically include m master devices and m slave devices. For the relevant explanation of the communication system, reference may be specifically made to the relevant explanation in the embodiment described in fig. 1, and details are not described here.

Embodiments of the present invention also provide a computer-readable storage medium, which stores instructions and implements the method flows shown in fig. 6 or fig. 8 when the computer-readable storage medium is run on a communication device.

Embodiments of the present invention also provide a computer program product, where when the computer program product runs on a communication device, the method flow shown in the embodiment of fig. 6 or fig. 8 is implemented.

The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied in hardware or in software executed by a processor. The software instructions may be comprised of corresponding software modules that may be stored in a Random Access Memory (RAM), a flash Memory, a Read Only Memory (ROM), an Erasable Programmable ROM (EPROM), an Electrically Erasable Programmable ROM (EEPROM), a register, a hard disk, a removable hard disk, a compact disc Read Only Memory (CD-ROM), or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. Of course, the storage medium may also be integral to the processor. The processor and the storage medium may reside in an ASIC. Additionally, the ASIC may reside in a communications device. Of course, the processor and the storage medium may reside as discrete components in a communication apparatus.

It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. And the aforementioned storage medium includes: various media that can store program codes, such as ROM, RAM, magnetic or optical disks.

Claims

A method for resource acquisition, the method comprising:

receiving at least one resource request, and storing the at least one resource request to a logic stack, wherein each resource request is sent by one processor core, the resource requests are in one-to-one correspondence with the processor cores, and the resource requests are used for requesting logic resources for the corresponding processor cores;

and allocating target logic resources for target resource requests, and allocating logic resources for only one resource request in one working clock cycle, wherein the target resource requests refer to resource requests which are located in the logic stack and have the highest priority.
The method of claim 1, wherein allocating the logical resource for the target resource request comprises:

after receiving the target resource request, inquiring whether idle resources for the target processor core exist;

and when inquiring that idle resources exist, allocating the idle resources to the target processor core as the target logic resources, wherein the target processor core is the processor core which sends the target resource request.
The method of claim 2, wherein after allocating the free resources as the target logical resources to the target processor core, the method further comprises:

automatically preempting a target protection lock corresponding to the target logic resource according to the target resource request, wherein the target processor core accesses the target logic resource based on the target protection lock;

reporting a rob lock result to the target processor core through an interrupt response, wherein the rob lock result is used for indicating that the target protection lock is successfully robed.
The method according to any one of claims 1 to 3, wherein each resource request carries an identifier for indicating a processor core to which the corresponding resource request belongs, the method further comprising:

after receiving a resource request, determining an identifier carried in the resource request;

and determining whether to store the resource request into the logic stack according to the identifier carried by the resource request.
The method of any of claims 1-4, wherein the storage capacity of the logical stack supports storing n resource requests, wherein the total number of processor cores is m, and wherein n ═ m, then the logical stack allows only one resource request per processor core of the m processor cores to be stored in the logical stack.
The method of claim 4, wherein the storage capacity of the logical stack supports storing m resource requests, and wherein the total number of processor cores is m, and wherein the logical stack allows only one resource request of the plurality of resource requests having the same identity to be stored in the logical stack.
The method as claimed in any one of claims 1 to 4, wherein the storage capacity of the logical stack supports storing n resource requests, the total number of processor cores is m, and n > m, then the logical stack allows at least two resource requests of a first processor core to be stored in the logical stack, the first processor core being any one of the m processor cores.
The method of any of claims 1-7, wherein the logical stack is a first-in-first-out unit (FIFO) logical stack.
The method according to any one of claims 1-8, further comprising:

receiving a revoke command for a first resource request, the first resource request being any of the at least one resource request;

and deleting the first resource request stored in the logic stack according to the withdrawal command.
The method of claim 9, wherein after deleting the first resource request, the method further comprises:

reporting a revocation result to a processor core corresponding to the first resource request through an interrupt response, wherein the revocation result is used for indicating that the logical stack completes revocation of the first resource request.
A communication apparatus comprising a logic stack and resource allocation logic, wherein,

the logic stack is used for receiving at least one resource request and storing the at least one resource request to the logic stack, wherein each resource request is sent by a processor core, the resource requests are in one-to-one correspondence with the processor cores, and the resource requests are used for requesting logic resources for the corresponding processor cores;

the resource allocation logic circuit is configured to allocate a target logic resource for a target resource request, and allocate a logic resource for only one resource request in one working clock cycle, where the target resource request is a resource request located in the logic stack and having the highest priority.
The apparatus of claim 11, wherein the resource allocation logic is specifically configured to:

after receiving the target resource request, inquiring whether idle resources for the target processor core exist;

and when inquiring that idle resources exist, allocating the idle resources to a target processor core as the target logic resources, wherein the target processor core is the processor core which sends the target resource request.
The apparatus of claim 12, wherein after the resource allocation logic allocates the free resource as the target logical resource to a target processor core, the resource allocation logic is further to:

automatically preempting a target protection lock corresponding to the target logic resource according to the target resource request, wherein the target processor core accesses the target logic resource based on the target protection lock;

reporting a rob lock result to the target processor core through an interrupt response, wherein the rob lock result is used for indicating that the target protection lock is successfully robed.
The apparatus as claimed in any one of claims 11 to 13, wherein each resource request carries an identifier, the identifier being used to indicate a processor core to which the corresponding resource request belongs, and the logic stack is further configured to:

after receiving a resource request, determining an identifier carried in the resource request;

and determining whether to store the resource request into the logic stack according to the identifier carried by the resource request.
The apparatus as claimed in any one of claims 11-14, wherein the storage capacity of the logical stack supports storing n resource requests, wherein the total number of processor cores is m, and n ═ m, then the logical stack allows only one resource request per processor core of the m processor cores to be stored in the logical stack.
The apparatus as in any of claims 11-14, wherein the storage capacity of the logical stack supports storing m resource requests and wherein the total number of processor cores is m, and wherein the logical stack allows only one resource request of the plurality of resource requests having the same identity to be stored in the logical stack.
The apparatus of any of claims 11-14, wherein the storage capacity of the logical stack supports storing n resource requests, wherein the total number of processor cores is m, and wherein n is greater than m, then the logical stack allows at least two resource requests of a first processor core to be stored in the logical stack, wherein the first processor core is any one of the m processor cores.
The apparatus of any of claims 11-17, wherein the logical stack is a first-in-first-out unit (FIFO) logical stack.
The apparatus of any of claims 11-18, wherein the resource allocation logic is independent of the processor core.
The apparatus according to any one of claims 11-19, further comprising: a plurality of the processor cores.
The apparatus of any of claims 11-20, wherein the logical stack is further configured to:

receiving a revoke command for a first resource request, the first resource request being any of the at least one resource request;

and deleting the first resource request stored in the logic stack according to the withdrawal command.
The apparatus as claimed in claim 21, wherein said logic stack, after deleting said first resource request, said resource allocation logic circuitry is configured to:

reporting a revocation result to a processor core corresponding to the first resource request through an interrupt response, wherein the revocation result is used for indicating that the logical stack completes revocation of the first resource request.