CN113765504B - Universal dynamic delay jitter elimination method, device, terminal and storage medium - Google Patents
Universal dynamic delay jitter elimination method, device, terminal and storage medium Download PDFInfo
- Publication number
- CN113765504B CN113765504B CN202110865847.6A CN202110865847A CN113765504B CN 113765504 B CN113765504 B CN 113765504B CN 202110865847 A CN202110865847 A CN 202110865847A CN 113765504 B CN113765504 B CN 113765504B
- Authority
- CN
- China
- Prior art keywords
- delay
- delay time
- false
- jitter
- elimination
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000003379 elimination reaction Methods 0.000 title claims abstract description 202
- 230000008030 elimination Effects 0.000 title claims abstract description 177
- 238000000034 method Methods 0.000 title claims abstract description 51
- 230000008569 process Effects 0.000 claims description 17
- 238000001514 detection method Methods 0.000 claims description 12
- 238000010586 diagram Methods 0.000 description 7
- 238000004891 communication Methods 0.000 description 6
- 230000009467 reduction Effects 0.000 description 5
- 230000008859 change Effects 0.000 description 4
- 230000006870 function Effects 0.000 description 4
- 230000007704 transition Effects 0.000 description 4
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- 206010044565 Tremor Diseases 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 2
- 230000009471 action Effects 0.000 description 2
- 230000003111 delayed effect Effects 0.000 description 2
- 230000002035 prolonged effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/125—Discriminating pulses
- H03K5/1252—Suppression or limitation of noise or interference
- H03K5/1254—Suppression or limitation of noise or interference specially adapted for pulses generated by closure of switches, i.e. anti-bouncing devices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Studio Devices (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
Abstract
The application discloses a general dynamic delay jitter elimination method, a device, a terminal and a storage medium, and the method, the device, the terminal and the storage medium are used for detecting whether an operation is a false operation or not; when the false operation is detected, recording the number of false operations; and adjusting the jitter elimination delay time of the next operation according to the recorded false operation times, and performing jitter elimination processing based on the adjusted jitter elimination delay time in the next operation. The application can adjust the jitter elimination delay time according to the false operation times, so that the jitter elimination delay time is more reasonable, the judgment of a plurality of times is avoided, and the judgment accuracy is ensured; meanwhile, one jitter elimination module can be used for adapting to different application scenes, and the workload of developers is reduced.
Description
Technical Field
The application relates to the field of delay jitter elimination, in particular to a method, a device, a terminal and a storage medium for universal dynamic delay jitter elimination.
Background
The anti-shake is generally used for a mechanical elastic switch or a hot plug connector, and when the mechanical switch is opened, closed or the connector performs plug action, the system cannot effectively judge the high/low level state of the signal, namely the metastable state, for a period of time before the state of the signal is stable due to the instability of the manual operation and the instability of contacts of the mechanical elastic switch/connector. Taking the connector as an example, when the connector is plugged in, the signal will not immediately stabilize, and at the moment of plugging in, a series of jitters will accompany, which will lead to erroneous judgment of the signal state by the system. In order to avoid this, i.e. to correctly identify the plugging action of the mechanical spring switch and the connector, the jitter of the signal has to be handled.
The state machine is generally used for eliminating jitter, when the state transition and delay are carried out when the new state is detected to be different from the old state, the new state is detected after the delay, if the state is still unchanged, the state change is determined to be effective change, and the old state is assigned to be the new state and is output to the system.
Taking key operation as an example: the key operation can be divided into 4 states, namely a key press operation S0, a key press operation S1, a stable press operation S2, and a key release operation S3. Assume that the level is 0 when the key is pressed and 1 when not pressed. A key initial state S0, which indicates that no key is pressed, and S0 is maintained; when the key is pressed, the state goes to the state S1.
First, the initial state of the key is S0, and when an input of 1 is detected, it means that no key is pressed, and S0 is held. When the key input is 0, the key is pressed, and after the delay time, if the input is detected to be still 0, the state S1 is shifted; after the state S1 is shifted, the input is still 0 after the delay time is passed, and the S2 is continuously shifted; similarly, after the state S2 is shifted, the input is still 0 after the delay time is elapsed, and the state S3 is shifted, that is, the fact that the key is pressed is indicated, and the message can be transmitted to the system. In this process, any state detects an input of 1, indicating that the key operation was just disturbed, and not actually a key operation, the state switches back to S0. In the S3 state, the input is detected as high, i.e., there is a key release operation, and the state switches back to S0.
In the state transition process of S1-S3, each state needs to be delayed, and the delay processing of jitter elimination is generally 10ms or 20ms. The choice of the delay time is very important, if the delay time is too short, the state machine needs to judge for many times; if the delay time is too long, the judgment efficiency is low. However, on one hand, the current delay time is generally determined empirically, and on the other hand, different application scenes have different jitter elimination requirements, and accordingly, the state machine needs to configure a jitter elimination module for each application scene, so that the workload of a developer is increased.
Disclosure of Invention
In order to solve the problems, the application provides a general dynamic delay jitter elimination method, a device, a terminal and a storage medium, which can dynamically adjust the jitter elimination delay time of each operation, and can be suitable for various application scenes by using one jitter elimination module.
In a first aspect, the present application provides a method for universal dynamic delay jitter elimination, comprising the steps of:
detecting whether the operation is a false operation;
when the false operation is detected, recording the number of false operations;
and adjusting the jitter elimination delay time of the next operation according to the recorded false operation times, and performing jitter elimination processing based on the adjusted jitter elimination delay time in the next operation.
Further, the jitter-elimination delay time of the next operation is adjusted according to the recorded false operation times, specifically, the jitter-elimination delay time of the next operation is calculated through the following formula:
delay n+1 =delay n + delay n *delaycounter/N；
wherein, delay n Delay time for the jitter elimination of the nth operation n+1 The delay time is the jitter elimination delay time of the n+1th operation, the delay is the recorded false operation times, and N is the number of states experienced in the operation process.
Further, the method comprises the following steps:
after the false operation is detected, when a normal operation is detected, the recorded number of false operations is cleared.
Further, the method comprises the following steps:
when the recorded false operation times are zero, the jitter elimination delay time of the next operation is set as the initial jitter elimination delay time.
In a second aspect, the present application provides a universal dynamic delay jitter reduction apparatus, comprising,
operation detection unit: detecting whether the operation is a false operation;
a false operation number recording unit: when the false operation is detected, recording the number of false operations;
jitter elimination delay time adjusting unit: and adjusting the jitter elimination delay time of the next operation according to the recorded false operation times.
Further, the jitter-elimination delay time adjusting unit adjusts the jitter-elimination delay time of the next operation according to the recorded false operation times, specifically, calculates the jitter-elimination delay time of the next operation through the following formula:
delay n+1 =delay n + delay n *delaycounter/N；
wherein, delay n Delay time for the jitter elimination of the nth operation n+1 The delay time is the jitter elimination delay time of the n+1th operation, the delay is the recorded false operation times, and N is the number of states experienced in the operation process.
Further, the device also comprises a device for detecting the position of the object,
a zero clearing unit for recording the false operation times: after the false operation is detected, when a normal operation is detected, the recorded number of false operations is cleared.
Further, the debounce delay time adjustment unit is further configured to set the debounce delay time of the next operation to be an initial debounce delay time when the recorded number of false operations clears zero.
In a third aspect, a technical solution of the present application provides a terminal, including:
the memory is used for storing a general dynamic delay jitter elimination program;
and the processor is used for realizing the steps of the universal dynamic delay jitter elimination method when executing the universal dynamic delay jitter elimination program.
In a fourth aspect, the present application provides a readable storage medium, where a general dynamic delay debounce program is stored, where the general dynamic delay debounce program, when executed by a processor, implements the steps of the general dynamic delay debounce method according to any one of the above claims.
Compared with the prior art, the general dynamic delay jitter elimination method, device, terminal and storage medium provided by the application have the following beneficial effects: recording the false operation times when the false operation is detected, adjusting the jitter elimination delay time of the next operation according to the recorded false operation times, and performing jitter elimination processing based on the adjusted jitter elimination delay time in the next operation. The application can adjust the jitter elimination delay time according to the false operation times, so that the jitter elimination delay time is more reasonable, the judgment of a plurality of times is avoided, and the judgment accuracy is ensured; meanwhile, one jitter elimination module can be used for adapting to different application scenes, and the workload of developers is reduced.
Drawings
For a clearer description of embodiments of the application or of the prior art, the drawings that are used in the description of the embodiments or of the prior art will be briefly described, it being apparent that the drawings in the description below are only some embodiments of the application, and that other drawings can be obtained from them without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a general dynamic delay jitter elimination method according to an embodiment of the application;
fig. 2 is a flow chart of a general dynamic delay jitter elimination method according to a second embodiment of the present application;
FIG. 3 is a flow chart of a general dynamic delay jitter elimination method according to a third embodiment of the present application;
fig. 4 is a schematic block diagram of a general dynamic delay jitter elimination device according to a fourth embodiment of the present application;
fig. 5 is a schematic block diagram of a general dynamic delay jitter reduction device according to a sixth embodiment of the present application;
fig. 6 is a schematic structural diagram of a terminal according to a seventh embodiment of the present application.
Detailed Description
In order to better understand the aspects of the present application, the present application will be described in further detail with reference to the accompanying drawings and detailed description. It will be apparent that the described embodiments are only some, but not all, embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
Example 1
In the scene that the mechanical elastic switch or the hot plug connector and the like need to remove the tremble, a state machine is generally used for completing the tremble removal, when the fact that a new state is different from an old state is detected, state transition is carried out, time delay is carried out, the fact that the new state is detected after the time delay is carried out, if the state is still unchanged, the state change is determined to be effective change, and the old state is assigned to be the new state and is output to a system.
Taking key operation as an example: the key operation can be divided into 4 states, namely a key press operation S0, a key press operation S1, a stable press operation S2, and a key release operation S3. Assume that the level is 0 when the key is pressed and 1 when not pressed. A key initial state S0, which indicates that no key is pressed, and S0 is maintained; when the key is pressed, the state goes to the state S1.
First, the initial state of the key is S0, and when an input of 1 is detected, it means that no key is pressed, and S0 is held. When the key input is 0, the key is pressed, and after the delay time, if the input is detected to be still 0, the state S1 is shifted; after the state S1 is shifted, the input is still 0 after the delay time is passed, and the S2 is continuously shifted; similarly, after the state S2 is shifted, the input is still 0 after the delay time is elapsed, and the state S3 is shifted, that is, the fact that the key is pressed is indicated, and the message can be transmitted to the system. In this process, any state detects an input of 1, indicating that the key operation was just disturbed, and not actually a key operation, the state switches back to S0. In the S3 state, the input is detected as high, i.e., there is a key release operation, and the state switches back to S0.
In the state transition process of S1-S3, each state needs to be delayed, and the delay processing of jitter elimination is generally 10ms or 20ms. The choice of the delay time is very important, if the delay time is too short, the state machine needs to judge for many times; if the delay time is too long, the judgment efficiency is low. However, on one hand, the current delay time is generally determined empirically, and on the other hand, different application scenes have different jitter elimination requirements, and accordingly, the state machine needs to configure a jitter elimination module for each application scene, so that the workload of a developer is increased.
Therefore, the present embodiment provides a general dynamic delay jitter elimination method, which can dynamically adjust jitter elimination delay time of each operation, and can be suitable for various application scenarios by using one jitter elimination module.
Fig. 1 is a flow chart of a general dynamic delay jitter elimination method according to the embodiment, which includes the following steps.
S101, detecting whether the operation is a false operation.
I.e. detecting whether the operation is a disturbing operation or a normal operation, a disturbing operation, i.e. a fake operation, for example a key operation, the time of which is detected after the state S1 after a delay time as an input becomes 1, the operation being a disturbing operation, i.e. a fake operation. If the state goes to S3, the operation is normal.
S102, when the fake operation is detected, recording the fake operation times.
Note that the number of pseudo operations recorded is the number of accumulation. For example, if the first operation is a false operation, the number of times of the false operation is recorded as 1, and if the second operation is still a false operation, the number of times of the false operation is recorded as 1, that is, the number of times of the false operation is recorded as 2.
S103, adjusting the jitter elimination delay time of the next operation according to the recorded false operation times, and performing jitter elimination processing based on the adjusted jitter elimination delay time in the next operation.
If the false operation is met, the jitter elimination delay time of the next operation is timely adjusted, the accuracy of the next judgment is improved, and false detection is avoided.
According to the universal dynamic delay jitter elimination method provided by the embodiment, when false operation is detected, the false operation times are recorded, the jitter elimination delay time of the next operation is adjusted according to the recorded false operation times, and jitter elimination processing is performed based on the adjusted jitter elimination delay time in the next operation. The application can adjust the jitter elimination delay time according to the false operation times, so that the jitter elimination delay time is more reasonable, the judgment of a plurality of times is avoided, and the judgment accuracy is ensured; meanwhile, one jitter elimination module can be used for adapting to different application scenes, and the workload of developers is reduced.
Example two
Considering that the probability that the next false operation still occurs is still relatively high after a certain detection of the false operation, the embodiment adjusts the jitter-elimination delay time of the next operation according to the recorded number of false operations, and the adjusted jitter-elimination delay time is prolonged before adjustment.
Specifically, the debounce delay time for the next operation is calculated by the following formula:
delay n+1 =delay n + delay n *delaycounter/N
wherein, delay n Delay time for the jitter elimination of the nth operation n+1 The delay time is the jitter elimination delay time of the n+1th operation, the delay is the recorded false operation times, and N is the number of states experienced in the operation process.
For example, the key operation is performed through four states S0, S1, S2, and S3, so N is 4 in the above formula during the key operation. Of course, in other scenarios, the value of N is adjusted according to the number of states experienced by a particular operational process.
It should be noted that an initial value of the debounce delay time, i.e. the debounce delay time delay of the first operation, needs to be preset before detection 1 。
Still taking the key operation as an example, if the first operation is a false operation, recording the number of false operations as 1, and further calculating the jitter-elimination delay time of the second operation 2 =delay 1 + delay 1 *1/4. If the second operation is still a false operation, recording the number of times of the false operation as 2, and further calculating the jitter-elimination delay time delay of the third operation 3 =delay 2 + delay 2 *2/4。
Fig. 2 is a flow chart of a general dynamic delay jitter elimination method according to the embodiment, which includes the following steps.
S201, detecting whether the operation is a false operation.
S202, when the fake operation is detected, recording the fake operation times.
S203, delay according to the formula n+1 =delay n + delay n * The delycounter/N calculates the debounce delay time for the next operation.
The general dynamic delay jitter elimination method provided by the embodiment records the false operation times when the false operation is detected, and based on the formula delay according to the recorded false operation times n+1 =delay n + delay n * The delycounter/N adjusts the jitter elimination delay time of the next operation, and the jitter elimination processing is carried out based on the adjusted jitter elimination delay time in the next operation. The application can adjust the jitter elimination delay time according to the false operation times, so that the jitter elimination delay time is more reasonable, the judgment of a plurality of times is avoided, and the judgment accuracy is ensured; meanwhile, one jitter elimination module can be used for adapting to different application scenes, and the workload of developers is reduced.
Example III
After the normal operation is detected, the probability of the next normal operation is larger, so that the recorded false operation times are cleared in time after the normal operation is detected, and the jitter elimination delay time of the next operation is correspondingly adjusted to be the initial jitter elimination delay time, namely, the recording of the false operation times and the adjustment of the jitter elimination delay time are carried out again.
Fig. 3 is a flow chart of a general dynamic delay jitter elimination method according to the embodiment, which includes the following steps.
S301, detecting whether the operation is a false operation.
S302, when the fake operation is detected, recording the fake operation times.
S303, delay according to the formula n+1 =delay n + delay n * The delycounter/N calculates the debounce delay time for the next operation.
Wherein, delay n Delay time for the jitter elimination of the nth operation n+1 The delay time is the jitter elimination delay time of the n+1th operation, the delay is the recorded false operation times, and N is the number of states experienced in the operation process.
S304, after the false operation is detected, when the normal operation is detected once, the recorded false operation times are cleared.
S305, when the recorded false operation times are zero, setting the jitter elimination delay time of the next operation as the initial jitter elimination delay time.
It should be noted that, except when the recorded number of false operations is zero, that is, when the previous false operation is changed to the normal operation of the previous time, the jitter-elimination delay time of the next operation is set to be the initial jitter-elimination delay time, otherwise, the jitter is eliminated according to the formula n+1 =delay n + delay n * The delycounter/N calculates the debounce delay time for the next operation.
The general dynamic delay jitter elimination method provided by the embodiment records the false operation times when the false operation is detected, and based on the formula delay according to the recorded false operation times n+1 =delay n + delay n * The delycounter/N adjusts the jitter elimination delay time of the next operation, and the jitter elimination processing is carried out based on the adjusted jitter elimination delay time in the next operation. In addition, after the false operation is changed into normal operation, the recorded false operation times are cleared in time, andthe jitter elimination delay time of the next operation is set as the initial jitter elimination delay time, so that the state detection efficiency is improved. The application can adjust the jitter elimination delay time according to the false operation times, so that the jitter elimination delay time is more reasonable, the judgment of a plurality of times is avoided, and the judgment accuracy is ensured; meanwhile, one jitter elimination module can be used for adapting to different application scenes, and the workload of developers is reduced.
Example IV
In order to solve the problems that the delay time is generally determined empirically and different application scenes have different jitter elimination requirements, and accordingly, a state machine needs to configure a jitter elimination module for each application scene and increase the workload of developers, the embodiment provides a universal dynamic delay jitter elimination device which can dynamically adjust the jitter elimination delay time of each operation and can be suitable for various application scenes by using one jitter elimination module.
Fig. 4 is a schematic block diagram of a general dynamic delay jitter reduction device according to the present embodiment, which includes the following functional units.
Operation detection unit 101: it is detected whether the operation is a false operation.
I.e. detecting whether the operation is a disturbing operation or a normal operation, a disturbing operation, i.e. a fake operation, for example a key operation, the time of which is detected after the state S1 after a delay time as an input becomes 1, the operation being a disturbing operation, i.e. a fake operation. If the state goes to S3, the operation is normal.
The dummy operation number recording unit 102: when a false operation is detected, the number of false operations is recorded.
Note that the number of pseudo operations recorded is the number of accumulation. For example, if the first operation is a false operation, the number of times of the false operation is recorded as 1, and if the second operation is still a false operation, the number of times of the false operation is recorded as 1, that is, the number of times of the false operation is recorded as 2.
Jitter-elimination delay time adjustment unit 103: and adjusting the jitter elimination delay time of the next operation according to the recorded false operation times.
The jitter elimination processing is performed based on the adjusted jitter elimination delay time in the next operation. When the false operation is met, the jitter elimination delay time of the next operation is timely adjusted, the accuracy of the next judgment is improved, and false detection is avoided.
The universal dynamic delay jitter elimination device provided by the embodiment records the false operation times when the false operation is detected, adjusts the jitter elimination delay time of the next operation according to the recorded false operation times, and performs jitter elimination processing based on the adjusted jitter elimination delay time in the next operation. The application can adjust the jitter elimination delay time according to the false operation times, so that the jitter elimination delay time is more reasonable, the judgment of a plurality of times is avoided, and the judgment accuracy is ensured; meanwhile, one jitter elimination module can be used for adapting to different application scenes, and the workload of developers is reduced.
Example five
Fig. 4 is a schematic block diagram of a general dynamic delay jitter reduction device according to the present embodiment, which includes the following functional units.
Operation detection unit 101: it is detected whether the operation is a false operation.
The dummy operation number recording unit 102: when a false operation is detected, the number of false operations is recorded.
Jitter-elimination delay time adjustment unit 103: and adjusting the jitter elimination delay time of the next operation according to the recorded false operation times.
Considering that the probability that the next false operation still occurs is still relatively high after a certain detection of the false operation, the embodiment adjusts the jitter-elimination delay time of the next operation according to the recorded number of false operations, and the adjusted jitter-elimination delay time is prolonged before adjustment.
Specifically, the debounce delay time adjustment unit 103 calculates the debounce delay time for the next operation by the following formula:
delay n+1 =delay n + delay n *delaycounter/N
wherein, delay n Delay time for the jitter elimination of the nth operation n+1 The delay time is the jitter elimination delay time of the n+1th operation, the delay is the recorded false operation times, and N is the number of states experienced in the operation process.
For example, the key operation is performed through four states S0, S1, S2, and S3, so N is 4 in the above formula during the key operation. Of course, in other scenarios, the value of N is adjusted according to the number of states experienced by a particular operational process.
It should be noted that an initial value of the debounce delay time, i.e. the debounce delay time delay of the first operation, needs to be preset before detection 1 。
Still taking the key operation as an example, if the first operation is a false operation, recording the number of false operations as 1, and further calculating the jitter-elimination delay time of the second operation 2 =delay 1 + delay 1 *1/4. If the second operation is still a false operation, recording the number of times of the false operation as 2, and further calculating the jitter-elimination delay time delay of the third operation 3 =delay 2 + delay 2 *2/4。
The general dynamic delay jitter elimination device provided in this embodiment records the number of false operations when the false operations are detected, and based on formula delay according to the recorded number of false operations n+1 =delay n + delay n * The delycounter/N adjusts the jitter elimination delay time of the next operation, and the jitter elimination processing is carried out based on the adjusted jitter elimination delay time in the next operation. The application can adjust the jitter elimination delay time according to the false operation times, so that the jitter elimination delay time is more reasonable, the judgment of a plurality of times is avoided, and the judgment accuracy is ensured; meanwhile, one jitter elimination module can be used for adapting to different application scenes, and the workload of developers is reduced.
Example six
After the normal operation is detected, the probability of the next normal operation is larger, so that the recorded false operation times are cleared in time after the normal operation is detected, and the jitter elimination delay time of the next operation is correspondingly adjusted to be the initial jitter elimination delay time, namely, the recording of the false operation times and the adjustment of the jitter elimination delay time are carried out again.
Fig. 5 is a schematic block diagram of a general dynamic delay jitter reduction device according to the present embodiment, which includes the following functional units.
Operation detection unit 101: it is detected whether the operation is a false operation.
The dummy operation number recording unit 102: when a false operation is detected, the number of false operations is recorded.
Jitter-elimination delay time adjustment unit 103: and adjusting the jitter elimination delay time of the next operation according to the recorded false operation times.
The record false operation number clearing unit 104: after the false operation is detected, when a normal operation is detected, the recorded number of false operations is cleared.
Wherein, the jitter-elimination delay time adjustment unit 103 calculates the jitter-elimination delay time of the next operation by the following formula:
delay n+1 =delay n + delay n *delaycounter/N
wherein, delay n Delay time for the jitter elimination of the nth operation n+1 The delay time is the jitter elimination delay time of the n+1th operation, the delay is the recorded false operation times, and N is the number of states experienced in the operation process.
In addition, the debounce delay time adjustment unit 103 is further configured to set the debounce delay time of the next operation as the initial debounce delay time when the recorded number of false operations clears zero.
It should be noted that, except when the recorded number of false operations is zero, that is, when the previous false operation is changed to the normal operation of the previous time, the jitter-elimination delay time of the next operation is set to be the initial jitter-elimination delay time, otherwise, the jitter is eliminated according to the formula n+1 =delay n + delay n * The delycounter/N calculates the debounce delay time for the next operation.
The general dynamic delay jitter elimination device provided in this embodiment records the number of false operations when the false operations are detected, and based on formula delay according to the recorded number of false operations n+1 =delay n + delay n * The delycounter/N adjusts the jitter elimination delay time of the next operation, and the jitter elimination processing is carried out based on the adjusted jitter elimination delay time in the next operation. In addition, after the false operation is changed into the normal operation, the recorded false operation times are cleared in time, and the jitter-elimination delay time of the next operation is set as the initial timeEliminating jitter and delaying time to raise state detecting efficiency. The application can adjust the jitter elimination delay time according to the false operation times, so that the jitter elimination delay time is more reasonable, the judgment of a plurality of times is avoided, and the judgment accuracy is ensured; meanwhile, one jitter elimination module can be used for adapting to different application scenes, and the workload of developers is reduced.
Example seven
Fig. 6 is a schematic structural diagram of a terminal device 600 according to an embodiment of the present application, including: processor 610, memory 620, and communication unit 630. The processor 610 is configured to implement the general dynamic delay debounce procedure stored in the memory 620 by:
detecting whether the operation is a false operation;
when the false operation is detected, recording the number of false operations;
and adjusting the jitter elimination delay time of the next operation according to the recorded false operation times, and performing jitter elimination processing based on the adjusted jitter elimination delay time in the next operation.
The universal dynamic delay jitter elimination method records the false operation times when the false operation is detected, adjusts the jitter elimination delay time of the next operation according to the recorded false operation times, and performs jitter elimination processing based on the adjusted jitter elimination delay time in the next operation. The application can adjust the jitter elimination delay time according to the false operation times, so that the jitter elimination delay time is more reasonable, the judgment of a plurality of times is avoided, and the judgment accuracy is ensured; meanwhile, one jitter elimination module can be used for adapting to different application scenes, and the workload of developers is reduced.
In some embodiments, the processor 610 may implement the general-purpose dynamic latency jitter elimination subroutine stored in the memory 620: the jitter elimination delay time of the next operation is calculated by the following formula: delay device n+1 =delay n + delay n * delaycounter/N; wherein, delay n Delay time for the jitter elimination of the nth operation n+1 The delay time is the jitter elimination delay time of the n+1th operation, the delay is the recorded false operation times, and N is the number of states experienced in the operation process.
In some embodiments, the processor 610 may implement the general-purpose dynamic latency jitter elimination subroutine stored in the memory 620: after the false operation is detected, when a normal operation is detected, the recorded number of false operations is cleared.
In some embodiments, the processor 610 may implement the general-purpose dynamic latency jitter elimination subroutine stored in the memory 620: when the recorded false operation times are zero, the jitter elimination delay time of the next operation is set as the initial jitter elimination delay time.
The terminal apparatus 600 may include: processor 610, memory 620, and communication unit 630. The components may communicate via one or more buses, and it will be appreciated by those skilled in the art that the configuration of the server as shown in the drawings is not limiting of the application, as it may be a bus-like structure, a star-like structure, or include more or fewer components than shown, or may be a combination of certain components or a different arrangement of components.
The memory 620 may be used to store instructions for execution by the processor 610, and the memory 620 may be implemented by any type of volatile or non-volatile memory terminal or combination thereof, such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk, or optical disk. The execution of the instructions in memory 620, when executed by processor 610, enables terminal 600 to perform some or all of the steps in the method embodiments described below.
The processor 610 is a control center of the storage terminal, connects various parts of the entire electronic terminal using various interfaces and lines, and performs various functions of the electronic terminal and/or processes data by running or executing software programs and/or units stored in the memory 620, and invoking data stored in the memory. The processor may be comprised of an integrated circuit (Integrated Circuit, simply referred to as an IC), for example, a single packaged IC, or may be comprised of a plurality of packaged ICs connected to the same function or different functions. For example, the processor 610 may include only a central processing unit (Central Processing Unit, simply CPU). In the embodiment of the application, the CPU can be a single operation core or can comprise multiple operation cores.
A communication unit 630, configured to establish a communication channel, so that the storage terminal can communicate with other terminals. Receiving user data sent by other terminals or sending the user data to other terminals.
Example eight
The present application also provides a computer storage medium in which a program may be stored, which program may include some or all of the steps in the embodiments provided by the present application when executed. The storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), a random-access memory (random access memory, RAM), or the like.
The computer storage medium stores a general dynamic delay debounce program which when executed by the processor performs the steps of:
detecting whether the operation is a false operation;
when the false operation is detected, recording the number of false operations;
and adjusting the jitter elimination delay time of the next operation according to the recorded false operation times, and performing jitter elimination processing based on the adjusted jitter elimination delay time in the next operation.
The universal dynamic delay jitter elimination method records the false operation times when the false operation is detected, adjusts the jitter elimination delay time of the next operation according to the recorded false operation times, and performs jitter elimination processing based on the adjusted jitter elimination delay time in the next operation. The application can adjust the jitter elimination delay time according to the false operation times, so that the jitter elimination delay time is more reasonable, the judgment of a plurality of times is avoided, and the judgment accuracy is ensured; meanwhile, one jitter elimination module can be used for adapting to different application scenes, and the workload of developers is reduced.
In some embodiments, the general dynamic delay jitter elimination subroutine stored in the readable storage medium may be implemented specifically as follows: the jitter elimination delay time of the next operation is calculated by the following formula: delay device n+1 =delay n + delay n * delaycounter/N; wherein, delay n Delay time for the jitter elimination of the nth operation n+1 The delay time is the jitter elimination delay time of the n+1th operation, the delay is the recorded false operation times, and N is the number of states experienced in the operation process.
In some embodiments, the general dynamic delay jitter elimination subroutine stored in the readable storage medium may be implemented specifically as follows: after the false operation is detected, when a normal operation is detected, the recorded number of false operations is cleared.
In some embodiments, the general dynamic delay jitter elimination subroutine stored in the readable storage medium may be implemented specifically as follows: when the recorded false operation times are zero, the jitter elimination delay time of the next operation is set as the initial jitter elimination delay time.
It will be apparent to those skilled in the art that the techniques of embodiments of the present application may be implemented in software plus a necessary general purpose hardware platform. Based on such understanding, the technical solution in the embodiments of the present application may be embodied essentially or in a part contributing to the prior art in the form of a software product stored in a storage medium such as a U-disc, a mobile hard disc, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk or an optical disk, etc. various media capable of storing program codes, including several instructions for causing a computer terminal (which may be a personal computer, a server, or a second terminal, a network terminal, etc.) to execute all or part of the steps of the method described in the embodiments of the present application.
In the several embodiments provided by the present application, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.
The foregoing disclosure is merely illustrative of the preferred embodiments of the application and the application is not limited thereto, since modifications and variations may be made by those skilled in the art without departing from the principles of the application.
Claims (8)
1. The universal dynamic delay jitter elimination method is characterized by comprising the following steps:
detecting whether the operation is a false operation; the false operation is an interference operation other than a normal operation;
when the false operation is detected, recording the number of false operations;
adjusting the jitter elimination delay time of the next operation according to the recorded false operation times, and performing jitter elimination processing based on the adjusted jitter elimination delay time in the next operation;
the jitter-elimination delay time of the next operation is adjusted according to the recorded false operation times, specifically, the jitter-elimination delay time of the next operation is calculated through the following formula:
delay n+1 =delay n + delay n *delaycounter/N；
wherein, delay n Delay time for the jitter elimination of the nth operation n+1 The delay time is the jitter elimination delay time of the n+1th operation, the delay is the recorded false operation times, and N is the number of states experienced in the operation process.
2. The universal dynamic time delay debounce method according to claim 1, further comprising the steps of:
after the false operation is detected, when a normal operation is detected, the recorded number of false operations is cleared.
3. The universal dynamic delay debounce method of claim 2, further comprising the steps of:
when the recorded false operation times are zero, the jitter elimination delay time of the next operation is set as the initial jitter elimination delay time.
4. A universal dynamic delay jitter elimination device is characterized by comprising,
operation detection unit: detecting whether the operation is a false operation; the false operation is an interference operation other than a normal operation;
a false operation number recording unit: when the false operation is detected, recording the number of false operations;
jitter elimination delay time adjusting unit: adjusting jitter elimination delay time of the next operation according to the recorded false operation times;
the jitter-elimination delay time adjusting unit adjusts the jitter-elimination delay time of the next operation according to the recorded false operation times, specifically, calculates the jitter-elimination delay time of the next operation through the following formula:
delay n+1 =delay n + delay n *delaycounter/N；
wherein, delay n For the nth operationDelay time of jitter elimination n+1 The delay time is the jitter elimination delay time of the n+1th operation, the delay is the recorded false operation times, and N is the number of states experienced in the operation process.
5. The universal dynamic time delay debounce device of claim 4, further comprising,
a zero clearing unit for recording the false operation times: after the false operation is detected, when a normal operation is detected, the recorded number of false operations is cleared.
6. The universal dynamic delay debounce device of claim 5, wherein the debounce delay time adjustment unit is further configured to set the debounce delay time of the next operation to an initial debounce delay time when the recorded number of dummy operations is zero.
7. A terminal, comprising:
the memory is used for storing a general dynamic delay jitter elimination program;
a processor for implementing the steps of the universal dynamic delay debounce method according to any one of claims 1-3 when executing said universal dynamic delay debounce program.
8. A readable storage medium, wherein a general dynamic delay debounce program is stored on the readable storage medium, the general dynamic delay debounce program implementing the steps of the general dynamic delay debounce method according to any one of claims 1-3 when executed by a processor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110865847.6A CN113765504B (en) | 2021-07-29 | 2021-07-29 | Universal dynamic delay jitter elimination method, device, terminal and storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110865847.6A CN113765504B (en) | 2021-07-29 | 2021-07-29 | Universal dynamic delay jitter elimination method, device, terminal and storage medium |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113765504A CN113765504A (en) | 2021-12-07 |
| CN113765504B true CN113765504B (en) | 2023-08-15 |
Family
ID=78788154
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110865847.6A Active CN113765504B (en) | 2021-07-29 | 2021-07-29 | Universal dynamic delay jitter elimination method, device, terminal and storage medium |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113765504B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116186086A (en) * | 2023-02-09 | 2023-05-30 | 辰芯半导体（深圳）有限公司 | Adaptive key jitter elimination digital processing method and system based on branch prediction |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109743263A (en) * | 2019-01-14 | 2019-05-10 | 北京三体云联科技有限公司 | Dynamic jitter buffer method, apparatus and computer equipment |
| CN111327386A (en) * | 2018-12-14 | 2020-06-23 | 深圳市中兴微电子技术有限公司 | Delay jitter compensation method and device and computer storage medium |
-
2021
- 2021-07-29 CN CN202110865847.6A patent/CN113765504B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111327386A (en) * | 2018-12-14 | 2020-06-23 | 深圳市中兴微电子技术有限公司 | Delay jitter compensation method and device and computer storage medium |
| CN109743263A (en) * | 2019-01-14 | 2019-05-10 | 北京三体云联科技有限公司 | Dynamic jitter buffer method, apparatus and computer equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113765504A (en) | 2021-12-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110113407B (en) | Applet state synchronization method, apparatus and computer storage medium | |
| CN103164523A (en) | Inspection method, device and system of data consistency inspection | |
| CN100365994C (en) | Method and system for regulating ethernet | |
| CN106502814B (en) | Method and device for recording error information of PCIE (peripheral component interface express) equipment | |
| EP3816924B1 (en) | Method for accepting blockchain evidence storage transaction and system | |
| CN113765504B (en) | Universal dynamic delay jitter elimination method, device, terminal and storage medium | |
| CN111800490A (en) | Method and device for acquiring network behavior data and terminal equipment | |
| WO2018026452A1 (en) | System and method for distributing and replaying trigger packets via a variable latency bus interconnect | |
| CN111381905B (en) | Program processing method, device and equipment | |
| JPH0528327A (en) | Ic card utilizing equipment | |
| CN111338628A (en) | Component rendering method and device | |
| CN111290915A (en) | Multipath equipment shielding system, method, equipment and readable storage medium | |
| CN114390114B (en) | User data packet protocol port scanning method, system, terminal and storage medium | |
| CN114328548B (en) | Dual-storage-pool data elimination speed control method, system, terminal and storage medium | |
| CN112311671B (en) | Method, apparatus, medium and device for issuing aggregated link configuration to switch chip | |
| CN111309521B (en) | FPGA reloading method, FPGA card type equipment and host | |
| CN109614246B (en) | Message processing method and device and message processing server | |
| CN115599287A (en) | Data processing method and device, electronic equipment and storage medium | |
| CN108133149B (en) | Data protection method and device and electronic equipment | |
| CN113177063A (en) | Thermal reset method and related device of PCI bus equipment | |
| CN112817701A (en) | Timer processing method and device, electronic equipment and computer readable medium | |
| CN113467720B (en) | Load balancing method and device, readable storage medium and electronic equipment | |
| CN112306348B (en) | Method and device for identifying touch operation and electronic equipment | |
| CN112148547B (en) | Method, device and equipment for monitoring application starting times and readable storage medium | |
| US6513126B1 (en) | System for modeling a processor-encoder interface by counting number of fast clock cycles occuring in one slower clock cycle and triggering a domain module if fast clock reaches the corresponding number of cycles |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |