CN113742003B - Program code execution method and device based on FPGA chip - Google Patents
Program code execution method and device based on FPGA chip Download PDFInfo
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- CN113742003B CN113742003B CN202111083820.8A CN202111083820A CN113742003B CN 113742003 B CN113742003 B CN 113742003B CN 202111083820 A CN202111083820 A CN 202111083820A CN 113742003 B CN113742003 B CN 113742003B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/445—Program loading or initiating
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention discloses a program code execution method and equipment based on an FPGA chip, wherein the method comprises the following steps: the equipment detects a control instruction, wherein the control instruction is used for indicating the equipment to call the program code associated with the control instruction; the program code is used for compressing the acquired ultra-high definition video by the equipment, or decompressing the compressed ultra-high definition video by the equipment; responding to the control instruction, calling the program code associated with the control instruction by the equipment, and loading the program code into the FPGA chip; the device compresses the acquired ultra-high definition video by executing the program codes through the FPGA chip, or decompresses the compressed ultra-high definition video by executing the program codes through the FPGA chip. By adopting the method and the device, the device can be used as the device for compressing the acquired ultra-high definition video and the device for decompressing the compressed ultra-high definition video, so that the method and the device are very convenient and fast, and the user experience is higher.
Description
Technical Field
The present invention relates to the field of video processing technologies, and in particular, to a method and apparatus for executing program codes based on an FPGA chip.
Background
Currently, the industry generally performs compression operation on the obtained high-definition video through an ASIC chip running the coding algorithm after the coding algorithm is burned into the ASIC chip, or performs decompression operation on the compressed high-definition video code stream data through an ASIC chip running the decoding algorithm after the decoding algorithm is burned into the ASIC chip; then, the above mentioned ASIC chip has a single function, and can only be used for compressing the high-definition video, or can only be used for decompressing the compressed high-definition video code stream data, so that the user experience is low.
Disclosure of Invention
In order to solve the technical problems, the invention provides a program code execution method and equipment based on an FPGA chip.
In order to solve the technical problems, the present invention provides a program code execution method based on an FPGA chip, the method comprising:
the method comprises the steps that equipment detects a control instruction, wherein the control instruction is used for indicating the equipment to call program codes associated with the control instruction; the program code is used for compressing the acquired ultra-high definition video by the equipment, or decompressing the compressed ultra-high definition video by the equipment;
Responding to the control instruction, calling the program code associated with the control instruction by the equipment, and loading the program code into an FPGA chip;
the device compresses the acquired ultra-high definition video by executing the program code through the FPGA chip, or decompresses the compressed ultra-high definition video by executing the program code through the FPGA chip.
To solve the above technical problems, the present invention provides a program code execution device based on an FPGA chip, the device comprising: the device comprises a processor and an FPGA chip, wherein the processor is used for detecting a control instruction, and the control instruction is used for indicating the equipment to call program codes associated with the control instruction; the program code is used for compressing the acquired ultra-high definition video by the equipment or decompressing the compressed ultra-high definition video; the FPGA chip is used for executing the program code to compress the uncompressed ultra-high definition video, or executing the program code to decompress the compressed ultra-high definition video.
After the scheme is adopted, different program codes are executed through the FPGA chip to compress the acquired ultra-high definition video or decompress the compressed ultra-high definition video, so that the device can be used as the device for compressing the acquired ultra-high definition video or the device for decompressing the compressed ultra-high definition video, and the method is very convenient and high in user experience.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic flow chart of a program code execution method based on an FPGA chip provided by the invention;
fig. 2 to 6 are schematic structural diagrams of the program code execution device based on the FPGA chip provided by the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made more apparent and fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments of the invention are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention. Referring to fig. 1, a schematic flow chart of a program code execution method based on an FPGA chip provided by the present invention, as shown in fig. 1,
S101, detecting a control instruction by the equipment.
The device detecting the control instruction may include, but is not limited to, the following:
mode 1:
when a user dials a dial switch of the device to a first side, the device detects that the level of a preset I/O interface of a micro control unit of the device is 0, and program codes associated with the level of the 0"I/O interface are used for compressing the acquired ultra-high definition video by the device; the program code associated with the 0"I/O interface level comprises: a compression algorithm for compressing the acquired ultra-high definition video; the preset I/O interface is any interface of the micro control unit; or alternatively, the process may be performed,
when a user dials a dial switch of the device to a second side, the device detects that the level of a preset I/O interface of the device is 1, and program codes associated with the level of the 1"I/O interface are used for decompressing the compressed ultra-high definition video by the device; the program code associated with the 1"I/O interface level comprises: and a decompression algorithm for decompressing the compressed ultra-high definition video. Wherein the first side comprises: left side, right side, upper side or lower side; the second side includes: left, right, upper or lower.
It should be noted that the position of the first side corresponds to or is symmetrical with the position of the second side; that is, when the first side is the left side, the second side is the right side, and when the first side is the right side, the second side is the left side; when the first side is the upper side, the second side is the lower side; when the first side is the lower side, the second side is the upper side; when the first side is the upper left side, the second side is the lower right side; when the first side is the lower left side, the second side is the upper right side. In particular, the method comprises the steps of,
it should be noted that when the dial switch of the device is dialed to the left, the device detects that the level of the preset I/O interface of the device is "1", and when the dial switch of the device is dialed to the left, the device detects that the level of the preset I/O interface of the device is "0"; and the program code associated with the '0"I/O interface level is used for compressing the acquired ultra-high definition video by the equipment, and the program code associated with the' 1"I/O interface level is used for decompressing the compressed ultra-high definition video by the equipment.
It should be noted that when the dial switch of the device is set to the upper side, the device detects that the level of the preset I/O interface of the device is "0", and when the dial switch of the device is set to the lower side, the device detects that the level of the preset I/O interface of the device is "1", and the program code associated with the level of the "1"I/O interface is used for compressing the acquired super-high definition video by the device, and the program code associated with the level of the "1"I/O interface is used for decompressing the compressed super-high definition video by the device.
It should be noted that when the dial switch of the device is set to the lower side, the device detects that the level of the preset I/O interface of the device is "0", and when the dial switch of the device is set to the upper side, the device detects that the level of the preset I/O interface of the device is "1"; and "0"I/O interface level-associated program code for the device to compress the acquired super-high definition video and "1"I/O interface level-associated program code for the device to decompress the compressed super-high definition video.
Mode 2:
the device detects a first control instruction received through the control interface and sent by the control device, wherein the first control instruction is used for indicating: the device is a transmitting device, and the device calls a program code associated with the first control instruction to compress the acquired ultra-high definition video; or alternatively, the process may be performed,
the device detects a second control instruction sent by the control device and received through the control interface, wherein the second control instruction is used for indicating: the device is receiving equipment, and the equipment calls the program code associated with the second control instruction to decompress the compressed ultra-high definition video; wherein the first control instruction is different from the second control instruction. The control device may include, but is not limited to: a mouse or keyboard;
Or the equipment detects a second control instruction which is received through the control interface and is sent by control software of the control equipment;
wherein the control interface may include, but is not limited to: type-C interface, USB interface, RS232 interface, SPI interface, net gape or I2C interface.
In the embodiment of the present invention, the control instruction is used to instruct the device to call the program code associated with the control instruction. The program code is used for compressing the acquired ultra-high definition video by the equipment or decompressing the compressed ultra-high definition video by the equipment;
wherein the ultra-high definition video may include, but is not limited to: the ultra-high definition video in RGB format or YUV format, or the ultra-high definition video in RGB format; the high-definition video data may further include, but is not limited to, the following features: the resolution may be: 1080P, 4K, or 8K resolution; the frame rate may be 30FPS, 60FPS, 100FPS, or 120FPS; high dynamic range HDR (High Dynamic Range Imaging).
Before the device detects the control instruction, the method may further include:
the equipment acquires a control instruction through an input interface; wherein the input interface may include, but is not limited to: one or more of HDMI interface, VGA interface, USB interface, type-C interface or DVI interface.
The program code is used by the device to compress the acquired ultra-high definition video, for example, the program code for compressing ultra-high definition video may include, but is not limited to: a compression coding algorithm code and a light compression coding algorithm code.
Wherein the compression coding algorithm comprises: an encoding algorithm based on an intra block copy prediction mode, an encoding algorithm based on a wide-angle intra prediction mode or an H.264 encoding algorithm; HEVC-SCC coding algorithm;
the light compression coding algorithm includes: a wavelet transform-based coding algorithm, a short-time Fourier transform-based coding algorithm, and a discrete cosine transform-based coding algorithm; the wavelet transform-based coding algorithm comprises: JPEG-XS encoding algorithm, JPEG-LS encoding algorithm or VDC-M encoding algorithm.
Program code for decompressing ultra-high definition video may include, but is not limited to: medium compression decoding algorithm code and light compression decoding algorithm code.
Wherein the compression decoding algorithm comprises: a decoding algorithm based on an intra block copy prediction mode, a decoding algorithm based on a wide-angle intra prediction mode or an H.264 decoding algorithm; HEVC-SCC decoding algorithm;
the light compression decoding algorithm includes: a decoding algorithm based on wavelet transformation, a decoding algorithm based on short-time Fourier transformation and a decoding algorithm based on discrete cosine transformation; the wavelet transform-based decoding algorithm includes: JPEG-XS decoding algorithm, JPEG-LS decoding algorithm or VDC-M decoding algorithm.
S102, responding to the control instruction, calling the program code associated with the control instruction by the equipment, and loading the program code into the FPGA chip.
In the embodiment of the invention, in response to the control instruction, the device invokes the program code associated with the control instruction, which may include but is not limited to:
in response to the control instruction, the device invokes program code associated with the control instruction from a memory integrated in the device through a Micro Control Unit (MCU); the memory may include, but is not limited to: a cache, FLASH memory or internal memory; or alternatively, the process may be performed,
in response to the control instruction, the device invokes program code associated with the control instruction from a cloud database of the device. The method comprises the steps of carrying out a first treatment on the surface of the The cloud database comprises: open source program code database.
In response to the control instruction, the device invokes program code associated with the control instruction and loads the program code into the FPGA chip, which may include, but is not limited to, the steps of:
and responding to the control instruction, calling a program code associated with the control instruction by the equipment through an internally integrated micro control unit, and loading the program code into the FPGA chip through an SPI interface of the micro control unit.
When the memory includes: FLASH memory, control instruction includes: the device comprises a first control instruction and a second control instruction, wherein the first control instruction is used for instructing the device to call the program code associated with the first control instruction so as to compress the acquired ultra-high definition video, and the second control instruction is used for instructing the device to call the program code associated with the second control instruction so as to decompress the compressed ultra-high definition video;
In response to the control instructions, the device invokes program code associated with the control instructions from a memory integrated in the device, which may include, but is not limited to, the following:
in response to the first control instruction, the device invokes program code for compressing the acquired ultra-high definition video from a first storage area integrated in a FLASH memory in the device; or alternatively, the process may be performed,
in response to the second control instruction, the device invokes program code that decompresses the compressed ultra-high definition video from a second memory area integrated in a FLASH memory in the device.
S103, the device executes the program codes through the FPGA chip to compress the acquired ultra-high definition video, or the device executes the program codes through the FPGA chip to decompress the compressed ultra-high definition video.
Specifically, the device executes the program code through the FPGA chip to compress the acquired super-high definition video, which may include, but is not limited to:
the device executes a program code through the FPGA chip to compress the acquired ultra-high definition video so as to obtain code stream data;
the code stream data are used for packaging equipment through a communication protocol to obtain a data packet; the communication protocol includes: UDP communication protocol, TCP communication protocol, or custom communication protocol; the program code includes: and the compression algorithm is used for compressing the obtained ultra-high definition video.
Specifically, the device decompresses the compressed super-high definition video by executing program code through the FPGA chip, which may include, but is not limited to:
the device decompresses the code stream data by executing program codes through the FPGA chip to obtain the ultra-high definition video;
wherein the compressed ultra-high definition video comprises: code stream data; the program code includes: a decompression algorithm for decompressing code stream data.
The device executes program codes through the FPGA chip to compress uncompressed ultra-high definition video, and after obtaining code stream data, the device further comprises:
the device encapsulates the code stream data into data packets through a communication protocol;
the communication protocol includes: UDP communication protocol, TCP communication protocol, or custom communication protocol; the data packet includes: UDP packets, TCP packets, or custom packets. More specifically, the method comprises the steps of,
the device encapsulates the code stream data into UDP data packets through a UDP communication protocol; that is, the device encapsulates the UDP header, the UDP trailer, and the code stream data into a UDP packet; the UDP data head and the UDP data tail comprise control information such as a destination address, a source address, a port number, a marking bit and the like of the ultra-high definition video; or alternatively, the process may be performed,
the device encapsulates the code stream data into TCP data packets through a TCP communication protocol; that is, the device encapsulates the TCP header, the TCP trailer, and the code stream data into TCP packets; the TCP data head and the TCP data tail comprise control information such as a destination address, a source address, a port number, a flag bit and the like of the ultra-high definition video; or alternatively, the process may be performed,
The device encapsulates the code stream data into a custom data packet through a custom communication protocol, namely, the device encapsulates the custom data header, the custom data trailer and the code stream data into the custom data packet; the custom data head and the custom data tail comprise control information such as a destination address, a source address, a port number, a flag bit and the like of the ultra-high definition video.
After the device encapsulates the code stream data into data packets through the communication protocol, the method may further include:
the device converts the data packet into an optical signal through the optical module and transmits the optical signal to a preset device, or,
the device converts the data packet into an optical signal through the optical module and sends the optical signal to the switch, wherein the switch is used for forwarding the optical signal to preset equipment.
After the device encapsulates the code stream data into a data packet through a communication protocol, the method may further include:
after the device outputs the data packet to the PHY chip through the communication time sequence interface of the MAC unit, the device outputs the data packet to the RJ-45 interface through the PHY chip, and sends the data packet to a preset device through the RJ-45 interface, or,
after the device outputs the data packet to the PHY chip through the communication time sequence interface of the MAC unit, the device outputs the data packet to an RJ-45 interface through the PHY chip and sends the data packet to a switch through the RJ-45 interface, wherein the switch is used for forwarding the data packet to the preset device; the switch may include: gigabit or tera-switch; the switch may also be: the switches are stacked.
The communication timing interface may include, but is not limited to: one or more of an XFI interface, an MII interface, a GMII interface, an SGMII interface, an RGMII interface, an XGMII interface, a Serdes interface, an XAUI interface, or an RXAUI interface.
After the device encapsulates the code stream data into a data packet through a communication protocol, the method may further include:
the device sends the data packet to preset device through the 5G communication module;
the communication interface of the 5G communication module may include, but is not limited to: PCIE interfaces, gigabit ethernet interfaces, 1G ethernet interfaces, 10G ethernet interfaces, USB3.0 interfaces, and the like. The 5G communication module can be a 5G communication module which adopts Aip (Antenna in Package) technology to package a plurality of antennas inside, and adopts large-scale multiple-input multiple-output (Multi Input Multi Output, MIMO) technology to improve the transmission rate of protocol stream data and reduce the transmission delay.
Or alternatively, the process may be performed,
the device sends the data packet to the base station through the 5G communication module, and the base station is used for forwarding the data packet to the preset device.
When the preset device includes: when the first preset device and the second preset device,
the device sends the data packet to a preset device through a 5G communication module, which may include:
The device sends the data packet to a first preset device and a second preset device through a 5G communication module respectively.
When the base station includes: when the first base station and the second base station are in use,
the device sends the data packet to the base station through the 5G communication module, which may include:
the device sends the data packet to the first base station through the 5G communication module, the data packet is forwarded to the second base station through the first base station, and the data packet is forwarded to the preset device through the second base station.
After the device encapsulates the code stream data into the data packet through the communication protocol, the device further includes:
the device sends the data packet to the preset device through the WIFI communication module.
And the device sends the data packet to preset devices through the WIFI communication module. The WIFI module adopts an orthogonal frequency division multiple access (Orthogonal Frequency Division Multiple Access, OFDMA) technology, and on the other hand, the WIFI module integrates a plurality of antenna communication modules.
When the preset device includes: when the first preset device and the second preset device,
the device sends the data packet to the preset device through the WIFI communication module, and may include:
the device sends the data packet to a first preset device and a second preset device through the WIFI communication module respectively.
After the device encapsulates the code stream data into data packets through the communication protocol, the method may further include:
the device sends the data packet to the preset device through the 60G communication module.
When the preset device includes: when the first preset device and the second preset device,
the device sends the data packet to the preset device through the 60G communication module, which may include:
the device will send the data packet to the first preset device and the second preset device through the 60G communication module, respectively.
The device decompresses the code stream data by executing the program code through the FPGA chip, and after obtaining the ultra-high definition video, the device further comprises:
the device outputs the ultra-high definition video to a display device coupled with the device through an output interface; the display device is used for displaying the ultra-high definition video; the output interface comprises: one or more of HDMI interface, VGA interface, USB interface, type-C interface or DVI interface.
The invention provides a program code executing device based on an FPGA chip, which can be used for realizing the program code executing method based on the FPGA chip in the embodiment of FIG. 1. Wherein the apparatus shown in fig. 2 may be used to perform the description in the embodiment of fig. 1.
As shown in fig. 2, the device 20 may include, but is not limited to: input interface 200, memory 201, processor 202, light module 203, FPGA chip 204.
Input interface 200 may include, but is not limited to: HDMI interface, VGA interface, USB interface, type-C interface or DVI interface.
The processor 202 is operable to:
detecting a control instruction, wherein the control instruction is used for instructing the device to call program codes associated with the control instruction from the memory 201 through a preset I/O interface of the processor 202; the program code is used for compressing the acquired ultra-high definition video by the device 20 or decompressing the compressed ultra-high definition video;
in response to the control instruction, invoking program code associated with the control instruction from memory 201 and loading the program code into FPGA chip 204; wherein the memory 201 may comprise: a FLASH memory;
wherein the processor 202 may include, but is not limited to: a Micro Control Unit (MCU);
the processor 202 is further operable to:
in response to the control instruction, the program code associated with the control instruction is invoked and loaded into the FPGA chip through the SPI interface of the processor 202.
The processor 202 is further operable to:
in response to the first control instruction, invoking program code for compressing the acquired ultra-high definition video from a first storage area in a FLASH memory integrated in the device 20; or alternatively, the process may be performed,
Program code for decompressing the compressed ultra-high definition video is invoked from a second memory area integrated in FLASH memory in the device 20 in response to the second control instruction.
FPGA chip 204, operable to:
the program code is executed to compress the uncompressed ultra high definition video or is operable to execute the program code to decompress the compressed ultra high definition video.
The processor 202 is specifically configured to:
when a user dials a dial switch of the device 20 to a first side, detecting that a level of a preset I/O interface of the device 20 is "0", wherein program codes associated with the level of the I/O interface of the "0" are used for compressing the acquired ultra-high definition video by the device 20; the "0" level associated program code comprising: a compression algorithm for compressing the acquired ultra-high definition video; or alternatively, the process may be performed,
when a user dials a dial switch of the device 20 to a second side, detecting that the level of a preset I/O interface of the device 20 is "1", wherein the program code associated with the "1" level is used for decompressing the compressed ultra-high-definition video by the device 20; the "1" level associated program code includes: a decompression algorithm for decompressing the compressed ultra-high definition video; wherein the first side is located at a position corresponding to or symmetrical with the second side.
The processor 202 is specifically further configured to:
detecting a first control instruction received through the control interface and sent by the control device, wherein the first control instruction is used for instructing the device 20 to call a program code associated with the first control instruction to compress the acquired ultra-high definition video; or alternatively, the process may be performed,
detecting a second control instruction received through the control interface and sent by the control device, wherein the second control instruction is used for instructing the device 20 to call the program code associated with the second control instruction to decompress the compressed ultra-high definition video; the control apparatus includes: a mouse or keyboard;
wherein the control interface comprises: USB interface, RS232 interface, SPI interface or I2C interface.
The processor 202 is specifically further configured to:
in response to the control instruction, invoking program code associated with the control instruction from a memory integrated in the device 20; or alternatively, the process may be performed,
in response to a control instruction, program code associated with the control instruction is invoked from a cloud database of device 20.
FPGA chip 204, operable to:
executing program codes for compressing the ultra-high definition video to compress the obtained ultra-high definition video to obtain code stream data;
The code stream data is used for the equipment to package through a communication protocol to obtain a data packet; the communication protocol includes: UDP communication protocol, TCP communication protocol, or custom communication protocol; the program code includes: and a compression algorithm for compressing the acquired ultra-high definition video.
FPGA chip 204, further operable to:
executing program codes for decompressing the compressed ultra-high definition video to decompress the compressed ultra-high definition video to obtain the ultra-high definition video;
wherein the compressed ultra-high definition video comprises: the code stream data; the program code includes: a decompression algorithm for decompressing the code stream data.
FPGA chip 204, further operable to:
compressing the obtained ultra-high definition video, and after obtaining code stream data, further comprising:
encapsulating the code stream data into data packets through a communication protocol; the communication protocol includes: UDP communication protocol, TCP communication protocol, or custom communication protocol; the data packet includes: UDP packets, TCP packets, or custom packets.
Optical module 203, operable to:
converting the data packet into an optical signal, and transmitting the optical signal to a preset device, or,
And converting the data packet into an optical signal, and sending the optical signal to a switch, wherein the switch is used for forwarding the optical signal to the preset equipment.
It should be understood that apparatus 20 is merely one example provided for embodiments of the present invention, and that apparatus 20 may have more or fewer components than shown, may combine two or more components, or may have different configuration implementations of the components.
It will be appreciated that, regarding the specific implementation of the functional modules included in the apparatus 20, reference may be made to the foregoing method embodiment shown in fig. 1, and no further description is given here.
Fig. 2 is merely for explaining an embodiment of the present invention and should not be construed as limiting the present invention.
The invention provides another program code executing device based on an FPGA chip, which can be used for realizing the program code executing method based on the FPGA chip in the embodiment of FIG. 1. Wherein the apparatus shown in fig. 3 may be used to perform the description in the embodiment of fig. 1.
As shown in fig. 3, the device 30 may include, but is not limited to: input interface 300, memory 301, processor 302, electrical module 303, FPGA chip 304.
The specific implementation method or function of the input interface 300 and the processor 302 may refer to the function of the processor in fig. 2, and the embodiment of the present invention will not be described herein.
The specific implementation method or function of the FPGA chip 304 may refer to the function of the FPGA chip in fig. 2, and the description of the embodiment of the present invention is omitted.
The electrical module 303 may include: PHY chip and RJ-45 interface; wherein, the device 30 can be used for outputting the data packet to the PHY chip through the communication time sequence interface of the MAC unit; wherein, communication timing interface includes: XFI interface, MII interface, GMII interface, SGMII interface, RGMII interface, XGMII interface, serdes interface, XAUI interface, or RXAUI interface.
The electrical module 303 is for:
the received data packet is output to the RJ-45 interface through the PHY chip, and is sent to a preset device through the RJ-45 interface, or,
and outputting the received data packet to an RJ-45 interface through the PHY chip, and sending the data packet to a switch through the RJ-45 interface, wherein the switch is used for forwarding the data packet to preset equipment.
It should be understood that device 30 is merely one example provided for embodiments of the present invention, and that device 30 may have more or fewer components than shown, may combine two or more components, or may have different configuration implementations of the components.
It will be appreciated that, regarding the specific implementation of the functional modules included in the device 30, reference may be made to the foregoing method embodiment shown in fig. 1 and the embodiment shown in fig. 2, which are not repeated here.
Fig. 3 is merely for explaining an embodiment of the present invention and should not be construed as limiting the present invention.
The invention provides a program code executing device based on an FPGA chip, which can be used for realizing the program code executing method based on the FPGA chip in the embodiment of FIG. 1. Wherein the apparatus shown in fig. 4 may be used to perform the description in the embodiment of fig. 1.
As shown in fig. 4, the device 40 may include, but is not limited to: input interface 400, memory 401, processor 402, WIFI communication module 403, FPGA chip 404.
The specific implementation method or function of the input interface 400 and the processor 402 may refer to the function of the processor in fig. 2, and the embodiment of the present invention will not be described herein.
The specific implementation method or function of the FPGA chip 404 may refer to the function of the FPGA chip in fig. 2, and the embodiment of the present invention will not be described again.
WIFI communication module 403, operable to:
and sending the data packet to preset equipment through the WIFI communication module.
When the preset device includes: when the first preset device and the second preset device,
WIFI communication module 403, operable to:
and respectively sending the data packet to the first preset device and the second preset device through the WIFI communication module.
The WIFI module adopts an orthogonal frequency division multiple access (Orthogonal Frequency Division Multiple Access, OFDMA) technology, and on the other hand, the WIFI module integrates a plurality of antenna communication modules.
It should be understood that device 40 is merely one example provided for embodiments of the present invention, and that device 40 may have more or fewer components than shown, may combine two or more components, or may have different configuration implementations of the components.
It will be appreciated that, regarding the specific implementation of the functional modules included in the device 40, reference may be made to the foregoing method embodiment shown in fig. 1 and the embodiment shown in fig. 2, which are not repeated here.
Fig. 4 is merely for explaining an embodiment of the present invention and should not be construed as limiting the present invention.
The invention provides a program code executing device based on an FPGA chip, which can be used for realizing the program code executing method based on the FPGA chip in the embodiment of FIG. 1. Wherein the apparatus shown in fig. 5 may be used to perform the description in the embodiment of fig. 1.
As shown in fig. 5, the device 50 may include, but is not limited to: input interface 500, memory 501, processor 502, 5G communication module 503, FPGA chip 504.
The specific implementation method or function of the input interface 500 and the processor 502 may refer to the function of the processor in fig. 2, and the embodiment of the present invention will not be described herein.
The specific implementation method or function of the FPGA chip 504 may refer to the function of the FPGA chip in fig. 2, and the description of the embodiment of the present invention is omitted.
The 5G communication module 503 may be configured to:
transmitting the data packet to preset equipment; the communication interface of the 5G communication module 503 may include, but is not limited to: PCIE interfaces, gigabit ethernet interfaces, 1G ethernet interfaces, 10G ethernet interfaces, USB3.0 interfaces, and the like. Or alternatively, the process may be performed,
and sending the data packet to a base station, wherein the base station is used for forwarding the data packet to preset equipment.
When the preset device includes: when the first preset device and the second preset device,
and respectively sending the data packet to the first preset device and the second preset device. The first display device connected with the first preset device and the second display device connected with the second preset device can respectively display the ultra-high definition video. Or alternatively, the process may be performed,
and sending the data packet to the first base station, forwarding the data packet to the second base station through the first base station, and forwarding the data packet to preset equipment through the second base station.
It should be understood that device 50 is merely one example provided for embodiments of the present invention, and that device 50 may have more or fewer components than shown, may combine two or more components, or may have different configuration implementations of the components.
It will be appreciated that, regarding the specific implementation of the functional modules included in the apparatus 50, reference may be made to the foregoing method embodiment shown in fig. 1 and the embodiment shown in fig. 2, which are not repeated here.
Fig. 5 is merely for explaining an embodiment of the present invention and should not be construed as limiting the present invention.
The invention provides a program code executing device based on an FPGA chip, which can be used for realizing the program code executing method based on the FPGA chip in the embodiment of FIG. 1. Wherein the apparatus shown in fig. 6 may be used to perform the description in the embodiment of fig. 1.
As shown in fig. 6, the device 60 may include, but is not limited to: input interface 600, memory 601, processor 602, 5G communication module 603, FPGA chip 604.
The specific implementation method or function of the input interface 600 and the processor 602 may refer to the function of the processor in fig. 2, and the embodiment of the present invention will not be described herein.
The specific implementation method or function of the FPGA chip 604 may refer to the function of the FPGA chip in fig. 2, and the description of the embodiment of the present invention is omitted.
The 5G communication module 603 may be configured to:
after the modem modulates the data packet, the modem is used for transmitting the modulated signal to preset equipment through a millimeter wave communication technology in the 60Ghz frequency band.
When the preset device includes: when the first preset device and the second preset device,
60G communication module 603, operable to:
and respectively transmitting the data packet to the first preset device and the second preset device through a millimeter wave communication technology in the 60Ghz frequency band.
It should be understood that the apparatus 60 is merely one example provided for an embodiment of the present invention, and that the apparatus 60 may have more or less components than those shown, may combine two or more components, or may have different configuration implementations of components.
It will be appreciated that, regarding the specific implementation of the functional modules included in the apparatus 60, reference may be made to the foregoing method embodiment shown in fig. 1 and the embodiment shown in fig. 2, which are not repeated here.
Fig. 6 is merely for explaining an embodiment of the present invention and should not be construed as limiting the present invention.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and the various illustrative elements and steps are described above in terms of functions generally in order to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
It will be clearly understood by those skilled in the art that, for convenience and brevity of description, specific working procedures of the apparatus, system and unit described above may refer to corresponding procedures in the foregoing method embodiments, which are not repeated herein.
In the several embodiments provided by the present invention, it should be understood that the disclosed apparatus, system, and method may be implemented in other ways. For example, the compositions and steps of the examples are described. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The above described embodiments of systems, devices are merely illustrative, e.g., the division of the elements is merely a logical functional division, and there may be additional divisions when actually implemented, e.g., multiple elements or components may be combined or integrated into another system, or some features may be omitted or not performed. In addition, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices, systems, or units, or may be an electrical, mechanical, or other form of connection.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the embodiment of the present invention.
In addition, each functional unit in the embodiments of the present invention may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.
The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention is essentially or a part contributing to the prior art, or all or part of the technical solution may be embodied in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
While the invention has been described with reference to certain preferred embodiments, it will be understood by those skilled in the art that various changes and substitutions of equivalents may be made and equivalents will be apparent to those skilled in the art without departing from the scope of the invention. Therefore, the protection scope of the invention is subject to the protection scope of the claims.
Claims (11)
1. A program code execution method based on an FPGA chip, comprising:
the method comprises the steps that equipment detects a control instruction, wherein the control instruction is used for indicating the equipment to call program codes associated with the control instruction; the program code is used for compressing the acquired ultra-high definition video by the equipment, or decompressing the compressed ultra-high definition video by the equipment;
responding to the control instruction, calling the program code associated with the control instruction by the equipment, and loading the program code into an FPGA chip;
the device executes the program code through the FPGA chip to compress the acquired ultra-high definition video, or the device executes the program code through the FPGA chip to decompress the compressed ultra-high definition video;
The device detecting a control instruction, comprising:
when a user dials a dial switch of the device to a first side, the device detects that the level of a preset I/O interface of a micro control unit of the device is 0, the 0 level indicates that the device is a transmitting device, and program codes associated with the 0"I/O interface level are used for compressing the acquired ultra-high definition video by the device; the program code associated with the 0"I/O interface level comprises: a compression algorithm for compressing the acquired ultra-high definition video; the preset I/O interface is any interface of the micro control unit; or alternatively, the process may be performed,
when a user dials a dial switch of the device to a second side, the device detects that the level of a preset I/O interface of a micro control unit of the device is 1, the 1 level indicates that the device is a receiving device, and program codes associated with the 1"I/O interface level are used for decompressing the compressed ultra-high definition video by the device; the program code associated with the 1"I/O interface level comprises: a decompression algorithm for decompressing the compressed ultra-high definition video; wherein the first side is located at a position corresponding to or symmetrical with the second side.
2. The method for executing program code based on an FPGA chip as set forth in claim 1,
the device detecting a control instruction, comprising:
the device detects a first control instruction sent by the control device and received through the control interface, wherein the first control instruction is used for indicating: the device is a transmitting device, and the device calls a program code associated with the first control instruction to compress the acquired ultra-high definition video; or alternatively, the process may be performed,
the device detects a second control instruction sent by the control device and received through a control interface, wherein the second control instruction is used for indicating: the device is receiving equipment, and the equipment calls the program code associated with the second control instruction to decompress the compressed ultra-high definition video; wherein the control interface comprises: USB interface, RS232 interface, SPI interface, net gape or I2C interface.
3. The method for executing program code based on an FPGA chip as set forth in claim 1,
in response to the control instruction, the device invokes program code associated with the control instruction, including:
in response to the control instruction, the device invokes program code associated with the control instruction from a memory integrated in the device; or alternatively, the process may be performed,
In response to the control instruction, the device invokes program code associated with the control instruction from a cloud database of the device; the cloud database comprises: open source program code database.
4. The method for executing program code based on an FPGA chip as set forth in claim 1,
in response to the control instruction, the device invokes program code associated with the control instruction and loads the program code into the FPGA chip, including:
and responding to the control instruction, calling the program code associated with the control instruction by the equipment through an internally integrated micro control unit, and loading the program code into an FPGA chip through an SPI interface of the micro control unit.
5. The method for executing program code based on an FPGA chip as set forth in claim 3,
the memory includes: a FLASH memory; the control instruction includes: a first control instruction and a second control instruction; the first control instruction is used for indicating the equipment to call the program code associated with the first control instruction so as to compress the acquired ultra-high definition video; the second control instruction is used for indicating the equipment to call the program code associated with the second control instruction so as to decompress the compressed ultra-high definition video;
In response to the control instruction, the device invokes program code associated with the control instruction from a memory integrated in the device, comprising:
in response to the first control instruction, the device invokes program code for compressing the acquired ultra-high definition video from a first storage area integrated in a FLASH memory in the device; or alternatively, the process may be performed,
in response to the second control instruction, the device invokes program code that decompresses the compressed ultra-high definition video from a second memory area integrated in a FLASH memory in the device.
6. The method for executing program code based on an FPGA chip as set forth in claim 1,
the device executes the program code through the FPGA chip to compress the acquired ultra-high definition video, including:
the device executes the program codes through the FPGA chip to compress the acquired ultra-high definition video so as to obtain code stream data;
the code stream data is used for the equipment to package through a communication protocol to obtain a data packet; the program code includes: a compression algorithm for compressing the acquired ultra-high definition video; the communication protocol includes: UDP communication protocol, TCP communication protocol, or custom communication protocol.
7. The method for executing program code based on an FPGA chip as set forth in claim 1,
the device decompresses the compressed ultra-high definition video by executing the program code through the FPGA chip, comprising:
the device decompresses the code stream data by executing the program codes through the FPGA chip to obtain the ultra-high definition video;
wherein the compressed ultra-high definition video comprises: the code stream data; the program code includes: a decompression algorithm for decompressing the code stream data.
8. The method for executing program code based on an FPGA chip as set forth in claim 6,
the device executes the program code through the FPGA chip to compress the acquired super-high definition video, and after obtaining code stream data, the device further includes:
the device encapsulates the code stream data into data packets through a communication protocol; the communication protocol includes: UDP communication protocol, TCP communication protocol, or custom communication protocol; the data packet includes: UDP packets, TCP packets, or custom packets.
9. The method for executing program code based on an FPGA chip as recited in claim 8, wherein,
After the device encapsulates the code stream data into a data packet through a communication protocol, the device further includes:
the device sends the data packet through a communication module; the communication module includes: an optical module, an electrical module, a 5G communication module, a WIFI communication module, or a 0G communication module; wherein the electrical module comprises: PHY chip and RJ-45 interface.
10. The method for executing program code based on an FPGA chip as recited in claim 7, wherein,
the device decompresses the code stream data by executing the program code through the FPGA chip, and after obtaining the ultra-high definition video, the device further comprises:
the device outputs the ultra-high definition video to a display device coupled with the device through an output interface; the display device is used for displaying the ultra-high definition video; the output interface includes: one or more of HDMI interface, VGA interface, USB interface, type-C interface or DVI interface.
11. A program code execution device based on an FPGA chip, comprising:
a processor and an FPGA chip, wherein,
the processor is used for detecting a control instruction, and the control instruction is used for instructing the equipment to call the program code associated with the control instruction; the program code is used for compressing the acquired ultra-high definition video by the equipment or decompressing the compressed ultra-high definition video;
The FPGA chip is used for executing the program code to compress uncompressed ultra-high definition video, or executing the program code to decompress the compressed ultra-high definition video;
the device detecting a control instruction, comprising:
when a user dials a dial switch of the device to a first side, the device detects that the level of a preset I/O interface of a micro control unit of the device is 0, the 0 level indicates that the device is a transmitting device, and program codes associated with the 0"I/O interface level are used for compressing the acquired ultra-high definition video by the device; the program code associated with the 0"I/O interface level comprises: a compression algorithm for compressing the acquired ultra-high definition video; the preset I/O interface is any interface of the micro control unit; or alternatively, the process may be performed,
when a user dials a dial switch of the device to a second side, the device detects that the level of a preset I/O interface of a micro control unit of the device is 1, the 1 level indicates that the device is a receiving device, and program codes associated with the 1"I/O interface level are used for decompressing the compressed ultra-high definition video by the device; the program code associated with the 1"I/O interface level comprises: a decompression algorithm for decompressing the compressed ultra-high definition video; wherein the first side is located at a position corresponding to or symmetrical with the second side.
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