CN113740719A - Chip and chip testing method - Google Patents

Abstract

The invention provides a chip and a chip testing method. The chip includes a data selector, a plurality of data samplers, and a test circuit. The data selector has a plurality of inputs and an output. The test circuit has a plurality of signal transmission paths. The plurality of signal transmission paths of the test circuit are respectively coupled between the plurality of input ends of the data selector and the plurality of data samplers. In the test mode, the test circuit outputs a plurality of output signals transmitted to the plurality of input terminals of the data selector to the plurality of data samplers via the plurality of signal transmission paths, and the plurality of data samplers output a plurality of test signals according to the plurality of output signals and the plurality of first clock signals. Therefore, the chip and the chip testing method can carry out effective loopback testing.

Description

Chip and chip testing method

Technical Field

The invention relates to a testing technology, in particular to a chip and a chip testing method.

Background

At present, the chip is developed towards the characteristics of high-speed operation and high-speed communication. As chip products become more bandwidth and delay demanding, higher and higher speed sequencer/de-sequencer (Serdes) protocols are beginning to be used to enable chip and external communications. In this regard, communication transmission rates of current chips have evolved to, for example, 50 gigabits per second (Gbps), and even 100 Gbps. Therefore, the reliability of the communication capability test of the current chip at the Design for Testability (DFT) stage in the manufacturing process is reduced.

For example, when a data signal transmitted by a chip is implemented by a four-level Pulse Amplitude Modulation (PAM 4) technique, because the frequency of the data signal is too high (for example, more than 50 Gbps), a clock signal and a data selector inside the chip cannot keep up with the data signal, so that a test signal of a loopback test of a general high-speed chip may be severely distorted due to the clock skew (clock skew) of the clock signal, and an effective loopback test (loopback test) cannot be performed.

For example, as shown in fig. 6, the eye diagram 600 of fig. 6 is a signal result of a loop-back test performed on a PAM4 signal by a general chip, wherein the eye widths 601-603 are 4.32942 picoseconds (ps), 3.71685 picoseconds (ps), and 3.49099 picoseconds (ps), respectively. That is, the test signal of the loopback test of a general high-speed chip has high intersymbol interference and noise, so that the communication function of the chip cannot be effectively tested.

Disclosure of Invention

The invention aims at a chip and a chip testing method, which can effectively test the communication function of the chip.

According to an embodiment of the present invention, a chip includes a data selector, a plurality of data samplers, and a test circuit. The data selector is provided with a plurality of input ends and output ends. The test circuit has a plurality of signal transmission paths. The plurality of signal transmission paths of the test circuit are respectively coupled between the plurality of input ends of the data selector and the plurality of data samplers. In the test mode, the test circuit transfers a plurality of output signals transmitted to the plurality of input terminals of the data selector to the plurality of data samplers via a plurality of signal transmission paths, and the plurality of data samplers output a plurality of test signals according to the plurality of output signals and the plurality of first clock signals.

According to the embodiment of the invention, the chip testing method is suitable for loopback testing. The chip includes a data selector and a plurality of data samplers. The chip also includes a test circuit. The plurality of signal transmission paths of the test circuit are respectively coupled between the plurality of input ends of the data selector and the plurality of data samplers. The chip testing method comprises the following steps: in a test mode, passing a plurality of output signals transmitted to a plurality of input terminals of the data selector to a plurality of data samplers by a test circuit via a plurality of signal transmission paths; outputting a plurality of test signals according to a plurality of output signals and a plurality of first clock signals through a plurality of data samplers; and performing loopback testing according to the plurality of test signals.

Based on the above, the chip and the chip testing method of the present invention can directly transmit the plurality of output signals to the plurality of data samplers based on the design of the signal transmission path, so as to reduce the data frequency of the test signal received by the back-end circuit of the chip, thereby reducing the requirements on the performance and the data timing sequence of the loopback test path.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

FIG. 1 is a schematic diagram of the internal circuitry of a chip according to a first embodiment of the invention;

FIG. 2 is a flow chart of a chip testing method according to an embodiment of the invention;

FIG. 3 is a schematic diagram of the internal circuitry of a chip according to a second embodiment of the present invention;

FIG. 4 is a schematic diagram of the internal circuitry of a chip according to a third embodiment of the present invention;

FIG. 5 is a schematic diagram of the internal circuitry of a chip according to a fourth embodiment of the present invention;

FIG. 6 is an exemplary eye diagram for loopback testing of a generic chip;

FIG. 7 is an exemplary eye diagram for a loopback test corresponding to four-level pulse amplitude modulation in accordance with an embodiment of the present invention;

FIG. 8 is an exemplary eye diagram for a loopback test corresponding to four-level pulse amplitude modulation according to another embodiment of the present invention;

fig. 9 is an exemplary eye diagram of a loopback test corresponding to four-level pulse amplitude modulation of yet another embodiment of the present invention.

Detailed Description

Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

Fig. 1 is a schematic diagram of an internal circuit of a chip according to a first embodiment of the present invention. Referring to FIG. 1, a chip 100 includes a data selector 110, a plurality of data samplers (slicers) 121-124, a front end circuit 130, and a test circuit. In the present embodiment, the data selector 110 has a plurality of input terminals and output terminals, and can receive the output signals So1 to So4 provided by the internal circuits of the chip 100 simultaneously or sequentially. The test circuit has a plurality of signal transmission paths 161-164. The signal transmission paths 161-164 of the test circuit are coupled between the input terminals of the data selector 110 and the data samplers 121-124, respectively. An output terminal of the data selector 110 is coupled to the signal output terminal 101(TX terminal) of the chip 100. The signal transmission paths 161-164 are each a physical signal trace. Front-end circuit 130 is coupled between signal input 102(RX side) of chip 100 and data samplers 121-124.

In the present embodiment, the output signals So1 and So2 may correspond to the Least Significant Bits (LSBs) of the data, and the output signals So3 and So4 may correspond to the Most Significant Bits (MSBs) of the data. The data selector 110 may be a four-to-one Multiplexer (4:1Multiplexer) and may also receive clock signals CK 1-CK 4. The clock signals CK 1-CK 4 have a phase difference of 90 degrees in sequence. The signal waveform of the clock signal CK1 corresponds to a phase of 0 degrees, for example. The signal waveform of the clock signal CK2 corresponds to a phase of 90 degrees. The signal waveform of the clock signal CK3 corresponds to a phase of 180 degrees. The signal waveform of the clock signal CK4 corresponds to a phase of 270 degrees.

In the present embodiment, the chip 100 may be, for example, an artificial intelligence chip (AI chip) or other chip capable of high-speed communication. The chip 100 of the present embodiment may be suitable for performing an internal loopback test (loopback test) in a Design for Testability (DFT) stage of a manufacturing process, for example, so as to effectively test the communication function of the chip 100. In this embodiment, the chip 100 may be designed based on a communication signal conforming to a high-speed Serializer-Deserializer (SERDES) protocol to communicate with the outside. In the embodiment, the communication signals output and received by the signal output terminal 101 and the signal input terminal 102 of the chip 100 may have a pattern (pattern) format of Pulse Amplitude Modulation 4-level (PAM 4), but the invention is not limited thereto. In other embodiments of the present invention, the communication signals output and received by the signal output terminal 101 and the signal input terminal 102 of the chip 100 may also have a Non-Return-to-Zero (NRZ) code format (or a two-level Pulse Amplitude Modulation (PAM 2) code format).

In the communication mode of the chip 100, the data selector 110 may output a pulse amplitude modulation signal having four amplitude levels (PAM4 signal) from the output terminal of the data selector 110 to the signal output terminal 101 of the chip 100 according to the output signals So1 to So4 and the clock signals CK1 to CK 4. Moreover, the signal input terminal 102 of the chip 100 may also receive another corresponding fourth-order pwm signal. The data samplers 121 to 124 respectively receive the clock signals CK1 to CK4 to respectively generate four input signals to the internal circuits of the chip 100 according to another four-level pwm signal and the corresponding clock signal.

Alternatively, in other embodiments of the present invention, in the communication mode of the chip 100, the data selector 110 may output the pwm signal having two amplitude levels (e.g., NRZ signal) from the output terminal of the data selector 110 to the signal output terminal 101 of the chip 100 according to the output signal So1, the output signal So2 (or the output signal So3 and the output signal So4), and another two clock signals having a phase difference of 180 degrees. Moreover, the signal input terminal 102 of the chip 100 may also receive another corresponding two-step pwm signal. The data samplers 121 and 122 (or the data samplers 123 and 124) may respectively receive two other clock signals with a phase difference of 180 degrees to generate two input signals to the internal circuits of the chip 100 according to the two other level pulse amplitude modulation signals and the corresponding clock signals.

In a test mode of the chip 100, the test circuit can transmit the output signals So 1-So 4 transmitted to the input terminals of the data selector 110 to the data samplers 121-124 through the signal transmission paths 161-164. It should be noted that the output signals So 1-So 4 have two amplitude levels (corresponding to data "0" and data "1"), respectively, and have test patterns with arbitrary amplitude level variations. For this, the output signals So 1-So 4 may have aperiodic data inverted test patterns, such as Pseudo Random Binary Sequence (PRBS) test patterns. The data samplers 121 to 124 may output a plurality of test signals Si1 to Si4 to the internal circuit of the chip 100 according to the output signals So1 to So4 and the clock signals CK1 to CK4, So that the internal circuit of the chip 100 performs a loopback test of the PAM4 signal according to the test signals Si1 to Si 4.

Alternatively, in other embodiments of the present invention, in the test mode of the chip 100, the test circuit may transmit the output signal So1 and the output signal So2 (or the output signal So3 and the output signal So4) transmitted to the input terminal of the data selector 110 to the data sampler 121 and the data sampler 122 (or the data sampler 123 and the data sampler 124) via the signal transmission path 161 and the signal transmission path 162 (or the signal transmission path 163 and the signal transmission path 164). The data samplers 121 and 122 (or the data samplers 123 and 124) may output the test signal Si1 and the test signal Si2 (or the test signal Si3 and the test signal Si4) to the internal circuit of the chip 100 according to the output signal So1 and the output signal So2 (or the output signal So3 and the output signal So4) and another two clock signals having a phase difference of 180 degrees, So that the internal circuit of the chip 100 performs a loopback test of the NRZ signal according to the test signal Si1 and the test signal Si2 (or the test signal Si3 and the test signal Si 4).

Therefore, since the chip 100 of the present embodiment directly transmits the output signals So1 to So4 to the data samplers 121 to 124, compared to the PAM4 signal of the general external loopback test or the test signal generated by the PAM4 signal outputted by the data selector 110, the loopback test performed by the chip 100 of the present embodiment can reduce the data frequency of the test signal received by the back-end circuit of the chip 100, thereby reducing the requirements for the performance and data timing of the loopback test path. The data frequency of the output signals So 1-So 4 received by the data samplers 121-124 is one half of the frequency of the PAM2 signal and one quarter of the frequency of the PAM4 signal.

FIG. 2 is a flowchart of a chip testing method according to an embodiment of the invention. Referring to fig. 1 and 2, the chip 100 of the present embodiment may perform the following steps S210 to S230. In step S210, in the test mode, the chip 100 can transmit the output signals So 1-So 4 transmitted to the plurality of input terminals of the data selector 110 to the data samplers 121-124 through the test circuit via the signal transmission paths 161-164. In step S220, the chip 100 can output the test signals Si1 Si4 according to the output signals So1 to So4 and the clock signals CK1 to CK4 through the data samplers 121 to 124. In step S230, the internal circuit of the chip 100 may perform a loopback test according to the test signals Si 1-Si 4. Therefore, the chip 100 and the chip test method of the present embodiment can effectively implement the internal loopback test for the (high-speed) communication function (Pam4 signal or NRZ signal). In addition, as to the specific implementation and the extended implementation of the chip testing method of the present embodiment, reference may be made to the descriptions of other embodiments of the present invention to obtain sufficient teachings, suggestions and implementation descriptions, so that detailed descriptions are omitted herein.

Fig. 3 is a schematic diagram of an internal circuit of a chip according to a second embodiment of the present invention. Referring to FIG. 3, the chip 300 includes a data selector 310, a plurality of data samplers 321-324, a front end circuit 330, preamplifiers 341-344, an output circuit (Driver)350, and a test circuit. The front-end circuit 330 includes a Variable Gain Amplifier (VGA) 331, an Equalizer (EQ) 332, and an impedance matching Amplifier (Termination) 333. In the present embodiment, the data selector 310 has a plurality of input terminals and output terminals. The preamplifiers 341 to 344 are respectively coupled to a plurality of inputs of the data selector 310. The preamplifiers 341 to 344 may receive the output signals So1 to So4 provided by the internal circuits of the chip 300 and respectively transmit the voltage-amplified output signals to the input terminals of the data selector 310. The output terminal of the data selector 310 is coupled to the output circuit 350. In the present embodiment, the impedance matching amplifier 333 is coupled to the signal input terminal 302 of the chip 300. Equalizer 332 is coupled to impedance matching amplifier 333. Variable gain amplifier 331 is coupled between equalizer 332 and data samplers 321-324.

In the communication mode of the chip 300, the data selector 310 may modulate the voltage-amplified plurality of output signals according to the clock signals CK1 to CK4 to output the high-speed communication signal (Pam4 signal) to the output circuit 350, so that the output circuit 350 may transmit the high-speed communication signal (Pam4 signal) to the outside through the signal output terminal 301. In addition, another communication signal inputted from the signal input terminal 302 of the chip 300 can be adjusted by the signals of the impedance matching amplifier 333, the equalizer 332 and the variable gain amplifier 331 and then outputted to the data samplers 321 to 324, so that the data samplers 321 to 324 can demodulate another communication signal according to the clock signals CK1 to CK4, respectively, to output a plurality of input signals to the internal circuits of the chip 300. It should be noted that the chip 300 can also output and receive the Pam2 signal, and the operation mechanism can be similar to that described in the foregoing description of the Pam4 signal, and thus, the description thereof is omitted.

In the present embodiment, the test circuit has a plurality of signal transmission paths 361-364. The signal transmission paths 361-364 of the test circuit are coupled between the input terminals of the data selector 310 and the data samplers 321-324, respectively. In a test mode of the chip 300, the test circuit can transmit the voltage-amplified output signals transmitted to the input terminals of the data selector 310 to the data samplers 321 to 324 via the signal transmission paths 361 to 364. The data samplers 321 to 324 may output a plurality of test signals Si1 to Si4 to the internal circuit of the chip 300 according to the plurality of voltage-amplified output signals and the clock signals CK1 to CK4, so that the internal circuit of the chip 300 performs a loop-back test of the PAM4 signal according to the test signals Si1 to Si 4. It should be noted that the chip 300 may also perform the loopback test of the PAM2 signal, and the operation mechanism thereof may be similar to that described in the foregoing description of the PAM4 signal, and therefore, the description thereof is omitted.

Fig. 4 is a schematic diagram of an internal circuit of a chip according to a third embodiment of the present invention. Referring to FIG. 4, a chip 400 includes a data selector 410, a plurality of data samplers 421 to 424, a front-end circuit 430, preamplifiers 441 to 444, an output circuit 450, a test circuit, a signal output terminal 401, and a signal input terminal 402. The front-end circuit 430 includes a variable gain amplifier 431, an equalizer 432, and an impedance matching amplifier 433. However, the circuit coupling relationship and related operation manner of the data selector 410, the plurality of data samplers 421 to 424, the front-end circuit 430, the pre-amplifiers 441 to 444, the output circuit 450, the test circuit, the signal output terminal 401 and the signal input terminal 402 of the present embodiment can refer to the description of the embodiments of fig. 1 to 3 and are not repeated.

Compared to fig. 3, the test circuit of the present embodiment includes a plurality of signal transmission paths 461-464 and a plurality of Multiplexers (MUXs) 417-474. The multiplexers 417-474 have a first input terminal, a second input terminal, and an output terminal, respectively. The first input terminals of the multiplexers 417-474 are coupled to the input terminals of the data selector 410 via signal transmission paths 461-464, respectively. Second input terminals of the multiplexers 417-474 are coupled to the variable gain amplifier 431 of the front-end circuit 430, respectively, and output terminals of the multiplexers 417-474 are coupled to the data samplers 421-424, respectively.

It is noted that in the test mode of the chip 400, the multiplexers 471-474 can transmit the corresponding output signals to the data samplers 421-424 simultaneously or sequentially according to the switching signals SS 1-SS 4, so as to effectively prevent the output signals of the front-end circuit 430 from affecting the loopback test. In the communication mode, the multiplexers 471-474 can transmit the communication signals received by the front-end circuit 430 from the signal input terminal 402 of the chip 400 to the data samplers 421-424 according to the switching signals SS 1-SS 4, so as to effectively prevent the output signals of the test circuit from affecting the communication.

Fig. 5 is a schematic diagram of an internal circuit of a chip according to a fourth embodiment of the present invention. Referring to FIG. 5, a chip 500 includes a data selector 510, a plurality of data samplers 521-524, a front end circuit 530, pre-amplifiers 541-544, an output circuit 550, a test circuit, a signal output terminal 501, and a signal input terminal 502. The front-end circuit 530 includes a variable gain amplifier 531, an equalizer 532, and an impedance matching amplifier 533. However, the circuit coupling relationship and related operation manner of the data selector 510, the plurality of data samplers 521 to 524, the front-end circuit 530, the preamplifiers 541 to 544, the output circuit 550, the test circuit, the signal output terminal 501 and the signal input terminal 502 of the present embodiment can refer to the description of the embodiments of fig. 1 to 4 and are not repeated.

Compared with FIG. 3, the test circuit of the present embodiment includes a plurality of signal transmission paths 561-564 and a plurality of switch circuits 581-584. The switch circuits 581 to 584 have a first terminal and a second terminal, respectively. First terminals of the switch circuits 581-584 are coupled to input terminals of the data selector 510 via signal transmission paths 561-564, respectively. A plurality of second terminals of the switch circuits 581-584 are coupled to the data samplers 521-524, respectively. Also, the variable gain amplifier 531 of the front end circuit 530 may receive the operation signal EN.

It is noted that, in the test mode of the chip 500, the switch circuits 581-584 may be simultaneously or sequentially operated to be in a conducting state according to the control signals CS 1-CS 4 to respectively transmit the corresponding output signals to the data samplers 521-524, and the variable gain amplifier 531 of the front-end circuit 530 may be operated to be in a disable (disable) state according to the operation signal EN to effectively prevent the output signal of the variable gain amplifier 531 of the front-end circuit 530 from affecting the loopback test. Also, in the communication mode, the switch circuits 581 to 584 may be operated in an off state according to the control signals CS1 to CS4, and the variable gain amplifier 531 of the front-end circuit 530 may be operated in an enable state according to the operation signal EN to transfer the communication signal received by the front-end circuit 530 from the signal input terminal 502 of the chip 500 to the data samplers 521 to 524, and the test circuit output signal may be effectively prevented from affecting the communication.

Fig. 7 is an exemplary eye diagram of a loopback test corresponding to four-level pulse amplitude modulation in accordance with an embodiment of the present invention. The eye diagram 700 of the present embodiment may be used to show oscillometric results of the test signals Si 1-Si 4 of the chip 100 of the embodiment of fig. 1. In addition, the oscillometric results of the test signals Si 1-Si 4 of the chips 200-500 of the embodiments of FIGS. 2-5 can be similar to that of FIG. 7. Referring to fig. 1 and 7, the test signals Si 1-Si 4 obtained by the chip 100 of the present invention through the internal loopback test performed by the design of the test circuit may exhibit an eye diagram 700 as in fig. 7, and the eye width 701 may be 7.83073 picoseconds (ps). Compared with the internal or external loopback test result of the conventional chip shown in fig. 6, the eye pattern corresponding to the internal loopback test result of the chip 100 of the embodiment of fig. 1 may have a wider eye width. In other words, the test signals Si 1-Si 4 of the chip 100 of the embodiment of fig. 1 may have lower inter-symbol interference and noise than the test signals of the conventional chip test. Thus, the chip 100 of the embodiment of fig. 1 can perform an efficient internal loopback test for high-speed communication functions.

Fig. 8 is an exemplary eye diagram of a loopback test corresponding to four-level pulse amplitude modulation according to another embodiment of the present invention. The eye diagram 800 of the present embodiment may be used to show oscillometric results of the test signals Si 1-Si 4 of the chip 100 of the previous embodiment of fig. 1. In addition, the oscillometric results of the test signals Si 1-Si 4 of the chips 200-500 of the embodiments of FIGS. 2-5 can be similar to that of FIG. 8. Referring to fig. 1 and 8, test signals Si 1-Si 4 obtained by internal loopback testing of chip 100 of the present invention through the design of test circuitry may appear as eye diagram 800 of fig. 8. In this regard, it is assumed that the clock signals CK 1-CK 4 received by the data samplers 121-124 have a clock skew (clock skew) of, for example, 5 picoseconds (ps), and the eye widths 801 of the test signals Si 1-Si 4 of the present embodiment may be 7.4307 picoseconds (ps). In other words, compared to the internal or external loopback test result of the conventional chip shown in FIG. 6, even though the clock signals CK1 CK4 received by the data samplers 121-124 of the embodiment of FIG. 1 have clock skew of, for example, 5 picoseconds (ps), the eye pattern corresponding to the internal loopback test result of the chip 100 can still have a wider eye width. Thus, the chip 100 of the embodiment of fig. 1 can perform an efficient internal loopback test for high-speed communication functions.

Fig. 9 is an exemplary eye diagram of a loopback test corresponding to four-level pulse amplitude modulation of yet another embodiment of the present invention. The eye diagram 900 of the present embodiment may be used to show oscillometric results of the test signals Si 1-Si 4 of the chip 100 of the previous embodiment of fig. 1. In addition, the oscillometric results of the test signals Si 1-Si 4 of the chips 200-500 of the embodiments of FIGS. 2-5 can be similar to that of FIG. 9. Referring to fig. 1 and 9, under the condition of a particularly high frequency (e.g., over 100Gbps), the chip 100 may also perform a loopback test by turning on the signal transmission paths 161-164 by turns, wherein the loopback test is implemented by, for example, the multiplexer of fig. 4 or the switch circuit of fig. 5, So as to transmit the output signals So 1-So 4 with test patterns to the data samplers 121-124 simultaneously or sequentially. Alternatively, the output signals So 1-So 4 alternately output signals with PRBS test patterns, So that the output signals So 1-So 4 with test patterns can be sequentially transmitted to the plurality of input terminals of the data selector 110. For example, the output signal So1 is first switched to a signal having a test pattern, and the output signals So2 to So4 are first switched to a signal having a fixed pattern (e.g., a signal waveform corresponding to data "0" or data "1"). Then, the output signal So2 is switched to a signal having a test pattern, and the output signals So1, So3 to So4 are switched to signals having a fixed pattern. By analogy, in an internal loopback test of chip 100, the internal circuitry of chip 100 may receive 1/4 data frequency test signals as far as possible and may present an eye diagram 900 as in fig. 9, and eye width 901 may be 16.6781 picoseconds (ps). Therefore, the internal loopback test result of the chip 100 of the embodiment of fig. 1 can effectively avoid the influence of clock skew of the clock signals CK 1-CK 4, and can perform effective internal loopback test for high-speed communication function.

In summary, the chip and the chip testing method of the present invention can effectively reduce the influence of clock skew of the clock signal through the design of the signal transmission path, and can realize effective internal loopback testing for the high-speed communication function.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims (20)

1. A chip, comprising:

a data selector having a plurality of input terminals and output terminals;

a plurality of data samplers; and

a test circuit having a plurality of signal transmission paths, wherein the plurality of signal transmission paths of the test circuit are respectively coupled between the plurality of inputs of the data selector and the plurality of data samplers,

wherein in a test mode, the test circuit passes a plurality of output signals transmitted to the plurality of input terminals of the data selector to the plurality of data samplers via the plurality of signal transmission paths, and the plurality of data samplers output a plurality of test signals according to the plurality of output signals and a plurality of first clock signals.

2. The chip of claim 1, wherein the plurality of output signals comprises a first output signal and a second output signal corresponding to least significant bits, and comprises a third output signal and a fourth output signal corresponding to most significant bits.

3. The chip of claim 2, wherein the number of the plurality of first clock signals is four, and the four first clock signals have a phase difference of 90 degrees therebetween in sequence.

4. The chip of claim 1, wherein the plurality of output signals comprises a first output signal and a second output signal number.

5. The chip of claim 4, wherein the number of the plurality of first clock signals is two, and the two first clock signals have a phase difference of 180 degrees therebetween in sequence.

6. The chip of claim 1, wherein the plurality of output signals each have two amplitude levels,

in the test mode, the plurality of output signals are simultaneously or sequentially transmitted to the plurality of inputs of the data selector.

7. The chip of claim 1, wherein the data selector is configured to output a pulse amplitude modulation signal from the output of the data selector according to the plurality of output signals and a plurality of second clock signals in a communication mode.

8. The chip of claim 7, wherein the plurality of second clock signals are four in number and have a phase difference of 90 degrees therebetween in sequence, and wherein the pulse amplitude modulation signal has four amplitude levels.

9. The chip of claim 7, wherein the plurality of second clock signals is two in number and 180 degrees out of phase with each other, and wherein the pulse amplitude modulation signal has two amplitude levels.

10. The chip of claim 1, further comprising:

a front-end circuit coupled between a signal input of the chip and the plurality of data samplers.

11. The chip of claim 10, wherein the test circuit comprises:

a plurality of multiplexers each having a first input terminal, a second input terminal, and an output terminal,

wherein the first inputs of the multiplexers are respectively coupled to the inputs of the data selector via the signal transmission paths, the second inputs of the multiplexers are respectively coupled to the front-end circuits, and the outputs of the multiplexers are respectively coupled to the data samplers.

12. The chip of claim 11, wherein in the test mode, the plurality of multiplexers pass the plurality of output signals to the plurality of data samplers simultaneously or sequentially according to a plurality of switching signals,

in a communication mode, the multiplexers pass communication signals received by the front-end circuits from the signal input terminals of the chip to the data samplers according to the switching signals.

13. The chip of claim 10, wherein the test circuit comprises:

a plurality of switch circuits each having a first terminal and a second terminal,

wherein the first terminals of the switch circuits are coupled to the input terminals of the data selector via the signal transmission paths, respectively, and the second terminals of the switch circuits are coupled to the data samplers, respectively.

14. The chip of claim 13, wherein the front-end circuit receives an operational signal,

in the test mode, the plurality of switch circuits operate in an on state according to a plurality of control signals to simultaneously or sequentially transfer a plurality of output signals to the plurality of data samplers, and the front-end circuit operates in a disable state according to the operation signal,

in a communication mode, the plurality of switching circuits operate in an off state according to a plurality of control signals, and the front-end circuit operates in an enable state according to the operation signal.

15. The chip of claim 10, wherein the front-end circuit comprises:

an impedance matching amplifier coupled to the signal input terminal of the chip;

an equalizer coupled to the impedance matching amplifier; and

a variable gain amplifier coupled between the equalizer and the plurality of data samplers.

16. The chip of claim 1, further comprising:

a plurality of pre-amplifiers respectively coupled to the plurality of input terminals of the data selector,

wherein the plurality of preamplifiers receive the plurality of output signals and respectively transmit the voltage-amplified plurality of output signals to the plurality of input terminals of the data selector.

17. A chip testing method, wherein the chip comprises a data selector and a plurality of data samplers, and wherein the chip further comprises a testing circuit, and a plurality of signal transmission paths of the testing circuit are respectively coupled between a plurality of inputs of the data selector and the plurality of data samplers, wherein the chip testing method comprises:

in a test mode, passing a plurality of output signals transmitted to the plurality of inputs of the data selector to the plurality of data samplers by the test circuit via the plurality of signal transmission paths;

outputting, by the plurality of data samplers, a plurality of test signals from the plurality of output signals and a plurality of first clock signals; and

and performing loopback test according to the plurality of test signals.

18. The chip testing method of claim 17, wherein the plurality of output signals includes a first output signal and a second output signal corresponding to least significant bits, and includes a third output signal and a fourth output signal corresponding to most significant bits,

wherein the number of the plurality of first clock signals is four, and wherein the four first clock signals have a phase difference of 90 degrees between them in sequence.

19. The chip testing method according to claim 17, wherein the plurality of output signals includes a first output signal and a second output signal number,

wherein the number of the plurality of first clock signals is two, and the two first clock signals have a phase difference of 180 degrees between the two first clock signals in sequence.

20. The chip testing method according to claim 17, wherein each of the plurality of output signals has two amplitude levels,

in the test mode, the plurality of output signals are simultaneously or sequentially transmitted to the plurality of inputs of the data selector.

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