CN113722261A - Method for expanding chip selection number and enhancing flexibility of read-write response time by SPI - Google Patents
Method for expanding chip selection number and enhancing flexibility of read-write response time by SPI Download PDFInfo
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Abstract
The invention discloses a method for expanding the number of chip selections and enhancing the flexibility of read-write response time by an SPI. The system comprises a master device, an SPI controller, a control word processing module and a slave device. The system adopts SPI protocol to communicate. In order to realize the chip selection expansion, the control word is expanded, and the chip selection Byte of the N Byte is added in front of the original control word. And after receiving the control instruction of the MOSI port, the control word processing module decodes the chip selection information and pulls down the corresponding chip selection port. In order to increase the response time of the slave device, an invalid control byte is added after the address byte when the SPI controller sends a read command. The slave device sends a data stream to the master device on the next clock cycle of the invalid control byte. By adopting the method of the invention, the chip selection number can be expanded to 256 multiplied by N, the response time of the slave device is increased, and the stability and the flexibility of SPI communication are improved.
Description
Technical Field
The invention belongs to the field of SPI communication, and particularly relates to a method for expanding the number of chip selects and enhancing the flexibility of read-write response time by an SPI.
Background
SPI (Serial Peripheral Interface) is a high-speed full-duplex communication bus. The printed circuit board only occupies four lines on the pins of the chip, thereby saving the pins of the chip and simultaneously saving the space for the layout of the printed circuit board. Due to this simple and easy-to-use nature, more and more chips are nowadays integrating such communication protocols.
The SPI operates in a master-slave manner, and this mode of operation typically has one master device and one or more slave devices. The SPI has no plaintext standard, is just a factual standard, only carries out general abstract description on the realization of communication operation, and chip manufacturers and driver developers communicate the details of realization through data sheets and application nodes.
SPI communication has two problems:
the first problem is that: the SPI interface signals include SCLK, MOSI, MISO, and CS. The CS is a slave chip select signal, and N chip select ports are required to connect N slaves. Currently, only 4 slave devices can be chip-selected by one SPI channel. When the number of slave devices is large, the SPI cannot achieve normal communication.
The second problem is that: when reading operation is carried out through the SPI, the slave device is required to send data to the master device in the next clock cycle when the address byte ends, and the slave device has no response time between receiving control information and sending data information, so that timing errors are easy to occur.
Disclosure of Invention
The invention aims to provide a method for expanding the number of chip selections and enhancing the flexibility of read-write response time by an SPI (serial peripheral interface), so as to solve the technical problems that when a plurality of slave devices are arranged, the SPI cannot realize normal communication, and the slave devices do not have response time between receiving control information and sending data information, so that time sequence errors are easy to occur.
In order to solve the technical problems, the specific technical scheme of the invention is as follows:
a SPI expands the chip selection number and strengthens reading and writing the method of the response time flexibility, including main equipment, SPI controller, control word processing module and slave unit, read process and write process;
the read process includes the steps of:
step 5, the slave device receives the valid control information, namely the mode selection byte and the address byte, and then carries out corresponding reading operation in the next clock cycle after the invalid control byte is ended, namely, the prepared data is transmitted to the control word processing module through the MISO port;
step 6, after receiving the read data, the control word processing module transmits the data to a MISO port of the SPI controller through a MISO _ o port;
step 7, the main device receives the read data and completes one-time reading operation;
the writing process comprises the steps of:
step a, the master device sends a control signal corresponding to a write command and data needing to be written into the slave device through the MOSI by using the SPI controller, wherein the control signal comprises a chip selection byte, a mode selection byte and an address byte; the chip selection byte is used for indicating the serial number of the slave equipment selected by the master equipment for communication, the mode selection byte is used for indicating that the control signal is a write command, and the address byte is used for addressing;
b, the control word processing module decodes the chip selection bytes in the control information and analyzes that the master device selects the slave device for communication;
c, controlling the word processing module to pull down the chip selection port corresponding to the communication slave equipment according to the analyzed chip selection information;
d, controlling the word processing module to send the mode selection byte, the address byte and the data needing to be written into the slave equipment to an MOSI port of the slave equipment through a Dout port;
and e, the slave equipment receives the mode selection byte, the address byte and the data information, carries out addressing according to the address information in the address byte, writes the corresponding data information and completes one-time writing operation.
Further, the specific step of step 3 in the reading process is that a chip selection port CS of each slave device is connected to one chip selection port of the control word processing module; and the control word processing module performs decoding operation on the chip selection byte sent by the master device, one chip selection port is correspondingly pulled up according to the data in the chip selection byte, and the slave device connected with the pulled-up chip selection port is the object selected by the master device for communication.
Further, the specific step of step c in the writing process is that the chip select port CS of each slave device is connected to one chip select port of the control word processing module, the control word processing module performs decoding operation on the chip select byte sent by the master device, one chip select port is pulled up according to data in the chip select byte, and the slave device connected to the pulled-up chip select port is the object selected by the master device for communication.
The method for expanding the chip selection number and enhancing the flexibility of the read-write response time by the SPI has the following advantages:
1. the chip selection information is transmitted by adding the chip selection bytes into the control signal, and the chip selection port is not used for chip selection. The method has the advantages that the ports (the number of pins occupied by the SPI communication is reduced) can be saved, the chip selection number can be increased, and the stability of the SPI communication is improved.
2. The invention adds an invalid control byte to the control signal. The invalid control byte does not convey any information, that is, the slave device does not need to process the invalid control byte during the time when the invalid control byte is received, but uses the time as the response time of the read instruction. The larger the number of bytes of the invalid control word, the longer the response time of the slave device. The advantages are that the response time of the slave device is increased, and the stability of SPI communication are improved.
Drawings
FIG. 1 is a system framework diagram of the present invention;
fig. 2 is a control word of the chip select extension method when the slave device is the SPI flash chip M25P64 in the embodiment of the present invention;
FIG. 3 is a timing diagram illustrating a chip select expansion method when the slave device is the SPI flash chip M25P64 according to an embodiment of the present invention;
fig. 4 is a control word of the method for enhancing read-write response time when the slave device is an SPI flash chip M25P64 in the embodiment of the present invention;
FIG. 5 is a timing diagram illustrating a method for enhancing read/write response time when the slave device is an SPI flash chip M25P64 according to an embodiment of the present invention;
Detailed Description
In order to better understand the purpose, structure and function of the present invention, the following describes the method for extending the number of chip selects and enhancing the flexibility of read/write response time in the SPI according to the present invention in detail with reference to the accompanying drawings.
As shown in fig. 1, the system includes a master device, an SPI controller, a control word processing module, and a slave device. The SPI controller is a module used for SPI communication in the master device and mainly used for sending SPI commands to the slave device and receiving data sent to the master device by the slave device. The control word processing module is mainly used for processing the control signal sent by the master device, decoding chip selection information and sending the control signal except chip selection bytes to the MOSI port of the slave device. Wherein, mosi (master Out slave) is a port for data output of the master device and data input of the slave device, and is used for data transmission from the master device to the slave device; miso (master In Slave out) is a port for data input and output of the master device, and is used for data transmission from the Slave device to the master device; sclk (spi clock) is a clock signal generated by the master device; CS: a device select line (chip select) controlled by the master device and in a selected state when a slave chip select signal is input to a high level.
The meaning of these four ports on the SPI controller:
mosi (master Out slave): a master data output port.
Miso (master In Slave out): a master data input port.
SCLK (SPI clock): a clock signal generated by the master device.
CS: the device select line (chip select), which is used as an enable signal for the control word processing block, controls whether the control word processing block is enabled.
The meaning of the four ports on the left side of the control word processing module:
SCLK (SPI clock): a clock signal generated by the master device.
MISO _ o: and a read data output port. The control word processing module transmits data received from the slave device to the master device through this port.
Din: input ports for read and write commands and data.
EN: and enabling the port, and controlling the word processing module to normally work when EN is pulled high.
Meaning of the right port of the control word processing module:
MISO _ i: and a read data input port. The control word processing module receives data from the slave device through this port.
Dout: and an output port for reading and writing the command and the data.
CS _ n: and chip selection ports.
The meaning of these four ports on the slave:
mosi (master Out Slave in): slave data input ports.
Miso (master In Slave out): a slave device data output port.
SCLK (SPI clock): a clock signal generated by the master device.
CS: a device select line (chip select) that can communicate with the master device through the SPI only when the chip select signal is pulled high.
The method for expanding the chip selection number and enhancing the flexibility of the read-write response time by the SPI comprises a read process and a write process.
Wherein the reading process comprises the steps of:
and 2, the control word processing module decodes the chip selection bytes by using a decoder. The input of the decoder is chip selection byte, and the output of the decoder is connected with the chip selection signal output port of the control word processing module, namely CS1, CS 2. The decoder can be used for decoding the chip selection information and analyzing the slave equipment selected by the master equipment for communication;
step 5, the slave device receives the valid control information, namely the mode selection byte and the address byte, and then carries out corresponding reading operation in the next clock cycle after the invalid control byte is ended, namely, the prepared data is transmitted to the control word processing module through the MISO port;
step 6, after receiving the read data, the control word processing module transmits the data to a MISO port of the SPI controller through a MISO _ o port;
and 7, receiving the read data by the main equipment to finish one-time reading operation.
The writing process comprises the following steps:
step 1: and the master device sends a control signal corresponding to the write command and data needing to be written into the slave device through the MOSI by using the SPI controller. The control signals include a chip select byte, a mode select byte, and an address byte. The chip selection byte is used for indicating the serial number of the slave equipment selected by the master equipment for communication, the mode selection byte is used for indicating that the control signal is a write command, and the address byte is used for addressing;
step 2: and the control word processing module decodes the chip selection bytes by using a decoder. The input of the decoder is chip selection byte, and the output of the decoder is connected with the chip selection signal output port of the control word processing module, namely CS1, CS 2. The decoder can be used for decoding the chip selection information and analyzing the slave equipment selected by the master equipment for communication;
and step 3: and the control word processing module pulls down the chip selection port corresponding to the communication slave equipment according to the analyzed chip selection information. The chip select port (i.e. CS) of each slave device is connected to one chip select port of the control word processing module. The control word processing module carries out decoding operation on chip selection bytes sent by the main equipment, one chip selection port is correspondingly pulled up according to data in the chip selection bytes, and the slave equipment connected with the pulled-up chip selection port is an object selected by the main equipment for communication;
and 4, step 4: the control word processing module sends the mode selection byte, the address byte and the data needing to be written into the slave equipment to an MOSI port of the slave equipment through a Dout port;
and 5: a mode select byte, an address byte, and data information are received from the device. The slave device carries out addressing according to the address information in the address byte, writes in corresponding data information and completes one-time writing operation;
the reason why an invalid control byte is needed for a read operation, but not for a write operation, is that: while the slave device requires a certain response time when performing a read operation, it does not require a response time when performing a write operation.
The first embodiment of the present invention:
aiming at the read operation, the method comprises the following steps:
1. the SPI controller in the master device sends control signals to the Din port of the control word processing module via the MOSI port. The chip selection port occupied by the existing SPI controller can be simplified into an enabling signal port of a control word processing module, if the main equipment is connected with 8 slave equipment, after the scheme is applied, the chip selection port of the main equipment occupied by the system is reduced from 8 to 1, and pins of a chip are greatly saved.
2. If the number of slave devices is less than 256, the chip select Byte length can be set to 1 Byte. Taking the slave SPI flash chip M25P64 as an example, the format of the control word containing the chip selection information is shown in fig. 2. The control signal includes a 1Byte chip select Byte, a 1Byte mode select Byte, a 3Byte address Byte and a 1Byte disable control Byte.
3. Fig. 3 is a corresponding timing diagram. And after receiving the control information, the control word processing module decodes the chip selection bytes. And analyzing that the master device selects the slave device for communication. And pulls down the chip select signal that the control word processing module is connected to the slave device. For example, the chip select byte data sent by the master device is 0x02, which indicates that the slave device serial number of the master device selecting communication is 2. The chip select port CS2, which controls the word processing module to connect to the slave device with sequence number 2, is pulled low on the next clock cycle. The control word processing module then transmits the mode select byte, the address byte and the invalid control byte to the MOSI of the slave device via the Dout port.
4. The slave M25P64 receives the valid control information, i.e. the mode select byte and the address byte, and then performs a corresponding read operation in the next clock cycle at the end of the invalid control byte, i.e. transfers the prepared data to the control word processing module via the MISO port. The invalid control bytes do not convey any information. After adding the invalid control byte, the slave device does not need to process the invalid control byte during the period of receiving the control byte, but uses the period as the response time of the read instruction. The problem that slave equipment does not have response time in original SPI communication is solved to improve SPI communication's stability and stability.
5. And after receiving the read data, the control word processing module transmits the data to the MISO port of the SPI controller through the MISO _ o port.
6. And the main equipment receives the read data and completes one read operation. The SPI single channel chip select number can be increased from 4 to 256 by adding a 1Byte chip select Byte and a 1Byte invalid control Byte. And the increased slave response time in a read operation is equal to the transmission time of the 1Byte character.
For a write operation, the method comprises the following steps:
1. the SPI controller in the master device sends control signals and data that needs to be written to the slave device to the Din port of the control word processing module via the MOSI port. The chip select port occupied by the original SPI controller can be simplified into an enabling signal port of a control word processing module. If the master device is connected with 8 slave devices, the number of the master device chip selection ports occupied by the system is reduced from 8 to 1 after the scheme is applied, and pins of a chip are greatly saved.
2. If the number of slave devices is less than 256, the chip select Byte length can be set to 1 Byte. Taking the slave SPI flash chip M25P64 as an example, the format of the control word containing the chip selection information is shown in fig. 4. The control signal includes a 1Byte chip select Byte, a 1Byte mode select Byte, and a 3Byte address Byte.
3. Fig. 5 is a corresponding timing diagram. And after receiving the control information, the control word processing module decodes the chip selection bytes. And analyzing that the master device selects the slave device for communication. And pulls down the chip select signal that the control word processing module is connected to the slave device. For example, the chip select byte data sent by the master device is 0x02, which indicates that the slave device serial number of the master device selecting communication is 2. The chip select port CS2, which controls the word processing module to connect to the slave device with sequence number 2, is pulled low on the next clock cycle. The control word processing module then transmits the mode select byte, the address byte and the data to be written to the slave device to the MOSI of the slave device via the Dout port.
4. After receiving the mode selection byte and the address byte, the slave device M25P64 addresses according to the address information in the address byte, writes the corresponding data information, and completes the write operation once. The SPI single channel chip select number can be increased from 4 to 256 by adding a 1Byte chip select Byte.
It is to be understood that the present invention has been described with reference to certain embodiments, and that various changes in the features and embodiments, or equivalent substitutions may be made therein by those skilled in the art without departing from the spirit and scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the essential scope thereof. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed, but that the invention will include all embodiments falling within the scope of the appended claims.
Claims (3)
1. A SPI expands the chip selection number and enhances the read-write response time flexible method, including master equipment, SPI controller, control word processing module and slave unit, characterized by, including reading process and writing process;
the read process includes the steps of:
step 1, the main device sends a control signal corresponding to a read instruction through an MOSI (serial peripheral interface) by utilizing an SPI (serial peripheral interface) controller, wherein the control signal comprises a chip selection byte, a mode selection byte, an address byte and an invalid control byte; the chip selection byte is used for indicating the serial number of the slave equipment selected by the master equipment for communication, the mode selection byte is used for indicating that the control signal is a read instruction, the address byte is used for addressing, and the invalid control byte does not transmit any valid information;
step 2, the control word processing module decodes the chip selection bytes in the control information by using a decoder and analyzes the slave equipment selected by the master equipment for communication;
step 3, controlling the word processing module to pull down the chip selection port corresponding to the communication slave equipment according to the analyzed chip selection information;
step 4, the control word processing module sends the mode selection byte, the address byte and the invalid control byte to an MOSI port of the slave equipment through a Dout port;
step 5, the slave device receives the valid control information, namely the mode selection byte and the address byte, and then carries out corresponding reading operation in the next clock cycle after the invalid control byte is ended, namely, the prepared data is transmitted to the control word processing module through the MISO port;
step 6, after receiving the read data, the control word processing module transmits the data to the MISO end of the SPI controller through the MISO _ o port;
step 7, the main device receives the read data and completes one-time reading operation;
the writing process comprises the steps of:
step a, the master device sends a control signal corresponding to a write command and data needing to be written into the slave device through the MOSI by using the SPI controller, wherein the control signal comprises a chip selection byte, a mode selection byte and an address byte; the chip selection byte is used for indicating the serial number of the slave equipment selected by the master equipment for communication, the mode selection byte is used for indicating that the control signal is a write command, and the address byte is used for addressing;
b, the control word processing module decodes the chip selection bytes in the control information and analyzes that the master device selects the slave device for communication;
c, controlling the word processing module to pull down the chip selection port corresponding to the communication slave equipment according to the analyzed chip selection information;
d, controlling the word processing module to send the mode selection byte, the address byte and the data needing to be written into the slave equipment to an MOSI port of the slave equipment through a Dout port;
and e, the slave equipment receives the mode selection byte, the address byte and the data information, carries out addressing according to the address information in the address byte, writes the corresponding data information and completes one-time writing operation.
2. The method according to claim 1, wherein the specific step of step 3 in the read process is that a chip select port CS of each slave device is connected to a chip select port of a control word processing module; and the control word processing module performs decoding operation on the chip selection byte sent by the master device, one chip selection port is correspondingly pulled up according to the data in the chip selection byte, and the slave device connected with the pulled-up chip selection port is the object selected by the master device for communication.
3. The method according to claim 1, wherein the specific step of step c in the writing process is that a chip select port CS of each slave device is connected to a chip select port of the control word processing module; and the control word processing module performs decoding operation on the chip selection byte sent by the master device, one chip selection port is correspondingly pulled up according to the data in the chip selection byte, and the slave device connected with the pulled-up chip selection port is the object selected by the master device for communication.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115543898A (en) * | 2022-09-26 | 2022-12-30 | 南京国电南自维美德自动化有限公司 | Communication bus expansion method and device |
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