CN113722254B - Multi-host communication bus system suitable for industrial control site - Google Patents
Multi-host communication bus system suitable for industrial control site Download PDFInfo
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- CN113722254B CN113722254B CN202110567753.0A CN202110567753A CN113722254B CN 113722254 B CN113722254 B CN 113722254B CN 202110567753 A CN202110567753 A CN 202110567753A CN 113722254 B CN113722254 B CN 113722254B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
- Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
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Abstract
The invention discloses a multi-host communication bus system suitable for an industrial control field, which is based on a plurality of groups of differential signals, uses a group of differential signal transmission clocks and uses one or more groups of signals to transmit data, and can transmit data in a parallel mode; the bus of the invention transmits the clock of the sender, so that the receiver does not need to recover and extract the clock signal from the data signal, and the data can be received only by using a common shift register, thereby reducing the hardware complexity of signal synchronization and increasing the length of the longest transmission unit. When the bus is used for data transmission, the hardware design is simpler, and multiplexing can be performed on the basis of the existing hardware.
Description
Technical Field
The invention belongs to the technical field of bus communication, and particularly relates to a multi-host communication bus system suitable for an industrial control site.
Background
The industrial control bus system is a bus system widely used in industrial control system sites, is mainly optimized for industrial control sites, and has stronger anti-interference performance. The industrial control buses widely used at present comprise RS232, RS485, CAN and the like. Wherein RS232 is a point-to-point communication bus, RS485 is a single-master multi-slave bus based on differential signals, and CAN is a multi-master multi-slave bus of differential signals.
With the increase of the complexity of industrial field devices, the point-to-point, single-master and multi-slave buses cannot meet new requirements in redundancy and connection complexity, so that more and more industrial control systems require the use of multi-master and multi-slave buses, but serial multi-master and multi-slave buses such as CAN belong to serial transmission buses, and the problems of low transmission efficiency, synchronous requirement of a receiver, short longest transmission word length and the like exist.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provide a multi-host communication bus system suitable for an industrial control field, which can transmit data in a parallel mode based on a plurality of groups of differential signals and can transmit data with longer length without synchronizing signals of slaves. When the bus is used for data transmission, the hardware design is simple, and multiplexing can be performed on the basis of the existing hardware.
The invention is realized by the following technical scheme:
a multi-host communication bus system suitable for industrial control sites:
using a plurality of groups of differential signals as a physical layer transmission mode, wherein '1' is dominant potential, and when a voltage difference exists on a differential bus, the differential bus is regarded as data '1'; "0" is a recessive potential, which is considered to be data "0" when there is no voltage difference on the differential bus, and will be maintained when there is no external drive on the bus;
transmitting data using one or more sets of signals using a set of differential signaling clocks;
the data frame transmitting process comprises the following steps: when the host prepares to send data, firstly monitoring whether the bus is in an idle state, if so, driving a clock signal line by using a standard clock, and sending data '0' of N1 clock cycles to the bus as a frame starting part; in the next N1 clock cycles, the host monitors whether the own sending signal is consistent with the receiving signal through an exclusive OR gate, if so, the host indicates that no conflict exists on the bus, if not, the host with larger phase difference with the local clock signal occupies the bus, and the host monitoring the event firstly gives up the occupation of the bus and goes to a monitoring state; if the host keeps occupying the bus for N1 clock cycles continuously, the host continues to drive the clock signal to transmit N2 cycle data 1 to the bus, then sequentially transmits the local address and the destination address, in this stage, the host starts the exclusive OR check when transmitting the local address and the destination address, if the local drive signal is inconsistent with the actual signal of the bus, the host with smaller phase difference between the clock signal and the host is occupying the bus, the host still keeps occupying the bus correctly when transmitting information, otherwise, the host gives up the control right to the bus; if the host still has control over the bus, the host will transmit the frame information portion for the next N3 cycles; after the frame information part is transmitted, the host adjusts the clock to be a high-speed clock, and the effective data is rapidly transmitted under the clock; after the effective data transmission is completed, the host switches back to the standard clock and transmits the check code part under the clock; finally, the host drives the clock line for N4 clock cycles, samples bus data according to the sampling edge of the slave, and is stored in a buffer as a frame response part;
data frame receiving process: when the slave receives data, if transmission of continuous data '0' occurs for more than N1/4 clock cycles, which means that the transmission is started, the slave will monitor continuously until N2 periodic data '1' occurs on the bus, at which time the slave considers that the correct frame start part has been received, and prepares to accept further frame data; if the slave receives the correct frame start part, the address part, the frame information part, the data part and the check part are sequentially received in a plurality of next clock cycles, when the data transmission of the last clock of the check part is finished, the slave starts to drive the data line part of the bus and drives response information to the bus under the clock drive of the host, and then the slave sets a receiving flag bit and further processes the data by a circuit driven by a local clock.
In the above technical solution, during the process of transmitting the frame information portion, the data portion, and the check code portion, the master uses the same clock edge as the slave samples to perform collision monitoring, and if it is detected that the data on the bus is inconsistent with the drive, the master will give up controlling the bus.
In the above technical solution, when the host monitors that the bus is idle for more than 3×n1+1 maximum clock cycles, it is determined that the bus is in an idle state.
In the above technical solution, during the receiving process of the slave, the local clock consistent with the standard clock is always enabled to monitor, when the clock bus has no signal transmission for N1+1 clock cycles continuously, the current transmission frame of the bus is considered to be abandoned or in error, and the receiving of the frame is abandoned.
In the above technical solution, if the slave receives the correct frame start part, the address part will be received and whether the slave is the receiving end will be determined in the next several clock cycles.
In the above technical solution, the slave will continue to receive the frame information portion, the data portion and the check portion, whether or not it is the receiving end.
In the above technical solution, the slave will continuously use the clock provided by the differential bus in the receiving process, when the data transmission of the last clock of the verification part is completed, if the slave is the receiving end, the slave starts to drive the data line part of the bus, and drives the response information to the bus under the clock drive of the host, and then the slave sets the receiving flag bit, and further data processing is performed by the circuit driven by the local clock.
In the above technical solution, the bus data frame of the present invention is divided into a start portion, an address portion, a frame information portion, a data portion, a check portion and a response portion, wherein the start portion is used for indicating the generation of a new frame in the bus; the address part is used for representing the source address and the destination address of the frame; the frame information part is used to represent the type, length and other necessary additional information of the frame; the data portion represents data to be actually transmitted; the checking part is a group of checking information generated by calculating an address part, a frame information part and a data part of the frame and is used for checking the integrity of the frame; the response part is used for reporting the receiving condition to the host computer from the slave computer.
In the technical scheme, the bus transmits data by using the rising edge or the falling edge of the clock, and when the host changes data on the rising edge of the clock, the slave samples data on the falling edge of the clock to become a rising edge mode; when the master machine changes data on the clock falling edge, the slave machine samples data on the clock rising edge, and the slave machine becomes a falling edge mode.
In the above technical solution, the clock used in the present invention includes a standard clock and a high-speed clock, the standard clock is a common prescribed bus transmission clock, each master and slave keep consistent, the high-speed clock is used when data transmission is performed, each host may not be consistent, but the frequency of the clock must be higher than that of the standard clock.
The invention has the advantages and beneficial effects that:
the invention is based on a plurality of groups of differential signals, can transmit data in a parallel mode, and can transmit data with longer length without the need of synchronizing signals by a slave machine. When the bus is used for data transmission, the hardware design is simpler, and multiplexing can be performed on the basis of the existing hardware.
Because the bus of the invention transmits the clock of the sender (host), the receiver (slave) does not need to recover and extract the clock signal from the data signal, and can realize the data receiving only by using a common shift register, thereby reducing the hardware complexity of signal synchronization and increasing the length of the longest transmission unit.
Meanwhile, as the data bus is expandable, the bus can be easily expanded to various bandwidths such as 4bit, 8bit, 16bit, 32bit and the like, and can meet the requirements of different transmission rates.
Drawings
FIG. 1 is a diagram of the physical layer of a bus in accordance with the present invention;
FIG. 2 is a data link layer frame structure of the bus of the present invention;
FIG. 3 is a data frame transmission process of the bus of the present invention;
FIG. 4 is a diagram illustrating a data frame reception process of the bus of the present invention;
fig. 5 is a schematic diagram of a carrier sense arbitration scheme of the bus of the present invention;
fig. 6 is a carrier sense collision scenario 1 of the inventive bus;
fig. 7 is a carrier sense collision case 2 of the bus of the present invention;
fig. 8 is a carrier sense collision scenario 3 of the inventive bus.
Other relevant drawings may be made by those of ordinary skill in the art from the above figures without undue burden.
Detailed Description
In order to make the person skilled in the art better understand the solution of the present invention, the following describes the solution of the present invention with reference to specific embodiments.
The invention uses a plurality of groups of differential signals as a physical layer transmission mode, wherein '1' is dominant potential, and when a voltage difference exists on a differential bus, the differential bus is regarded as data '1'; "0" is a recessive potential and is considered to be a data "0" when there is no voltage difference on the differential bus. When the bus is not externally driven, the recessive potential will be maintained.
Referring to fig. 1, the present invention uses a set of differential signaling clocks to transfer data using one or more sets of signals for the physical layer architecture of the bus of the present invention. Wherein TX is connected with the sending signal of the data link layer, RX is connected with the receiving signal of the data link layer, BUS+ and BUS-are respectively connected with the anode and the cathode of the differential BUS. In particular, the number of differential signal groups for transmitting data is scalable, but is fixed for a certain usage environment.
Referring to fig. 2, a frame structure of a data link layer of the bus of the present invention is divided into a start portion, an address portion, a frame information portion, a data portion, a check portion, and a response portion. Wherein the initial portion is used to represent the generation of a new frame on the bus; the address part is used for representing the source address and the destination address of the frame; the frame information part is used for representing the type, length and other necessary additional information of the frame; the data portion represents data to be actually transmitted; the checking part is a group of checking information generated by calculating the address part, the frame information part and the data part of the frame and is used for checking the integrity of the frame; the response part is used for reporting the receiving condition to the host computer from the slave computer.
The bus transmits data by using the rising edge or the falling edge of the clock, and when the data change is carried out on the rising edge of the clock by the host, the data sampling is carried out on the falling edge of the clock by the slave, so that the bus becomes a rising edge mode; when the master changes data on the clock falling edge, the slave samples data on the clock rising edge, and becomes a falling edge mode.
The clock used in the invention comprises a standard clock and a high-speed clock, wherein the standard clock is a bus transmission clock which is uniformly regulated, each master and slave keeps consistent, the high-speed clock is used for data transmission, and each host can be inconsistent but the frequency of the high-speed clock is higher than that of the standard clock.
The bus of the invention adopts a carrier sense mode to carry out competition president. Referring to fig. 3, in the data frame transmission process of the bus of the present invention, when the host prepares to transmit data, firstly, listening to the bus until the bus is found to be idle for more than 3×n1+1 maximum clock cycles, then driving the clock signal line using the standard clock, and transmitting data "0" of N1 clock cycles to the bus as a frame start portion; the host monitors whether own sending signals and receiving signals are consistent or not through an exclusive-or gate in the next N1 clock cycles, if so, no conflict exists on the bus, if not, a host with larger phase difference with the local clock signals occupies the bus, and the host which monitors the event first gives up the occupation of the bus and goes to a monitoring state; if the host keeps occupying the bus for N1 clock cycles continuously, the host continues to drive the clock signal to transmit N2 cycle data 1 to the bus, then sequentially transmits the local address and the destination address, in the stage, the host starts the exclusive OR check when transmitting the local address and the destination address, if the local drive signal is inconsistent with the bus actual signal, the host with smaller clock signal and the host also occupies the bus, the host still keeps occupying the bus when transmitting information, otherwise, the host gives up the control right to the bus; if the host still has control over the bus, the host will transmit the frame information portion, including frame type and frame length, for the next N3 cycles; after the frame information part is transmitted, the host adjusts the clock to be in a high-speed clock mode, and effective data is rapidly transmitted under the clock; after the effective data transmission is completed, the host switches back to the standard clock and transmits the check code part under the clock; finally, the master drives the clock line for N4 clock cycles, samples the bus data according to the slave sampling edge, and stores the bus data in the buffer as a frame response part. During the transmission of the frame information part, the data part and the check code part, the master uses the same clock edge as the slave samples to perform conflict monitoring, and if the data on the bus is detected to be inconsistent with the drive, the master gives up the control on the bus.
Referring to fig. 4, in the data frame receiving process of the bus of the present invention, when the slave receives data, it listens to the bus data based on the clock of the differential bus, and at any time, a transmission of continuous data "0" occurs for more than N1/4 clock cycles, indicating that the transmission has started, the slave will continue to listen until N2 cycles of data "1" appear on the bus, at which time the slave considers that the correct frame start has been received, ready to accept further frame data; if the slave receives the correct frame start part, it will receive the address part, frame information part, data part and check part in turn in the next several clock cycles, the clock provided by the differential bus will be used continuously in the receiving process, when the data transmission of the last clock of the check part is completed, the slave starts to drive the data line part of the bus and drives the response information to the bus under the clock drive of the host, then the slave will set the receiving flag bit, and the circuit driven by the local clock will process further data.
During the receiving process of the slave, a local clock which is basically consistent with the standard clock is always enabled to monitor (a certain offset is allowed to exist), when the clock bus has no signal transmission for the continuous N1+1 clock cycles, the current transmission frame of the bus is considered to be abandoned or has errors, and the receiving of the frame is abandoned. If the slave receives the correct frame start part, it will receive the address part and determine if it is the receiving end for the next few clock cycles. Whether the slave is a receiving end or not, the slave continuously receives the frame information part, the data part and the check part, the clock provided by the differential bus is continuously used in the receiving process, when the data transmission of the last clock of the check part is finished, if the slave is the receiving end, the slave starts to drive the data line part of the bus, response information is driven onto the bus under the clock drive of the host, then the slave receives the flag bit in a bit position, and a circuit driven by a local clock carries out further data processing.
Fig. 5 is a carrier sense arbitration method of the bus of the present invention, and fig. 6, fig. 7, and fig. 8 are three carrier sense arbitration processes of the bus of the present invention. The first and second cases are applicable to the process of transmitting frame start and address parts by the host, the host asynchronously monitors whether own sending signals and receiving signals are consistent through an exclusive or gate, if so, no conflict exists on the bus, otherwise, the conflict exists, and the bus data and the host which expects to be incorrect lose control over the bus. The third condition is suitable for the process host of the host transmission frame type, data and verification part, and monitors whether own sending signals and receiving signals are consistent or not according to the sampling edges of the slaves through an exclusive or gate, if so, no conflict exists on the bus, otherwise, the existence of the conflict is indicated, and the bus data and the host which expects to be incorrect lose control right on the bus.
While the invention has been described by way of example, it should be noted that any simple variations, modifications, or other equivalent which would not take the inventive effort by those skilled in the art will fall within the scope of the invention without departing from the gist of the invention.
Claims (10)
1. A multi-host communication bus system suitable for an industrial control site, characterized in that:
using a plurality of groups of differential signals as a physical layer transmission mode, wherein '1' is dominant potential, and when a voltage difference exists on a differential bus, the differential bus is regarded as data '1'; "0" is a recessive potential, which is considered to be data "0" when there is no voltage difference on the differential bus, and will be maintained when there is no external drive on the bus;
transmitting data using one or more sets of signals using a set of differential signaling clocks;
the data frame transmitting process comprises the following steps: when the host prepares to send data, firstly monitoring whether the bus is in an idle state, if so, driving a clock signal line by using a standard clock, and sending data '0' of N1 clock cycles to the bus as a frame starting part; in the next N1 clock cycles, the host monitors whether own sending signals and receiving signals are consistent through an exclusive OR gate, if so, no conflict exists on the bus, if not, a host with larger phase difference with the local clock signals occupies the bus, and the host monitoring the event firstly gives up the occupation of the bus and goes to a monitoring state; if the host keeps occupying the bus for N1 clock cycles continuously, the host continues to drive the clock signal to transmit N2 cycle data 1 to the bus, then sequentially transmits the local address and the destination address, in this stage, the host starts the exclusive OR check when transmitting the local address and the destination address, if the local drive signal is inconsistent with the actual signal of the bus, the host with smaller phase difference between the clock signal and the host is occupying the bus, the host still keeps occupying the bus correctly when transmitting information, otherwise, the host gives up the control right to the bus; if the host still has control over the bus, the host will transmit the frame information portion for the next N3 cycles; after the frame information part is transmitted, the host adjusts the clock to be a high-speed clock, and the effective data is rapidly transmitted under the clock; after the effective data transmission is completed, the host switches back to the standard clock and transmits the check code part under the clock; finally, the host drives the clock line for N4 clock cycles, samples bus data according to the sampling edge of the slave, and is stored in a buffer as a frame response part;
data frame receiving process: when the slave receives data, if transmission of continuous data '0' occurs for more than N1/4 clock cycles, which means that the transmission is started, the slave will monitor continuously until N2 periodic data '1' occurs on the bus, at which time the slave considers that the correct frame start part has been received, and prepares to accept further frame data; if the slave receives the correct frame start part, the address part, the frame information part, the data part and the check part are sequentially received in a plurality of next clock cycles, when the data transmission of the last clock of the check part is finished, the slave starts to drive the data line part of the bus and drives response information to the bus under the clock drive of the host, and then the slave sets a receiving flag bit and further data processing is carried out by a circuit driven by a local clock.
2. The multi-host communication bus system of claim 1, wherein: during the transmission of the frame information part, the data part and the check code part, the master uses the same clock edge as the slave samples to perform conflict monitoring, and if the data on the bus is detected to be inconsistent with the drive, the master gives up the control on the bus.
3. The multi-host communication bus system of claim 1, wherein: and when the host monitors that the bus is idle for more than 3 times N1+1 maximum clock cycles, judging that the bus is in an idle state.
4. The multi-host communication bus system of claim 1, wherein: and in the receiving process of the slave, a local clock consistent with the standard clock is always started to monitor, when the clock bus has no signal transmission for continuous N1+1 clock cycles, the current transmission frame of the bus is considered to be abandoned or has errors, and the receiving of the frame is abandoned.
5. The multi-host communication bus system of claim 4, wherein: if the slave receives the correct frame start part, it will receive the address part and determine if it is the receiving end in the next several clock cycles.
6. The multi-host communication bus system of claim 5, wherein: the slave will continue to receive the frame information portion, the data portion and the check portion, whether or not it is the receiving end.
7. The multi-host communication bus system of claim 6, wherein: the slave machine continuously uses the clock provided by the differential bus in the receiving process, when the data transmission of the last clock of the verification part is finished, if the slave machine is a receiving end, the slave machine starts to drive the data line part of the bus and drives response information to the bus under the driving of the clock of the host machine, and then the slave machine sets a receiving flag bit and further processes data by a circuit driven by a local clock.
8. The multi-host communication bus system of claim 1, wherein: the bus data frame is divided into a starting part, an address part, a frame information part, a data part, a checking part and a response part, wherein the starting part is used for representing the generation of a new frame in the bus; the address part is used for representing the source address and the destination address of the frame; the frame information part is used for representing the type, length and other necessary additional information of the frame; the data portion represents data to be actually transmitted; the checking part is a group of checking information generated by calculating an address part, a frame information part and a data part of the frame and is used for checking the integrity of the frame; the response part is used for reporting the receiving condition to the host computer from the slave computer.
9. The multi-host communication bus system of claim 1, wherein: the bus transmits data by using the rising edge or the falling edge of the clock, and when the host computer changes the data at the rising edge of the clock, the slave computer samples the data at the falling edge of the clock to become a rising edge mode; when the master changes data on the clock falling edge, the slave samples data on the clock rising edge, and becomes a falling edge mode.
10. The multi-host communication bus system of claim 1, wherein: the standard clock is a bus transmission clock which is uniformly regulated, and all the master-slave machines are kept consistent; the high-speed clock is used for data transmission and is higher than the frequency of the standard clock.
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| CN1662008A (en) * | 2004-10-20 | 2005-08-31 | 天津市英克瑞电子技术有限公司 | Communication method of half duplex serial bus with clock singal and communication system |
| CN102088386A (en) * | 2011-01-20 | 2011-06-08 | 中北大学 | Universal serial bus (USB) for master-slave interconnection module of circuit system |
| CN111123806A (en) * | 2020-01-14 | 2020-05-08 | 广东工业大学 | EtherCAT main station system with double data channels |
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| CN107332749B (en) * | 2017-07-05 | 2020-09-22 | 北京东土科技股份有限公司 | Synchronization method and device based on industrial internet field layer broadband bus architecture |
| US11327917B2 (en) * | 2019-01-14 | 2022-05-10 | Sigmasense, Llc. | Low voltage drive circuit and communication system |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1662008A (en) * | 2004-10-20 | 2005-08-31 | 天津市英克瑞电子技术有限公司 | Communication method of half duplex serial bus with clock singal and communication system |
| CN102088386A (en) * | 2011-01-20 | 2011-06-08 | 中北大学 | Universal serial bus (USB) for master-slave interconnection module of circuit system |
| CN111123806A (en) * | 2020-01-14 | 2020-05-08 | 广东工业大学 | EtherCAT main station system with double data channels |
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