CN113708736A - LOC and VDB shared numerical control automatic gain loop and method - Google Patents

Abstract

The invention provides a LOC and VDB shared numerical control automatic gain loop and a method, comprising the following steps: the frequency synthesizer generates a local oscillation signal module, a radio frequency front end module, an intermediate frequency signal processing module, a VGA automatic gain module and an FPGA processing module. The LOC/VDB shares a set of radio frequency hardware circuit and a numerical control AGC circuit in a time-sharing multiplexing mode, the LOC and VDB software mathematical models are the same, and the LOC or VDB function can be matched only by changing parameters corresponding to the LOC and the VDB on software. The invention is compatible with the VDB function on the basis of the ILS instrument landing system, guides the airplane to approach and land accurately, and can ensure that the ILS is compatible with the VDB function on the basis of not increasing a radio frequency channel, so the product integration level is high, corresponding signals can be switched according to different scenes, and the selection of the approach and landing guide functions of the airplanes in different airports can be solved.

Description

LOC and VDB shared numerical control automatic gain loop and method

Technical Field

The invention belongs to the technical field of communication navigation, and particularly relates to a numerical control automatic gain loop shared by LOC and VDB and a method thereof.

Background

An Instrument Landing System (ILS) is the most widely used guidance System for precise approach and Landing of an aircraft, and functions as: the ground transmits radio signals to realize course and glide slope guidance, a virtual path pointing to the air from the runway is established, the aircraft determines the relative position of the aircraft and the path through airborne receiving equipment, so that the aircraft flies to the runway along the correct direction and stably descends to the height, and finally, safe landing is realized.

The common instrument landing system transmits a heading beacon LOC with a radio signal to guide an airplane to approach and land. The instrument landing system has single function and only has single signal guiding and navigating function, and can not meet the requirements of various guiding and navigating signals required by approaching and landing guidance of airplanes in different airports.

Disclosure of Invention

Aiming at the defects in the prior art, the invention provides a numerical control automatic gain loop shared by LOC and VDB and a method thereof, which can effectively solve the problems.

The technical scheme adopted by the invention is as follows:

the invention provides a LOC and VDB shared numerical control automatic gain loop, comprising: the frequency synthesizer generates a local oscillation signal module, a radio frequency front end module, an intermediate frequency signal processing module, a VGA automatic gain module and an FPGA processing module;

the mixed radio frequency signal output end of the radio frequency front-end module and the LOC/VDB local oscillation signal output end of the local oscillation signal generation module of the frequency synthesizer are connected to the input end of the intermediate frequency signal processing module; the output end of the intermediate frequency signal processing module is connected to the input end of the VGA automatic gain module; the output end of the VGA automatic gain module is connected to the input end of the FPGA processing module;

and the control end of the FPGA processing module is respectively connected with the local oscillator signal generating module of the frequency synthesizer, the radio frequency front end module and the control end of the VGA automatic gain module.

Preferably, the frequency synthesizer generates a local oscillation signal module, which includes a frequency synthesizer U7, a 100M crystal oscillator Y1, a filter F5 and an amplifier U8;

the frequency synthesizer U7, the filter F5 and the amplifier U8 are connected in series; the 100M crystal oscillator Y1 is connected with the working clock signal input end of the frequency synthesizer U7.

Preferably, the radio frequency front end module comprises a LOC/VDB antenna, a filter F1, a coupler U1, a filter F2, an attenuator U2, an amplifier U3 and a mixer U4;

the output end of an amplifier U8 of the frequency synthesizer local oscillation signal generating module is connected to the first input end of the mixer U4;

after the LOC/VDB antenna, the filter F1, the coupler U1, the filter F2, the attenuator U2 and the amplifier U3 are connected in series, the output terminal thereof is connected to the second input terminal of the mixer U4.

Preferably, the intermediate frequency signal processing module comprises a filter F3, an amplifier U5 and a filter F4;

an output of the mixer U4 connected to an input of the filter F3; an output of the filter F3 connected to an input of the amplifier U5; an output of the amplifier U5 is connected to an input of the filter F4.

Preferably, the VGA automatic gain module comprises a VGA amplifier U6, an RC circuit, an analog-to-digital converter U9, a digital-to-analog converter U10;

the FPGA processing module comprises an FPGAU 11;

an output of the filter F4 connected to a first input of the VGA amplifier U6; the gain feedback digital signal of the FPGAU11 is connected to the second input end of the VGA amplifier U6 after passing through the digital-to-analog converter U10 and the RC circuit;

the output end of the VGA amplifier U6 is connected to the input end of the FPGAU11 after passing through the analog-to-digital converter U9.

The invention also provides a method for sharing the numerical control automatic gain loop by LOC and VDB, which comprises the following steps:

step 1, LOC/VDB local oscillation signal output process:

a 100M crystal oscillator Y1 provides a stable working clock signal for the frequency synthesizer U7;

the FPGAU11 outputs a control signal to the frequency synthesizer U7 as an operation enabling switch signal of the frequency synthesizer U7;

FPGAU11 outputs a frequency feedback signal as the LOC/VDB automatic frequency control signal of frequency synthesizer U7;

the frequency synthesizer U7 adjusts the local oscillator output frequency according to the frequency feedback signal output by the FPGAU11, and outputs the LOC/VDB intermediate frequency local oscillator signal, and the LOC/VDB intermediate frequency local oscillator signal passes through the filter F5 and the amplifier U8 to be filtered and amplified, so that the LOC/VDB local oscillator signal of the target intermediate frequency is obtained; the frequency synthesizer U7 switches and outputs LOC local oscillation signals or VDB local oscillation signals according to the time division multiplexing instruction;

step 2, LOC and VDB radio frequency mixed signal output process:

the LOC/VDB antenna receives a radio frequency mixed signal formed by mixing a plurality of radio frequency signals, an interference signal is filtered through a filter F1, then the interference signal enters a coupler U1, then the interference signal enters a filter F2, other frequency band signals are filtered through a filter F2, only LOC and VDB radio frequency signals are reserved, and the LOC and VDB radio frequency mixed signal is obtained;

the LOC and VDB radio frequency mixed signals enter an attenuator U2, an attenuator U2 generates an attenuator control signal, and the LOC and VDB radio frequency mixed signals are processed; wherein: the attenuator control signal is an attenuation control signal fed back by the FPGAU11 according to the collected power of the intermediate frequency signal;

the LOC and VDB radio frequency mixed signals processed by the attenuator U2 are subjected to radio frequency signal amplification processing through an amplifier U3 to obtain amplified LOC and VDB radio frequency mixed signals, and then the amplified LOC and VDB radio frequency mixed signals enter a mixer U4;

the mixer U4 inputs two signals, which are: the radio frequency mixed signal of LOC and VDB, and the LOC local oscillator signal or VDB local oscillator signal that the frequency synthesizer produces the local oscillator signal module and produces, show as: the LOC/VDB local oscillation signal outputs an LOC/VDB intermediate frequency signal under the action of a mixer U4;

step 3, intermediate frequency signal processing:

the LOC/VDB intermediate frequency signal output by the mixer U4 is filtered and amplified through a filter F3, an amplifier U5 and a filter F4, the signal quality is further improved, and an intermediate frequency signal with a certain power value is output;

step 4, automatic gain control process:

an intermediate frequency signal output in the intermediate frequency signal processing process is firstly subjected to gain amplification through a VGA amplifier U6, the intermediate frequency signal is input into an analog-to-digital converter U9 after the gain amplification for analog-to-digital signal conversion, the obtained digital signal is input into an FPGA processing module, meanwhile, the digital-to-analog converter U10 converts a gain feedback digital signal output by the FPGA processing module into an analog signal, and after a clock and clutter are filtered through an RC circuit, a voltage-controlled voltage is output to serve as a gain value of the VGA amplifier U6;

wherein: the signal processing process of the FPGA processing module comprises the following steps:

the FPGA processing module carries out square law detection and integral accumulation on the digital signal output by the analog-to-digital converter U9 of the VGA automatic gain module to obtain the current output signal power value; then, the current output signal power value is input into a comparator, and the comparator compares the current output signal power value with a reference value C to obtain a difference value between the current output signal power value and the reference value C, that is: a power error Pe; multiplying the power error Pe by the amplification factor A, limiting, and realizing loop filtering through an IIR filter;

after the loop is filtered, a signal is input into a digital-to-analog converter U10 to be converted, after a clock and clutter are filtered by an RC circuit, a voltage-controlled voltage is output to serve as a gain value of a VGA amplifier U6, a loop is formed, repeated feedback iteration is carried out, and along with the repeated feedback iteration process, a power error Pe approaches to a constant value and represents loop convergence.

The invention provides a LOC and VDB shared numerical control automatic gain loop and a method thereof, which have the following advantages:

the invention provides a numerical control automatic gain loop shared by LOC and VDB and a method thereof, wherein the LOC/VDB shares a set of radio frequency hardware circuit and a numerical control AGC circuit in a time-sharing multiplexing mode, the mathematical models of LOC and VDB software are the same, and the LOC or VDB function can be matched only by changing the corresponding parameters of the LOC and the VDB on the software. The invention is compatible with the VDB function on the basis of the ILS instrument landing system, guides the airplane to approach and land accurately, and can ensure that the ILS is compatible with the VDB function on the basis of not increasing a radio frequency channel, so the product integration level is high, corresponding signals can be switched according to different scenes, and the selection of the approach and landing guide functions of the airplanes in different airports can be solved.

Drawings

FIG. 1 is a schematic diagram of a digital controlled automatic gain loop shared by LOC and VDB provided by the present invention;

fig. 2 is a mathematical model diagram of gain control provided by the present invention.

Detailed Description

In order to make the technical problems, technical solutions and advantageous effects solved by the present invention more clearly apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

As shown in fig. 1, the present invention provides a digital controlled automatic gain loop shared by LOC and VDB, comprising: the frequency synthesizer generates a local oscillation signal module, a radio frequency front end module, an intermediate frequency signal processing module, a VGA automatic gain module and an FPGA processing module.

The mixed radio frequency signal output end of the radio frequency front-end module and the LOC/VDB local oscillation signal output end of the local oscillation signal generation module of the frequency synthesizer are connected to the input end of the intermediate frequency signal processing module; the output end of the intermediate frequency signal processing module is connected to the input end of the VGA automatic gain module; the output end of the VGA automatic gain module is connected to the input end of the FPGA processing module;

and the control end of the FPGA processing module is respectively connected with the local oscillator signal generating module of the frequency synthesizer, the radio frequency front end module and the control end of the VGA automatic gain module.

Module for generating local oscillator signal by frequency synthesizer

The frequency synthesizer generates a local oscillation signal module, which comprises a frequency synthesizer U7, a 100M crystal oscillator Y1, a filter F5 and an amplifier U8. The frequency synthesizer U7, the filter F5 and the amplifier U8 are connected in series; the 100M crystal oscillator Y1 is connected with the working clock signal input end of the frequency synthesizer U7.

The 100M crystal oscillator Y1 provides a stable operating clock signal for the frequency synthesizer U7. The enable signal is a control signal output by FPGAU11 as an operation enable switching signal of frequency synthesizer U7. The LOC/VDB automatic frequency control signal is a frequency feedback signal output by the FPGAU11, the FPGAU11 feeds back the LOC/VDB intermediate frequency signal frequency to the frequency synthesizer U7 by detecting the LOC/VDB intermediate frequency signal frequency, and the frequency synthesizer U7 can accurately adjust the local oscillator output frequency according to the feedback so as to obtain a target intermediate frequency signal. The local oscillator signal LOC/VDB generated by the frequency synthesizer U7 is filtered and amplified by the filter F5 and the amplifier U8, and then enters the mixer U4 of the RF front-end module.

(II) radio frequency front end module

The radio frequency front end module comprises a LOC/VDB antenna, a filter F1, a coupler U1, a filter F2, an attenuator U2, an amplifier U3 and a mixer U4.

The output end of an amplifier U8 of the frequency synthesizer local oscillation signal generating module is connected to the first input end of the mixer U4;

after the LOC/VDB antenna, the filter F1, the coupler U1, the filter F2, the attenuator U2 and the amplifier U3 are connected in series, the output terminal thereof is connected to the second input terminal of the mixer U4.

The LOC/VDB antenna receives the radio frequency mixed signals of LOC, VDB and the like, firstly, interference signals are filtered through a filter F1, then the radio frequency mixed signals enter a coupler U1 and a filter F2, the filter F2 has a passband of 108MHz-118MHz, LOC and VDB radio frequency signals are reserved, and other frequency band signals are filtered. An attenuator U2 is arranged behind the filter F2, and an attenuator control signal is an attenuation control signal fed back by the FPGAU11 according to the collected power of the intermediate frequency signal. The amplifier U3 can amplify the LOC and VDB RF signals to obtain a mixed LOC and VDB RF signal, which then enters the mixer U4.

The mixer U4 inputs two signals, which are: the frequency synthesizer generates local oscillation signals of LOC or VDB, and the frequency synthesizer generates local oscillation signals of LOC or VDB. If the local oscillator signal generating module of the frequency synthesizer is currently switched to generate the LOC local oscillator signal, the LOC local oscillator signal and the radio frequency mixed signal of the LOC and the VDB enter the mixer U4, and the LOC local oscillator signal and the radio frequency mixed signal of the LOC and the VDB are mixed under the action of the mixer U4 to obtain the LOC intermediate frequency signal. Similarly, if the module for generating local oscillation signal by the frequency synthesizer is currently switched to generate VDB local oscillation signal, the VDB local oscillation signal and the radio frequency mixed signal of LOC and VDB enter the mixer U4, and are mixed by the mixer U4 to obtain VDB intermediate frequency signal.

(III) intermediate frequency signal processing module

The intermediate frequency signal processing module comprises a filter F3, an amplifier U5 and a filter F4. The output end of an amplifier U8 of the frequency synthesizer local oscillation signal generating module is connected to the first input end of the mixer U4;

after the LOC/VDB antenna, the filter F1, the coupler U1, the filter F2, the attenuator U2 and the amplifier U3 are connected in series, the output terminal thereof is connected to the second input terminal of the mixer U4.

The mixer U4 of the rf front-end module outputs the LOC intermediate frequency signal or VDB intermediate frequency signal, expressed as: the LOC/VDB intermediate frequency signals are filtered and amplified through a filter F3, an amplifier U5 and a filter F4 respectively, the signal quality is further improved, and intermediate frequency signals with a certain power value, such as 26.25MHz intermediate frequency signals, are output.

(IV) VGA automatic gain module

The VGA automatic gain module comprises a VGA amplifier U6, an RC circuit, an analog-to-digital converter U9 and a digital-to-analog converter U10.

The FPGA processing module comprises an FPGAU 11;

an output of the filter F4 connected to a first input of the VGA amplifier U6; the gain feedback digital signal of the FPGAU11 is connected to the second input end of the VGA amplifier U6 after passing through the digital-to-analog converter U10 and the RC circuit;

the output end of the VGA amplifier U6 is connected to the input end of the FPGAU11 after passing through the analog-to-digital converter U9.

The 26.25MHz intermediate frequency signal that intermediate frequency signal processing module output, at first gain amplification through VGA (variable gain amplifier) amplifier U6, after gain amplification input analog-to-digital converter U9 carry out analog-to-digital signal conversion, the digital signal that obtains inputs to FPGA processing module, simultaneously, digital-to-analog converter U10 converts the gain feedback digital signal that FPGA processing module output to analog signal, after RC circuit filtering clock and clutter, output voltage-controlled voltage as the gain value of VGA amplifier U6.

(V) FPGA processing module

The FPGA processing module comprises an FPGAU 11;

1) the digital signal output by an analog-to-digital converter U9 of the VGA automatic gain module is subjected to square-law detection and integral accumulation, and the square-law detection and the integral accumulation form a detector together, so that the current output signal power value is obtained;

the purpose of integral accumulation is to smooth and sample a high-speed over-sampling clock sampling signal and convert the signal into a clock domain suitable for a loop.

2) Then, the current output signal power value is input into a comparator, and the comparator compares the current output signal power value with a reference value C to obtain a difference value between the current output signal power value and the reference value C, that is: the power error Pe.

Wherein the reference value C is a desired output power value. The final stable signal amplitude can be adjusted by adjusting the reference value C;

3) then, the power error Pe is multiplied by the amplification factor a, and then the limit is performed.

The feedback gain of the loop can be adjusted by adjusting the amplification factor A. Too much feedback gain may cause loop divergence, and too little feedback gain may cause steady state output amplitude to be affected by input power to produce a constant difference.

The purpose of the limits is: the amplified error is clipped subject to the limitation of the digital representation bit width.

4) And realizing loop filtering by using an IIR filter as a limiting result.

The IIR filter adopts a first-order structure, namely a first-order loop. The IIR filter plays a decisive role in the stability and convergence speed of the loop. The loop bandwidth is too small, which may cause the loop to produce parasitic amplitude modulation and not be stable.

5) The signals after loop filtering are input into a digital-to-analog converter U10 for conversion, and after a clock and clutter are filtered by an RC circuit, voltage-controlled voltage is output to serve as a gain value of a VGA amplifier U6, so that a loop is formed for repeated feedback iteration, and as the repeated feedback iteration process is carried out, a power error Pe approaches to a constant value, which indicates that the loop is converged.

Wherein:

the gain calculation formula is as follows:

G(n+1)＝G(n)+K(Thr-P(n)) (1)

wherein:

p (n): the output signal power value of the nth iteration;

thr: a reference value C;

k: a feedback coefficient;

g (n): channel gain for the nth iteration, namely: a voltage-controlled voltage output via an RC circuit;

g (n + 1): channel gain for the (n +1) th iteration.

The model is abstracted, and the logarithm value of the power error is taken as the function of loop transfer, so that the effect of the VGA amplifier on the loop can be more accurately described. After abstraction, the mathematical model is shown in fig. 2:

and comparing the input signal power logarithm value with a reference value C, defining the compared value as a power error Pe, entering a loop for repeated feedback iteration, wherein Pe approaches a constant value along with the repeated feedback iteration process, and indicating the convergence of the loop. The model A comprises two parts, the first part is digital gain and is adjusted according to loop design, and the second part is VGA amplification factor. The VGA gain change and the power error are converted into addition and subtraction operation by using the power logarithm. If the gain curvature of the VGA is 120dB/V, the gain A can be expressed as 12 a. The loop filter is realized by an IIR filter, and can be correspondingly transformed with the analog RC filter.

The invention provides a LOC and VDB shared numerical control automatic gain loop and a method, which have the following characteristics: LOC and VDB functions are time division multiplexing functions, and are controlled and selected by an FPGA processing module. The LOC/VDB intermediate frequency signal is converted into a digital signal by an ADC after being amplified by a VGA, the digital signal is subjected to square-law detection, integral accumulation, comparison amplification and feedback gain output, voltage-controlled voltage is output by a DAC, the gain value of the VGA is controlled by the voltage-controlled voltage, and a first-stage RC filter is inserted between the DAC and the VGA and used for filtering clocks and noise waves. In addition, LOC and VDB share one radio frequency channel, and an automatic gain control loop (AGC) circuit can simultaneously meet the gain control of the LOC and VDB loops.

The invention provides a LOC and VDB shared numerical control automatic gain loop and a method, which have the following advantages:

the LOC/VDB shares a set of radio frequency hardware circuit and a numerical control AGC circuit in a time-sharing multiplexing mode, the LOC and VDB software mathematical models are the same, and the LOC or VDB function can be matched only by changing parameters corresponding to the LOC and the VDB on software. The invention is compatible with the VDB function on the basis of the ILS instrument landing system, guides the airplane to approach and land accurately, and can ensure that the ILS is compatible with the VDB function on the basis of not increasing a radio frequency channel, so the product integration level is high, corresponding signals can be switched according to different scenes, and the selection of the approach and landing guide functions of the airplanes in different airports can be solved.

The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and improvements can be made without departing from the principle of the present invention, and such modifications and improvements should also be considered within the scope of the present invention.

Claims (6)

1. A digitally controlled automatic gain loop shared by LOC and VDB, comprising: the frequency synthesizer generates a local oscillation signal module, a radio frequency front end module, an intermediate frequency signal processing module, a VGA automatic gain module and an FPGA processing module;

the mixed radio frequency signal output end of the radio frequency front-end module and the LOC/VDB local oscillation signal output end of the local oscillation signal generation module of the frequency synthesizer are connected to the input end of the intermediate frequency signal processing module; the output end of the intermediate frequency signal processing module is connected to the input end of the VGA automatic gain module; the output end of the VGA automatic gain module is connected to the input end of the FPGA processing module;

and the control end of the FPGA processing module is respectively connected with the local oscillator signal generating module of the frequency synthesizer, the radio frequency front end module and the control end of the VGA automatic gain module.

2. The LOC and VDB shared digitally controlled automatic gain loop of claim 1, wherein the frequency synthesizer produces local oscillator signals modules comprising a frequency synthesizer U7, a 100M crystal oscillator Y1, a filter F5 and an amplifier U8;

the frequency synthesizer U7, the filter F5 and the amplifier U8 are connected in series; the 100M crystal oscillator Y1 is connected with the working clock signal input end of the frequency synthesizer U7.

3. The LOC and VDB shared digitally controlled automatic gain loop of claim 2, wherein the RF front end module comprises LOC/VDB antenna, filter F1, coupler U1, filter F2, attenuator U2, amplifier U3 and mixer U4;

the output end of an amplifier U8 of the frequency synthesizer local oscillation signal generating module is connected to the first input end of the mixer U4;

after the LOC/VDB antenna, the filter F1, the coupler U1, the filter F2, the attenuator U2 and the amplifier U3 are connected in series, the output terminal thereof is connected to the second input terminal of the mixer U4.

4. The LOC and VDB shared digitally controlled automatic gain loop of claim 3, wherein the IF signal processing block comprises filter F3, amplifier U5 and filter F4;

an output of the mixer U4 connected to an input of the filter F3; an output of the filter F3 connected to an input of the amplifier U5; an output of the amplifier U5 is connected to an input of the filter F4.

5. The LOC and VDB shared digitally controlled automatic gain loop of claim 4, wherein the VGA automatic gain module comprises VGA amplifier U6, RC circuit, analog-to-digital converter U9, digital-to-analog converter U10;

the FPGA processing module comprises an FPGAU 11;

an output of the filter F4 connected to a first input of the VGA amplifier U6; the gain feedback digital signal of the FPGAU11 is connected to the second input end of the VGA amplifier U6 after passing through the digital-to-analog converter U10 and the RC circuit;

the output end of the VGA amplifier U6 is connected to the input end of the FPGAU11 after passing through the analog-to-digital converter U9.

6. A method of digital controlled automatic gain loop shared by LOC and VDB of any of claims 1-5, comprising the steps of:

step 1, LOC/VDB local oscillation signal output process:

a 100M crystal oscillator Y1 provides a stable working clock signal for the frequency synthesizer U7;

the FPGAU11 outputs a control signal to the frequency synthesizer U7 as an operation enabling switch signal of the frequency synthesizer U7;

FPGAU11 outputs a frequency feedback signal as the LOC/VDB automatic frequency control signal of frequency synthesizer U7;

the frequency synthesizer U7 adjusts the local oscillator output frequency according to the frequency feedback signal output by the FPGAU11, and outputs the LOC/VDB intermediate frequency local oscillator signal, and the LOC/VDB intermediate frequency local oscillator signal passes through the filter F5 and the amplifier U8 to be filtered and amplified, so that the LOC/VDB local oscillator signal of the target intermediate frequency is obtained; the frequency synthesizer U7 switches and outputs LOC local oscillation signals or VDB local oscillation signals according to the time division multiplexing instruction;

step 2, LOC and VDB radio frequency mixed signal output process:

the LOC/VDB antenna receives a radio frequency mixed signal formed by mixing a plurality of radio frequency signals, an interference signal is filtered through a filter F1, then the interference signal enters a coupler U1, then the interference signal enters a filter F2, other frequency band signals are filtered through a filter F2, only LOC and VDB radio frequency signals are reserved, and the LOC and VDB radio frequency mixed signal is obtained;

the LOC and VDB radio frequency mixed signals enter an attenuator U2, an attenuator U2 generates an attenuator control signal, and the LOC and VDB radio frequency mixed signals are processed; wherein: the attenuator control signal is an attenuation control signal fed back by the FPGAU11 according to the collected power of the intermediate frequency signal;

the LOC and VDB radio frequency mixed signals processed by the attenuator U2 are subjected to radio frequency signal amplification processing through an amplifier U3 to obtain amplified LOC and VDB radio frequency mixed signals, and then the amplified LOC and VDB radio frequency mixed signals enter a mixer U4;

the mixer U4 inputs two signals, which are: the radio frequency mixed signal of LOC and VDB, and the LOC local oscillator signal or VDB local oscillator signal that the frequency synthesizer produces the local oscillator signal module and produces, show as: the LOC/VDB local oscillation signal outputs an LOC/VDB intermediate frequency signal under the action of a mixer U4;

step 3, intermediate frequency signal processing:

the LOC/VDB intermediate frequency signal output by the mixer U4 is filtered and amplified through a filter F3, an amplifier U5 and a filter F4, the signal quality is further improved, and an intermediate frequency signal with a certain power value is output;

step 4, automatic gain control process:

an intermediate frequency signal output in the intermediate frequency signal processing process is firstly subjected to gain amplification through a VGA amplifier U6, the intermediate frequency signal is input into an analog-to-digital converter U9 after the gain amplification for analog-to-digital signal conversion, the obtained digital signal is input into an FPGA processing module, meanwhile, the digital-to-analog converter U10 converts a gain feedback digital signal output by the FPGA processing module into an analog signal, and after a clock and clutter are filtered through an RC circuit, a voltage-controlled voltage is output to serve as a gain value of the VGA amplifier U6;

wherein: the signal processing process of the FPGA processing module comprises the following steps:

the FPGA processing module carries out square law detection and integral accumulation on the digital signal output by the analog-to-digital converter U9 of the VGA automatic gain module to obtain the current output signal power value; then, the current output signal power value is input into a comparator, and the comparator compares the current output signal power value with a reference value C to obtain a difference value between the current output signal power value and the reference value C, that is: a power error Pe; multiplying the power error Pe by the amplification factor A, limiting, and realizing loop filtering through an IIR filter;

after the loop is filtered, a signal is input into a digital-to-analog converter U10 to be converted, after a clock and clutter are filtered by an RC circuit, a voltage-controlled voltage is output to serve as a gain value of a VGA amplifier U6, a loop is formed, repeated feedback iteration is carried out, and along with the repeated feedback iteration process, a power error Pe approaches to a constant value and represents loop convergence.

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