CN113707567A - Method for testing strength of semiconductor structure - Google Patents
Method for testing strength of semiconductor structure Download PDFInfo
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- CN113707567A CN113707567A CN202110778068.2A CN202110778068A CN113707567A CN 113707567 A CN113707567 A CN 113707567A CN 202110778068 A CN202110778068 A CN 202110778068A CN 113707567 A CN113707567 A CN 113707567A
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- H01—ELECTRIC ELEMENTS
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- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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Abstract
The embodiment of the disclosure discloses a strength test method of a semiconductor structure, which comprises the following steps: providing a semiconductor structure to be tested; intercepting a target area in the semiconductor structure to be tested to obtain the structure to be tested; determining the position of a target structure in the structure to be detected; wherein the target structure is located within the target region; and applying a load to the structure to be measured at the position of the target structure, and measuring the mechanical strength of the position of the target structure in the structure to be measured.
Description
Technical Field
The embodiment of the disclosure relates to the technical field of semiconductors, in particular to a strength testing method of a semiconductor structure.
Background
During the fabrication and packaging of semiconductor chips, a lot of scenes introduce large shear or positive stress, such as the residual stress caused by Chemical-Mechanical planarization (CMP) in the front end process, Polishing in the back end process, and structure warpage, which requires that the entire chip and the internal material have sufficient Mechanical strength to resist the structure failure.
With the increasing number of layers and longitudinal thickness of 3D NAND memory layers, internal structures and stress distribution become more and more complex, and each process may introduce more local residual stress and more potential weak structures. These weak structures can cause local cracks during the chip manufacturing process, which can cause macro-structure failure and yield loss. Therefore, establishing the analysis method for the intensity characteristic and the failure mechanism of the semiconductor chip provides necessary data support for the adjustment of the production process, and has important significance.
Disclosure of Invention
In view of the above, an embodiment of the present disclosure provides a method for testing strength of a semiconductor structure, including:
providing a semiconductor structure to be tested;
intercepting a target area in the semiconductor structure to be tested to obtain the structure to be tested;
determining the position of a target structure in the structure to be detected; wherein the target structure is located within the target region;
and applying a load to the structure to be measured at the position of the target structure, and measuring the mechanical strength of the position of the target structure in the structure to be measured.
In some embodiments, the structure under test includes a substrate and a structural layer on the substrate, the structural layer having the target structure therein, the method further including:
and after the structure to be detected is obtained, thinning the substrate included by the structure to be detected to a preset thickness.
In some embodiments, the predetermined thickness range is: 50 μm to 250 μm.
In some embodiments, the method further comprises:
polishing the side surface of the structure to be detected after the substrate of the structure to be detected is thinned to a preset thickness; wherein the side is perpendicular to the substrate.
In some embodiments, said intercepting a target region in said semiconductor structure under test comprises:
and obtaining the part of the target area in the semiconductor structure by cutting the semiconductor structure.
In some embodiments, the target structure comprises at least one of the following structures in a 3D NAND memory:
a gate stack;
a channel hole;
and (3) a step structure.
In some embodiments, the applying a load to the structure under test at the position of the target structure, and measuring the mechanical strength of the structure under test at the position of the target structure includes:
and applying gradually increased load to the structure to be tested, and determining the load value applied when the structure to be tested is damaged.
In some embodiments, the method comprises: and measuring the bending strength of the structure to be measured by adopting a three-point bending test.
In some embodiments, the structure under test comprises a substrate and a structural layer on the substrate, the structural layer having the target structure therein;
the applying a load to the structure to be tested includes: a load is applied from a surface of the substrate relatively remote from the structural layer.
In some embodiments, the applying a gradually increasing load to the structure under test and determining the value of the applied load when the structure under test is damaged includes:
applying a load which is increased at a constant rate to the structure to be measured, and measuring the deflection change of the structure to be measured to obtain a corresponding relation change curve of the load and the deflection;
and determining the load value when the structure to be tested is damaged through the catastrophe points on the curve.
According to the strength measurement method of the semiconductor structure, the structure to be measured is obtained by intercepting the target area in the semiconductor structure to be measured, and the mechanical strength of the structure to be measured is measured by applying a load to the position of the target structure in the structure to be measured. On one hand, the influence of a target structure formed in a station process on the mechanical strength of a semiconductor structure can be analyzed, and data support is provided for analyzing a crack generation mechanism. On the other hand, the mechanical strength of the target position of different areas of the semiconductor structure is detected, so that the process abnormity of the current station process forming the target structure can be monitored, and reference is provided for process adjustment of the current station process.
Drawings
FIG. 1a is a schematic diagram illustrating a method of three-point bending testing in accordance with an exemplary embodiment;
FIG. 1b is a schematic diagram illustrating the load versus position for testing a semiconductor structure using a three-point bend test, according to an exemplary embodiment;
FIG. 2 is a schematic diagram illustrating the relationship between load and wafer deflection when a three-point bend test is used to test the bending strength of a wafer in accordance with an exemplary embodiment;
FIG. 3 is a flow chart illustrating a method for testing the strength of a semiconductor structure in accordance with one exemplary embodiment;
FIG. 4 is a schematic diagram illustrating a method for thinning a structure under test according to an exemplary embodiment;
FIG. 5 is a schematic diagram illustrating a top view of a structure under test in accordance with an exemplary embodiment;
FIG. 6 is a schematic diagram illustrating a method for inspecting a structure under test using a three-point bend test in accordance with one illustrative embodiment;
FIG. 7 is a schematic diagram illustrating another method for inspecting a structure under test using a three-point bend test in accordance with one illustrative embodiment;
FIG. 8 is a schematic diagram illustrating a relationship between a load and a deflection of a structure under test when a three-point bending test is used to test bending strength of the structure under test, according to an exemplary embodiment.
Detailed Description
The technical solution of the present disclosure is further described in detail below with reference to the drawings and specific embodiments of the specification.
In the embodiments of the present disclosure, the terms "first", "second", and the like are used for distinguishing similar objects, and are not used for describing a particular order or sequence.
In the disclosed embodiment, the term "a is in contact with B" includes the case where a is in direct contact with B, or A, B is in contact with B indirectly with another component interposed between the two.
In embodiments of the present disclosure, the term "layer" refers to a portion of material that includes a region having a thickness. A layer may extend over the entirety of the underlying or overlying structure or may have an extent that is less than the extent of the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of the continuous structure, or a layer may be between any horizontal pair at the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically and/or along inclined surfaces. Also, a layer may include multiple sublayers.
It is to be understood that the meaning of "on … …," "over … …," and "over … …" in this disclosure should be read in the broadest manner such that "on … …" not only means that it is "on" something without intervening features or layers therebetween (i.e., directly on something), but also includes the meaning of "on" something with intervening features or layers therebetween.
Currently, methods such as Nanoindentation (Nanoindentation) and Three-Point Bend (3 PB) have been established to evaluate the overall strength Of Back End Of Line (BEOL) products.
The nano indentation technology is to press a needle point into a sample through controllable load, measure indentation depth in real time and obtain a load-displacement curve of the sample. The sensor has nanometer (nm) level displacement and micro-Newton (mu N) level load resolution, and can be used for measuring the mechanical properties of ultrathin layer materials such as films, coatings and the like.
FIG. 1a is a schematic diagram of a three-point bending test method for testing the bending strength of a semiconductor back-end-of-line product. Referring to FIG. 1a, a back-end-of-line product includes a substrate and a device layer formed on the substrate. The test sample of the back-end process product is placed on two supporting points with a certain span, a downward load is applied to the test sample above the span middle point between the two supporting points, three-point bending occurs when 3 contact points of the test sample form two equal moments, and the test sample breaks at the span middle point.
FIG. 1b is a schematic diagram showing the relationship between load and position when a test specimen is tested by the three-point bending test method. Referring to fig. 1b, the ordinate represents the load, and the abscissa represents the position between two support points, and it can be seen from fig. 1b that the load is the largest at the middle point of the span between the two support points, and the test specimen is broken at the middle point of the span.
Generally, the three-point bending test is used for a macroscopic mechanical test for testing the overall macroscopic strength of the semiconductor chip, and is not used for a microscopic mechanical test. For example, in manufacturing a three-dimensional memory, after a plurality of memory chips are formed on one wafer, the strength of the entire wafer is measured by a three-point bending test.
FIG. 2 is a graph showing the relationship between load and deflection obtained when the three-point bending test method is used to measure the overall bending strength of a wafer in the back-end process. From the load-deflection curve in fig. 2, the bending strength of the entire back-end-of-line wafer can be analyzed, but the strength distribution of different regions on the wafer cannot be obtained. Moreover, since the wafer in the back-end process includes a multi-layer film structure, the influence of each layer of structure on the strength of the wafer cannot be analyzed, and a reference cannot be provided for failure analysis caused by cracks.
In the related art, only the overall strength of the back-end-of-line product is concerned, and multiple layers of different structures are formed in the back-end-of-line product through the previous processes, each structure may introduce residual stress and weak structures, and due to the non-uniformity of the processes and other reasons, the same structure formed in different regions of the same wafer has a difference in strength, so that a part of the weak regions on the wafer may crack to cause device failure. However, the specific process of crack generation cannot be evaluated by strength analysis of the back-end-of-line product. Moreover, by analyzing the overall macroscopic strength of the wafer, statistical analysis cannot be performed on the probability of cracks at different positions of the wafer.
Fig. 3 is a flowchart illustrating a method for testing the strength of a semiconductor structure according to an embodiment of the disclosure. Referring to fig. 3, the method includes the steps of:
s100: providing a semiconductor structure to be tested;
s110: intercepting a target area in the semiconductor structure to be tested to obtain the structure to be tested;
s120: determining the position of a target structure in a structure to be detected; wherein the target structure is located within the target region;
s130: and applying load to the structure to be measured at the position of the target structure, and measuring the mechanical strength of the position of the target structure in the structure to be measured.
Illustratively, the semiconductor structure may include a wafer processed to form a device layer, such as a Front End Of Line (FEOL) or a back End product Of a three-dimensional memory device, and may specifically include an intermediate product structure formed in each process. The target structure may include additional structures introduced in each process, such as structures forming trenches, vias, or dielectric layers.
As will be readily appreciated, the formation of a semiconductor device is accomplished through a number of station processes, each of which includes at least one fabrication process. After the target structure is formed in the predetermined region by processing the semiconductor structure formed in the previous station process in the station process, the mechanical strength of the semiconductor structure in the station process in the target structure region is usually changed (increased or decreased), and new internal stress may be introduced to cause generation of cracks. In addition, the probability of cracks occurring at a portion having a weak mechanical strength is high.
Illustratively, the mechanical strength of the structure to be tested can be detected by adopting a nano indentation technology or a three-point bending test method.
For example, determining the location of the target structure in the structure under test may be performed under a high-power electron microscope, for example, using a Scanning Electron Microscope (SEM) to observe and calibrate the location of the target structure in the structure under test.
Illustratively, a reference may be provided for analyzing the mechanism of crack initiation by measuring and comparing the mechanical strength of a predetermined area in the semiconductor structure before and after formation of the target structure.
For example, when the semiconductor structure is a wafer including a plurality of identical sub-semiconductor structures, the target area may be selected at different positions on the wafer, and a plurality of structures to be tested may be obtained. Each structure to be tested comprises the same type of target structure formed in the current station process, and the process uniformity of the current station process can be analyzed by measuring and comparing the mechanical strength of the target structure in each structure to be tested.
On one hand, the mechanical strength of the structure to be tested obtained from different areas on the wafer can be analyzed to determine the area likely to generate cracks, for example, the area with lower mechanical strength has a higher probability of generating cracks. On the other hand, by analyzing the mechanical strength of the structure to be measured obtained from different areas on the wafer, the process difference between the different areas on the wafer can be analyzed, and the process adjustment can be carried out according to the difference, so that the process uniformity of the working procedure in the station is ensured, the weak structure area is reduced, the probability of generating cracks is reduced, and the product yield is improved.
Therefore, in practical applications, the method can be used for monitoring the strength of the semiconductor structure in the current station process so as to find out the process abnormality of the current station process in time. For example, in the manufacture of three-dimensional memory chips, after the target structure is formed in the station process, the chip product in the station process can be sampled and detected, and the mechanical strength at the position of the target structure in different areas on the wafer can be measured and statistically analyzed, so that on one hand, the probability of cracks in different areas on the wafer can be predicted, and on the other hand, reference can be provided for process adjustment in the station process.
In the embodiment of the present disclosure, the mechanical strength of the target structure in the structure to be measured is not the mechanical strength of the target structure itself, but the mechanical strength of the target structure in the structure to be measured in the local position, and the measured mechanical strength value is not necessarily the actual strength of the structure to be measured, but is mainly used as a mechanical strength value for transverse comparison. That is to say, the mechanical strength of the structure to be tested measured by the embodiment of the present disclosure is mainly used for comparing with the mechanical strength of other micro regions in the same structure to be tested, or is used for comparing with the mechanical strength of the same target structure in the structure to be tested obtained from different target regions.
According to the strength measurement method of the semiconductor structure, the structure to be measured is obtained by intercepting the target area in the semiconductor structure to be measured, and the mechanical strength of the structure to be measured is measured by applying a load to the position of the target structure in the structure to be measured. On one hand, the influence of a target structure formed in a station process on the mechanical strength of a semiconductor structure can be analyzed, and data support is provided for analyzing a crack generation mechanism. On the other hand, the mechanical strength of the target position of different areas of the semiconductor structure is detected, so that the process abnormity of the current station process forming the target structure can be monitored, and reference is provided for process adjustment of the current station process.
In some embodiments, a structure under test includes a substrate and a structural layer on the substrate, the structural layer having a target structure therein, the method further comprising:
and after obtaining the structure to be detected, thinning the substrate included in the structure to be detected to a preset thickness.
For example, a semiconductor structure may include a wafer having a structural layer formed on a substrate, and a structure to be tested obtained by cutting a target area from the semiconductor structure may also have the substrate and the structural layer. The substrate may comprise a semiconductor substrate, such as a silicon (Si) substrate. The structural layer includes a device layer formed on the substrate, and the device layer has a target structure, such as a gate stack structure formed on the substrate in the three-dimensional NAND memory, a channel hole penetrating through the gate stack structure, and the like.
Illustratively, referring to FIG. 4, a structure to be tested includes a substrate 10 and a structural layer 20 formed on the substrate 10. The substrate 10 may be thinned (in the direction of the arrow in fig. 4) from the surface of the substrate 10 facing away from the structural layer 20 by means of an automatic polisher or Chemical Mechanical Polishing (CMP), and the thickness of the resulting thinned substrate 10' is smaller than the thickness of the substrate 10 before thinning.
Because the thickness of the substrate is thicker and usually exceeds the thickness of the structural layer, the occupation ratio in the thickness of the structure to be detected is higher, when the mechanical strength of the structure to be detected is detected, the occupation ratio of the mechanical strength of the substrate in the overall mechanical strength of the structure to be detected is higher, the mechanical strength of the structural layer is not favorably reflected, when the transverse comparison is carried out, the mechanical strength of different positions in the same structure to be detected or the mechanical strength of the positions of the same target structure in the structure to be detected obtained from different target areas are not obviously different, and the analysis on the change of the mechanical strength of the structural layer is not favorably carried out.
This disclosed embodiment reduces the substrate and accounts for the ratio in the whole thickness of structure that awaits measuring through thinning to predetermineeing thickness with the substrate to reduce the mechanical strength of substrate and account for the ratio in the whole mechanical strength of structure that awaits measuring, make the whole mechanical strength of structure that awaits measuring that records more be close to the mechanical strength of structural layer, when making horizontal contrast, be convenient for analyze the difference between the mechanical strength.
In some embodiments, the predetermined thickness range is: 50 μm to 250 μm. For example, the thickness of the substrate of the structure to be tested is thinned to 100 μm or 150 μm, etc.
It can be understood that, when the thickness of the substrate is too large, it is inconvenient to analyze the mechanical strength of the structural layer on the substrate because it is relatively high in the overall thickness and mechanical strength of the structure to be measured. When the thickness of the substrate is too small, if the thickness of the structural layer is also small, the overall thickness of the structure to be measured is small, the strength is weak, and the structural sample to be measured may be easily broken. Therefore, the thickness of the substrate can be properly adjusted, the contribution ratio of the substrate in the overall mechanical strength of the structure to be detected is reduced, and meanwhile, the structure to be detected is ensured to have certain strength so as to be convenient to detect. It should be noted that, for different structures to be tested for lateral comparison, the substrate thickness needs to be kept consistent.
In some embodiments, the method further comprises:
after the substrate of the structure to be detected is thinned to a preset thickness, polishing the side face of the structure to be detected; wherein, the side of the structure to be tested is vertical to the substrate.
Illustratively, the target area on the semiconductor structure is rectangular, and the structure to be measured obtained by cutting out the target area is a cuboid structure. Referring to fig. 5, the structure to be tested 100 is a rectangular parallelepiped structure having two pairs of oppositely disposed side surfaces: the side surfaces 100a and 100a 'parallel to the long axis direction of the structure 100 to be tested, and the side surfaces 100b and 100b' parallel to the short axis direction of the structure 100 to be tested are perpendicular to the substrate.
Since the sides 100a and 100a 'and 100b' of the structure 100 to be measured are obtained by cutting out a target area in the semiconductor structure, the cutting-out method generally includes a physical mechanical method, and thus the sides 100a and 100a 'and the sides 100b and 100b' may be rough and uneven and may be prone to microcracks. When the mechanical strength of the structure to be detected is detected, the microcracks on the side surfaces may expand under the action of stress, and interfere with the detection of the mechanical strength of the structure to be detected.
For example, an automatic polishing machine may be used to perform fine polishing on the side surfaces 100a and 100a 'and the side surfaces 100b and 100b', remove micro cracks on the surfaces, reduce or eliminate the influence of the micro cracks on the detection of the mechanical strength of the structure to be detected, and improve the accuracy of the detection.
In some embodiments, only the side 100a and the side 100a' parallel to the long axis of the structure 100 to be tested may be polished.
In some embodiments, the thinned surface of the substrate of the structure under test may also have microcracks, which may also need to be polished to reduce or eliminate the effect of microcracks on the mechanical strength of the structure under test.
In some embodiments, the intercepting a target region in the semiconductor structure to be tested in step S110 includes:
by dicing the semiconductor structure, a portion of the target region in the semiconductor structure is obtained.
Illustratively, the semiconductor structure is a wafer formed with a device layer, the target area may be selected areas at different locations on the wafer, and the wafer may be diced using wire saw dicing or other dicing means to separate portions of the target area from the wafer.
In some embodiments, the target structure comprises at least one of the following structures in a 3D NAND memory:
a gate stack;
a channel hole;
and (3) a step structure.
Illustratively, in the manufacturing process of the 3D NAND memory, the gate stack is a stack structure formed by alternately stacking conductive layers and insulating layers on a semiconductor substrate, and further, a step structure is generally formed at an end portion of the stack structure to expose the conductive layers of different levels for establishing an electrical connection with the outside.
The channel hole is a hole structure penetrating through the gate stack in a direction perpendicular to the substrate, and is used for filling the memory layer and the channel layer to form a memory string.
It should be noted that the target structures listed in the present embodiment are only examples, and the target structures include, but are not limited to, the above-listed examples.
It will be appreciated that when the target structure in the structural layer comprises a gate stack, a channel hole or a step structure, the mechanical strength of the structural layer at the location of the different target structures is different. For example, the mechanical strength of the structure layer at the position where the channel hole is formed is different from that at the position where the step structure is formed.
In some embodiments, the step S130 of applying a load to the structure under test at the position of the target structure, and measuring the mechanical strength of the structure under test at the position of the target structure includes:
and applying gradually increased load to the structure to be tested, and determining the load value applied when the structure to be tested is damaged.
For example, when a load is applied to the structure to be measured at the position of the target structure, the applied load may gradually increase from 0, the structure to be measured is deformed by a stress, and finally breaks, and a load value of the structure to be measured at the time of breaking is stored, so as to represent the mechanical strength of the structure to be measured at the position of the target structure.
In some embodiments, step S130 includes: and measuring the bending strength of the structure to be measured by adopting a three-point bending test.
The structure to be measured is a cuboid structure, and the bending strength of the structure to be measured can be measured by adopting a three-point bending test, namely, the structure to be measured is placed on two supporting points with a certain span, a load is applied to the structure to be measured above the middle point of the span, and the bending strength of the structure to be measured can be represented by the load born by the structure to be measured when the structure to be measured is broken.
It should be noted that the three-point bending test method adopted in the embodiments of the present disclosure may be a method model for simulating a standard three-point bending test, and does not necessarily adopt a test standard of the standard three-point bending test. For example, the dimensions of the structure to be tested, the span between two support points, etc. do not necessarily adopt the test standards of the standard three-point bending test. But different structures to be tested adopt the same test standard so as to transversely compare the bending strength of the different structures to be tested.
In some embodiments, referring to fig. 6, a structure to be tested includes a substrate 10 'and a structural layer 20 on the substrate 10', the structural layer 20 having a target structure 30 therein;
in step S130, applying a load to the structure to be tested includes: a load is applied from the surface of the substrate 10' relatively remote from the structural layer 20.
When the bending strength of a sample is measured by a three-point bending test, the sample is placed on two supporting points with a certain span, and an increased load is continuously applied to the surface of the sample relatively far from the supporting points, so that the sample is firstly fractured from the surface close to the supporting points, and then a crack is expanded to the surface far from the two supporting points, and the whole sample is fractured.
Therefore, when the bending strength of the structure under test is measured by the three-point bending test, as shown in fig. 6, the surface 20a of the structural layer 20 in the structure under test may be brought into contact with two supporting points, and a load may be applied to the substrate surface 10' a opposite to the surface 20a of the structural layer 20 at a position aligned with the target structure 30, so that the structure under test may be fractured from the target structure. Thus, the measured bending strength of the structure to be measured is closer to the bending strength of the structural layer at the target structure 30, which is beneficial to improving the accuracy of analyzing the bending strength of the structural layer 20 at the target structure 30.
It should be noted that, when the bending strength of the structure to be tested is detected by using the three-point bending test method in the embodiment of the present disclosure, the two supporting points are not necessarily symmetrical with respect to the midpoint of the long axis of the structure to be tested. For example, referring to fig. 7, when the target structure 30 is not located at the middle of the structure to be measured but is located near one end of the structure to be measured, the center of the local region where the target structure is located may be located at the center of the span between two support points, and then a load may be applied above the center of the span between the two support points. When a plurality of structures to be detected are detected, the span between two supporting points is kept unchanged.
In some embodiments, applying a gradually increasing load to the structure under test, and determining the value of the applied load when the structure under test is damaged, includes:
applying a load which is increased at a constant rate to the structure to be measured, and measuring the deflection change of the structure to be measured to obtain a corresponding relation change curve of the load and the deflection;
and determining the load value when the structure to be tested is damaged through the catastrophe points on the curve.
It can be understood that the bending strength of the structure to be tested is detected by adopting a three-point bending test method, and a relation curve corresponding to the load and the deflection is obtained in the process of applying the load. Referring to fig. 8, before the structure to be measured is broken, the deflection is increased as the load is increased. And when the structure to be measured is broken, the deflection is not increased any more, and the load is suddenly changed to 0. The bending strength of the structure to be measured can be obtained through the load value corresponding to the catastrophe point (point P in figure 8) on the load-deflection relation curve.
Illustratively, the load can be applied to the structure to be measured through the automatic control system, the load is slowly increased at a small constant rate and continuously acts on the structure to be measured, so that the obtained load-deflection relation curve is smooth, the abrupt point on the curve can be accurately obtained, and the load value applied when the structure to be measured is broken can be accurately obtained.
It should be noted that although the present description is described in terms of embodiments, not every embodiment includes only a single technical solution, and such description of the embodiments is merely for clarity, and those skilled in the art should make the description as a whole, and the technical solutions in the embodiments may be appropriately combined to form other embodiments that can be understood by those skilled in the art.
The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present disclosure, and all the changes or substitutions should be covered within the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.
Claims (10)
1. A method for testing the strength of a semiconductor structure, comprising:
providing a semiconductor structure to be tested;
intercepting a target area in the semiconductor structure to be tested to obtain the structure to be tested;
determining the position of a target structure in the structure to be detected; wherein the target structure is located within the target region;
and applying a load to the structure to be measured at the position of the target structure, and measuring the mechanical strength of the position of the target structure in the structure to be measured.
2. The method of claim 1, wherein the structure under test comprises a substrate and a structural layer on the substrate, the structural layer having the target structure therein, the method further comprising:
and after the structure to be detected is obtained, thinning the substrate included by the structure to be detected to a preset thickness.
3. The method according to claim 2, wherein the predetermined thickness range is: 50 μm to 250 μm.
4. The method of claim 2, further comprising:
polishing the side surface of the structure to be detected after the substrate of the structure to be detected is thinned to a preset thickness; wherein the side is perpendicular to the substrate.
5. The method of claim 1, wherein said intercepting a target region in the semiconductor structure under test comprises:
and obtaining the part of the target area in the semiconductor structure by cutting the semiconductor structure.
6. The method of claim 1, wherein the target structure comprises at least one of the following structures in a 3D NAND memory:
a gate stack;
a channel hole;
and (3) a step structure.
7. The method of claim 1, wherein the applying a load to the structure under test at the location of the target structure and measuring the mechanical strength of the structure under test at the location of the target structure comprises:
and applying gradually increased load to the structure to be tested, and determining the load value applied when the structure to be tested is damaged.
8. The method of claim 7, wherein the method comprises: and measuring the bending strength of the structure to be measured by adopting a three-point bending test.
9. The method of claim 7, wherein the structure under test comprises a substrate and a structural layer on the substrate, the structural layer having the target structure therein;
the applying a load to the structure to be tested includes: a load is applied from a surface of the substrate relatively remote from the structural layer.
10. The method of claim 7, wherein the applying of the gradually increasing load to the structure under test and the determining of the value of the applied load when the structure under test is damaged comprises:
applying a load which is increased at a constant rate to the structure to be measured, and measuring the deflection change of the structure to be measured to obtain a corresponding relation change curve of the load and the deflection;
and determining the load value when the structure to be tested is damaged through the catastrophe points on the curve.
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