CN113705161A - UVM register model rapid generation method and system, and chip verification method and system - Google Patents
UVM register model rapid generation method and system, and chip verification method and system Download PDFInfo
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Abstract
The invention discloses a rapid UVM register model generation method and system and a chip verification method and system; the rapid UVM register model generation method comprises the following steps: defining a register table; converting the set register table into register model information; generating a register model according to the register model information obtained by conversion; and outputting the UVM register model. The rapid UVM model generation method and system, and the chip verification method and system disclosed by the invention can solve the problems of low efficiency and high error rate of manually compiling a fussy UVM model, and the UVM model can be immediately output only by a table in a module excel format provided by a designer, so that the fussy manual compiling process is saved, and the accuracy of the UVM model is ensured.
Description
Technical Field
The invention belongs to the technical field of microelectronics, relates to a chip verification system, and particularly relates to a rapid UVM register model generation method and a rapid UVM register model generation system.
Background
In the chip verification stage, firstly, the register configuration of the module to be tested is required, and the configuration is incorrect, which directly results in the failure of verification, so that the importance of the register configuration on the chip verification can be seen.
In the verification process using uvm as the verification methodology, the configuration process of the register depends on the register model, which mainly consists of three categories uvm _ reg _ block, uvm _ reg and uvm _ reg _ field, uvm _ reg _ block consists of uvm _ reg and uvm _ reg consists of uvm _ reg _ field.
When the number of registers of the verification module is large, hundreds of uvm _ reg _ block, uvm _ reg and uvm _ reg _ field classes exist in a register model, and a verifier needs to manually knock out the classes one register by one register according to a register table (excel) of a specific module to be tested, so that the task is heavy and the efficiency is low; and once the register table has large changes, the classes need to be knocked out again, and the efficiency and the progress of chip verification are affected.
In view of the above, there is a need to design a new chip verification method to overcome at least some of the above-mentioned defects of the existing chip verification methods.
Disclosure of Invention
The invention provides a rapid UVM model generation method and system, and a chip verification method and system, which can solve the problems of low efficiency and high error rate of manually compiling a fussy UVM model, and can immediately output the UVM model by only one table in a module excel format provided by a designer, thereby omitting the fussy manual compiling process and ensuring the accuracy of the UVM model.
In order to solve the technical problem, according to one aspect of the present invention, the following technical solutions are adopted:
a UVM register model fast generation method, the method comprising:
converting the set register table into register model information;
and generating a register model according to the register model information obtained by conversion.
As an embodiment of the present invention, the converting the setting register table into the register model information includes:
step A, reading a register table through perl script;
b, outputting register table information in a first text format through a perl script;
step C, analyzing the register table information in the first text format through the perl script;
and D, outputting register model information in a second text format according to the analyzed register table information in the first text format.
As an embodiment of the present invention, the generating a register model according to a register table includes:
storing all information by a perl hash storage method, and respectively storing matched Ral, sub _ reg _ block, sub _ reg and sub _ reg _ field by using 4 hashes, wherein the names of the 4 hashes are Ral, sub _ reg _ block, sub _ reg and sub _ reg _ field, the Ral hashes have two stages, the sub _ reg _ block hashes have three stages, the sub _ reg hashes have four stages, and the sub _ reg _ field hashes have five stages;
firstly initializing a Ral _ cnt, then reading register model information in a line of text format, sequentially judging whether the line is matched with Ral, sub _ reg _ block, sub _ reg and sub _ reg _ field, if not, judging whether the line is the register model information of the last line, if so, directly ending, otherwise, continuously reading the register model information in the line of text format, and continuously detecting the matching. If any one mode is matched, performing hash operation of storing the matching item;
according to the arrangement of register model information, when the register model information is matched with the Ral, setting sub _ reg _ block _ cnt to 0, preparing for storage of the matched sub _ reg _ block, respectively storing matching items into Ral hash by using the Ral _ cnt and NAME (and other information) as primary and secondary indexes, and then adding one to the Ral _ cnt to prepare for storage of the next matched Ral;
next, when sub _ reg _ block is matched, setting 0 to the sub _ reg _ cnt to prepare for storage matched to the sub _ reg, respectively storing the match items in the sub _ reg _ block hash by using the Ral _ cnt, the sub _ reg _ block _ cnt and the NAME (and other information) as primary, secondary and tertiary indexes, and then adding one to the sub _ reg _ block _ cnt to prepare for storage matched to the sub _ reg _ block next time;
when sub _ reg is matched, setting 0 to the sub _ reg _ field _ cnt, preparing for storage matched to the sub _ reg _ field, storing the matching items into sub _ reg hash by using Ral _ cnt, sub _ reg _ block _ cnt, sub _ reg _ cnt and NAME (other information) as first-level, second-level, third-level and fourth-level indexes respectively, and then adding one to the sub _ reg _ cnt to prepare for storage matched to the sub _ reg next time;
finally, when the sub _ reg _ field is matched, storing the matching items into the sub _ reg _ field hash by using the Ral _ cnt, the sub _ reg _ block _ cnt, the sub _ reg _ field _ cnt and the NAME (other information) as first-level, second-level, third-level, fourth-level and fifth-level indexes respectively, and then adding one to the sub _ reg _ field _ cnt to prepare for storage of the next matching to the sub _ reg _ field;
after any one of the four matches is matched and stored, judging whether the register model information is the last line of register model information, if so, directly ending, otherwise, continuously reading the information of a line of text register model information format, and continuing the matching operation;
when all information of the text register model information format is read, the information of a top layer uvm _ reg _ block corresponding to the Ral _ cnt number is stored in the Ral hash, and all sub uvm _ reg _ block information in the top layer uvm _ reg _ block corresponding to the Ral _ cnt number is stored in the sub _ reg _ block hash;
the sub uvm _ reg _ block is numbered as sub _ reg _ block _ cnt, and sub _ reg hash stores all sub uvm _ reg information in a sub uvm _ reg _ block corresponding to the sub _ reg _ block number in a top layer uvm _ reg _ block corresponding to the Ral _ cnt number;
sub uvm _ reg is numbered sub _ reg _ cnt, the storage of the sub _ reg _ field hash is analogized;
so far, the four hashes store all information required for constructing uvm register models, and a uvm register model file can be output in a top-down form only by sequentially traversing the Ral, sub _ reg _ block, sub _ reg, and sub _ reg _ field hashes from the Ral hash to the lower 4-layer nesting and outputting according to the format of the uvm register model.
As an embodiment of the present invention, the method further comprises: defining a register table; the register table includes a base address, an offset address of each register, a register name, a width, a name, and read-write attributes of a register sub-field.
As an embodiment of the present invention, the method further comprises: and outputting the UVM register model.
According to another aspect of the invention, the following technical scheme is adopted: a UVM register model fast generation system, the system comprising:
the register model information conversion module is used for converting the set register table into register model information;
and the register model generation module is used for generating a register model according to the register model information obtained by conversion.
As an embodiment of the present invention, the register model information conversion module includes:
the register table reading unit is used for reading the register table through the perl script;
the first register table information output unit is used for outputting register table information in a first text format through perl scripts;
the register table information analysis unit is used for analyzing the register table information in the first text format through the perl script;
and the second register model information output unit is used for outputting the register model information in the second text format according to the register table information in the first text format obtained by analysis.
As an embodiment of the present invention, the processing procedure of the register model generation module includes:
storing all information by a perl hash storage method, and respectively storing matched Ral, sub _ reg _ block, sub _ reg and sub _ reg _ field by using 4 hashes, wherein the names of the 4 hashes are Ral, sub _ reg _ block, sub _ reg and sub _ reg _ field, the Ral hashes have two stages, the sub _ reg _ block hashes have three stages, the sub _ reg hashes have four stages, and the sub _ reg _ field hashes have five stages;
firstly initializing a Ral _ cnt, then reading register model information in a line of text format, sequentially judging whether the line is matched with Ral, sub _ reg _ block, sub _ reg and sub _ reg _ field, if not, judging whether the line is the register model information of the last line, if so, directly ending, otherwise, continuously reading the register model information in the line of text format, and continuously detecting the matching. If any one mode is matched, performing hash operation of storing the matching item;
according to the arrangement of register model information, when the register model information is matched with the Ral, setting sub _ reg _ block _ cnt to 0, preparing for storage of the matched sub _ reg _ block, respectively storing matching items into Ral hash by using the Ral _ cnt and NAME (and other information) as primary and secondary indexes, and then adding one to the Ral _ cnt to prepare for storage of the next matched Ral;
next, when sub _ reg _ block is matched, setting 0 to the sub _ reg _ cnt to prepare for storage matched to the sub _ reg, respectively storing the match items in the sub _ reg _ block hash by using the Ral _ cnt, the sub _ reg _ block _ cnt and the NAME (and other information) as primary, secondary and tertiary indexes, and then adding one to the sub _ reg _ block _ cnt to prepare for storage matched to the sub _ reg _ block next time;
when sub _ reg is matched, setting 0 to the sub _ reg _ field _ cnt, preparing for storage matched to the sub _ reg _ field, storing the matching items into sub _ reg hash by using Ral _ cnt, sub _ reg _ block _ cnt, sub _ reg _ cnt and NAME (other information) as first-level, second-level, third-level and fourth-level indexes respectively, and then adding one to the sub _ reg _ cnt to prepare for storage matched to the sub _ reg next time;
finally, when the sub _ reg _ field is matched, storing the matching items into the sub _ reg _ field hash by using the Ral _ cnt, the sub _ reg _ block _ cnt, the sub _ reg _ field _ cnt and the NAME (other information) as first-level, second-level, third-level, fourth-level and fifth-level indexes respectively, and then adding one to the sub _ reg _ field _ cnt to prepare for storage of the next matching to the sub _ reg _ field;
after any one of the four matches is matched and stored, judging whether the register model information is the last line of register model information, if so, directly ending, otherwise, continuously reading the information of a line of text register model information format, and continuing the matching operation;
when all information of the text register model information format is read, the information of a top layer uvm _ reg _ block corresponding to the Ral _ cnt number is stored in the Ral hash, and all sub uvm _ reg _ block information in the top layer uvm _ reg _ block corresponding to the Ral _ cnt number is stored in the sub _ reg _ block hash;
the sub uvm _ reg _ block is numbered as sub _ reg _ block _ cnt, and sub _ reg hash stores all sub uvm _ reg information in a sub uvm _ reg _ block corresponding to the sub _ reg _ block number in a top layer uvm _ reg _ block corresponding to the Ral _ cnt number;
sub uvm _ reg is numbered sub _ reg _ cnt, the storage of the sub _ reg _ field hash is analogized;
so far, the four hashes store all information required for constructing uvm register models, and a uvm register model file can be output in a top-down form only by sequentially traversing the Ral, sub _ reg _ block, sub _ reg, and sub _ reg _ field hashes from the Ral hash to the lower 4-layer nesting and outputting according to the format of the uvm register model.
As an embodiment of the present invention, the system further includes: the register table definition module is used for defining a register table; the register table includes a base address, an offset address of each register, a register name, a width, a name, and read-write attributes of a register sub-field.
As an embodiment of the present invention, the system further includes: and the register model output module is used for outputting the UVM register model.
According to another aspect of the invention, the following technical scheme is adopted: a chip verification method comprises the rapid UVM register model generation method.
According to another aspect of the invention, the following technical scheme is adopted: a chip verification system comprises the UVM register model rapid generation system.
The invention has the beneficial effects that: the rapid UVM model generation method and system, and the chip verification method and system provided by the invention can solve the problems of low efficiency and high error rate of manually compiling a fussy UVM model, and the UVM model can be immediately output only by a table in a module excel format provided by a designer, so that the fussy manual compiling process is saved, and the accuracy of the UVM model is ensured.
Drawings
FIG. 1 is a schematic diagram of script-based register model generation
FIG. 2 is a diagram of a register table format.
FIG. 3 is a diagram of register table information in text format.
FIG. 4 is a diagram of register model information in text format.
FIG. 5 is a diagram of an uvm register model.
FIG. 6 is a diagram illustrating a register model information storage process.
Detailed Description
Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
For a further understanding of the invention, reference will now be made to the preferred embodiments of the invention by way of example, and it is to be understood that the description is intended to further illustrate features and advantages of the invention, and not to limit the scope of the claims.
The description in this section is for several exemplary embodiments only, and the present invention is not limited only to the scope of the embodiments described. It is within the scope of the present disclosure and protection that the same or similar prior art means and some features of the embodiments may be interchanged.
The steps in the embodiments in the specification are only expressed for convenience of description, and the implementation manner of the present application is not limited by the order of implementation of the steps. The term "connected" in the specification includes both direct connection and indirect connection.
Referring to fig. 1, the present invention discloses a method for fast generating a UVM register model, which includes:
step S0 defines a register table. In one embodiment, the register table includes a base address, an offset address for each register, a register name, a width of a register sub-field, a name, and read and write attributes.
Of course, the method may not include step S0, and the register table may be defined in advance.
Step S1, converting the setting register table into register model information;
in an embodiment of the present invention, the step S1 includes:
step S11, read the register table through perl script (other scripts may be selected). And reading the register table line by line through a perl script ParseExcl module, and outputting the read contents of each line in a text file format, namely a first text format. In an embodiment, the register table is in an excel format, as shown in fig. 2.
And step S12, outputting the register table information in the first text format through perl script.
In an embodiment of the present invention, the first text format is as shown in fig. 3, in the first text format, starting from the second line, the Base Address of the register model is specified by Base Address, the Bus data bit Width is specified by Bus Width, the first occurring # addr is 0x0 i2c _ config specifies a sub uvm _ reg name of the register model as i2c _ config, the offset Address relative to the Base Address is 0x0, the information of [31:28] 4'd 0 r/crjj 2c _ deg _ cnt, [23:20] 4' b/crjj 2c _ pkt _ dir indicates a sub uvm _ reg _ field of the i2c _ config sub-block, the position is 32bit Width data: 28. 23:20, r/w indicates that the attribute of the child uvm _ reg _ field is readable and writable, cr _ i2c _ deg _ cnt and cr _ i2c _ pkt _ dir are the names of the child uvm _ reg _ field, respectively, # addr ═ 0x4 i2c _ int _ sts, as above. In one embodiment, the register table information is output in a text format as shown in FIG. 3.
And step S13, analyzing the register table information in the first text format through perl script. In one embodiment, the register model information is output in a text format in the format of FIG. 4.
And step S14, outputting register model information in a second text format according to the analyzed register table information in the first text format, and preparing for generating a register model.
In an embodiment of the invention, the second text format is as shown in fig. 4, the first line Ral i2c _ soc70740 UVM _ LITTLE _ enhanced UVM _ NO _ COVERAGE 0 indicates the name of register model is Ral i2c _ soc707, the remaining parameters are professional parameters of register model, the second line sub _ reg _ block i2c UVM _ LITTLE _ end UVM _ NO _ COVERAGE 040018000 XXX indicates the name of a sub-block of Ral i2c _ soc707 as i2c, 40018000 as base address of sub-block, the third line sub _ reg i2c _ config 32UVM _ NO _ COVERAGE 0 indicates that a sub-block UVM _ reg of remaining sub-block i2c is i2c _ config, the fourth to tenth lines indicate sub _ reg 2 _ reg _ field 32UVM _ NO _ COVERAGE RW 3, etc. contain the names of sub _ i2 _ reg _ i2 _ config 3, sub _ reg _ 5 _ ref _ id _ ref _ i _ ref _ c _ ref _ 5, etc. respectively.
Referring to fig. 4, fig. 4 includes names of top layers uvm _ reg _ block, such as Ral _ i2c _ soc707, sub uvm _ reg _ block, such as i2c, uvm _ reg, such as i2c _ config, and uvm _ reg _ field, such as cr _ i2c _ deg _ cnt, contents appearing below Ral all belong to uvm _ reg _ block of the top layer until next top layer Ral appears, sub _ reg appearing below sub _ reg _ block all belong to sub _ reg _ block of the current time until next sub _ reg _ block appears, and sub _ reg _ field below sub _ reg _ block all belong to sub _ reg of the current time until next sub _ reg _ block appears, and the hierarchy is clear.
Step S2, a register model is generated from the converted register model information.
In one embodiment, the register model information in the second text format is read to generate a corresponding register model.
In an embodiment of the present invention, the step of generating the register model according to the register table includes:
and outputting the UVM register model, wherein all register model information in a text format is required. In one embodiment, all information is stored by perl hash storage. As shown in fig. 6, a total of 4 hashes are used to store matched Ral, sub _ reg _ block, sub _ reg, and sub _ reg _ field, the names of the 4 hashes are Ral, sub _ reg _ block, sub _ reg, and sub _ reg _ field, respectively, the Ral hash has two stages, the sub _ reg _ block hash has three stages, the sub _ reg hash has four stages, and the sub _ reg _ field hash has five stages.
Firstly initializing a Ral _ cnt, then reading register model information in a line of text format, sequentially judging whether the line is matched with Ral, sub _ reg _ block, sub _ reg and sub _ reg _ field, if not, judging whether the line is the register model information of the last line, if so, directly ending, otherwise, continuously reading the register model information in the line of text format, and continuously detecting the matching. And if any mode is matched, performing matching item storage hash operation.
According to the arrangement of register model information, when the register model information is matched with the Ral, setting sub _ reg _ block _ cnt to 0 to prepare for storage of the matched sub _ reg _ block, respectively storing matching items in the Ral hash by using the Ral _ cnt and the NAME (and other information) as primary and secondary indexes, and then adding one to the Ral _ cnt to prepare for storage of the next matched Ral.
And when the sub _ reg _ block is matched, setting 0 to the sub _ reg _ cnt to prepare for storage matched with the sub _ reg, storing the matched items in the sub _ reg _ block hash by using the Ral _ cnt, the sub _ reg _ block _ cnt and the NAME (and other information) as primary, secondary and tertiary indexes respectively, and adding one to the sub _ reg _ block _ cnt to prepare for storage matched with the sub _ reg _ block next time.
And when the sub _ reg is matched, setting the sub _ reg _ field _ cnt to 0 to prepare for storage matched to the sub _ reg _ field, storing the matched items into the sub _ reg hash by using the Ral _ cnt, the sub _ reg _ block _ cnt, the sub _ reg _ cnt and the NAME (other information) as first-level, second-level, third-level and fourth-level indexes respectively, and then adding one to the sub _ reg _ cnt to prepare for storage matched to the sub _ reg next time.
And finally, when the sub _ reg _ field is matched, storing the matching items into the sub _ reg _ field hash by using the Ral _ cnt, the sub _ reg _ block _ cnt, the sub _ reg _ field _ cnt and the NAME (other information) as first-level, second-level, third-level, fourth-level and fifth-level indexes respectively, and then adding one to the sub _ reg _ field _ cnt to prepare for storage of the next matching to the sub _ reg _ field.
After any one of the four matches is matched and stored, whether the register model information is the last line of register model information is judged, if so, the process is ended directly, otherwise, the information of a line of text register model information format is read continuously, and the matching operation is continued.
When all information of the text register model information format is read, the information of a top layer uvm _ reg _ block corresponding to the Ral _ cnt number is stored in the Ral hash, and the information of all sub uvm _ reg _ blocks in the top layer uvm _ reg _ block corresponding to the Ral _ cnt number is stored in the sub _ reg _ block hash.
The sub uvm _ reg _ block is numbered as sub _ reg _ block _ cnt, and sub _ reg hash stores all sub uvm _ reg information in a sub uvm _ reg _ block corresponding to the sub _ reg _ block number in the top layer uvm _ reg _ block corresponding to the Ral _ cnt number.
The sub uvm _ reg is numbered sub _ reg _ cnt, the storage of the sub _ reg _ field hash is analogized. Specifically, the Ral hash stores therein information of all top layers UVM _ reg _ block, such as Ral _ i2c _ soc70740 UVM _ light _ end UVM _ NO _ COVERAGE 0 information; the sub _ reg _ block hash stores all sub UVM _ reg _ block information, such as sub _ reg _ block i2c 40UVM _ light _ end UVM _ NO _ covering 040018000 XXX information; the sub _ reg hash stores all sub UVM _ reg information, such as sub _ reg i2c _ config 32UVM _ NO _ COVERAGE RW 0; the sub _ reg _ field hash stores all sub uvm _ reg _ field information, such as sub _ reg _ field cr _ i2c _ deg _ cnt 428 RW 00110 XXX information.
So far, the four hashes store all information required for constructing uvm register models, and a uvm register model file can be output in a top-down form only by sequentially traversing the Ral, sub _ reg _ block, sub _ reg, and sub _ reg _ field hashes from the Ral hash to the lower 4-layer nesting and outputting according to the format of the uvm register model.
Step S3 outputs the UVM register model. Referring to fig. 5, in an embodiment, the UVM register model shown in fig. 5 is output.
Of course, the method may not include step S3.
The invention also discloses a rapid UVM register model generation system, which comprises: a register model information conversion module 1 and a register model generation module 2. The register model information conversion module 1 is used for converting a set register table into register model information; the register model generation module 2 is used for generating a register model according to the register model information obtained by conversion.
In an embodiment of the present invention, the register model information conversion module 1 includes: register table reading section 11, first register table information output section 12, register table information analyzing section 13, and second register model information output section 14.
The register table reading unit 11 is used for reading a register table through perl scripts; and reading the register table line by line through a perl script ParseExcl module, and outputting the read contents of each line in a text file format, namely a first text format.
The first register table information output unit 12 is configured to output register table information in a first text format through perl script. First text format as in fig. 3, in the first text format, starting from the second line, the Base Address of the register model is specified by Base Address, the Bus data bit Width is specified by Bus Width, the first occurrence of # addr ═ 0x0 i2c _ config specifies a sub uvm _ reg name of the register model as i2c _ config, the offset Address relative to the Base Address is 0x0, the immediately following information of [31:28] 4'd 0 r/cri 2c _ deg _ cnt, [23:20] 4' b1111 r/cri 2c _ pkt _ dir indicates a sub uvm _ reg _ field of the sub-block of i2c _ config, the position is 32bit Width data: 28. 23:20, r/w indicates that the attribute of the child uvm _ reg _ field is readable and writable, cr _ i2c _ deg _ cnt and cr _ i2c _ pkt _ dir are the names of the child uvm _ reg _ field, respectively, # addr ═ 0x4 i2c _ int _ sts, as above.
The register table information parsing unit 13 is configured to parse the register table information in the first text format through the perl script.
The second register model information output unit 14 is configured to output register model information in a second text format according to the parsed register table information in the first text format. A second text format is shown in fig. 4, the first line Ral i2c _ soc70740 UVM LI TTLE _ endin UVM _ NO _ covering 0 indicates the name ra l _ i2c _ soc707 of the register model, the remaining parameters are professional parameters of the register model, the second line sub _ reg _ block i2c UVM _ LITTLE _ endin UVM _ NO _ covering 040018000 XXX indicates the name i2c of a sub-block of Ral i2c _ soc707, 40018000 is the base address of the sub-block, the third line sub _ reg i2c _ config 32UVM _ NO _ covering RW 0 indicates a sub-block i 2UVM _ reg of sub-block i2c is i2 _ config, the fourth to tenth lines indicate sub _ reg _ config _ i UVM _ reg _ 3 _ decoder 2 _ c _ i _.
In an embodiment of the present invention, the processing procedure of the register model generation module includes:
all information stored by a perl hash storage method is stored, and matched Ral, sub _ reg _ block, sub _ reg and sub _ reg _ field are respectively stored by 4 hashes, wherein the names of the 4 hashes are Ral, sub _ reg _ block, sub _ reg and sub _ reg _ field, the Ral hashes have two stages, the sub _ reg _ block hashes have three stages, the sub _ reg hashes have four stages, and the sub _ reg _ field hashes have five stages.
Firstly initializing a Ral _ cnt, then reading register model information in a line of text format, sequentially judging whether the line is matched with Ral, sub _ reg _ block, sub _ reg and sub _ reg _ field, if not, judging whether the line is the register model information of the last line, if so, directly ending, otherwise, continuously reading the register model information in the line of text format, and continuously detecting the matching. And if any mode is matched, performing matching item storage hash operation.
According to the arrangement of register model information, when the register model information is matched with the Ral, setting sub _ reg _ block _ cnt to 0 to prepare for storage of the matched sub _ reg _ block, respectively storing matching items in the Ral hash by using the Ral _ cnt and the NAME (and other information) as primary and secondary indexes, and then adding one to the Ral _ cnt to prepare for storage of the next matched Ral.
And when the sub _ reg _ block is matched, setting 0 to the sub _ reg _ cnt to prepare for storage matched with the sub _ reg, storing the matched items in the sub _ reg _ block hash by using the Ral _ cnt, the sub _ reg _ block _ cnt and the NAME (and other information) as primary, secondary and tertiary indexes respectively, and adding one to the sub _ reg _ block _ cnt to prepare for storage matched with the sub _ reg _ block next time.
And when the sub _ reg is matched, setting the sub _ reg _ field _ cnt to 0 to prepare for storage matched to the sub _ reg _ field, storing the matched items into the sub _ reg hash by using the Ral _ cnt, the sub _ reg _ block _ cnt, the sub _ reg _ cnt and the NAME (other information) as first-level, second-level, third-level and fourth-level indexes respectively, and then adding one to the sub _ reg _ cnt to prepare for storage matched to the sub _ reg next time.
And finally, when the sub _ reg _ field is matched, storing the matching items into the sub _ reg _ field hash by using the Ral _ cnt, the sub _ reg _ block _ cnt, the sub _ reg _ field _ cnt and the NAME (other information) as first-level, second-level, third-level, fourth-level and fifth-level indexes respectively, and then adding one to the sub _ reg _ field _ cnt to prepare for storage of the next matching to the sub _ reg _ field.
After any one of the four matches is matched and stored, whether the register model information is the last line of register model information is judged, if so, the process is ended directly, otherwise, the information of a line of text register model information format is read continuously, and the matching operation is continued.
When all information of the text register model information format is read, the information of a top layer uvm _ reg _ block corresponding to the Ral _ cnt number is stored in the Ral hash, and the information of all sub uvm _ reg _ blocks in the top layer uvm _ reg _ block corresponding to the Ral _ cnt number is stored in the sub _ reg _ block hash. The sub uvm _ reg _ block is numbered as sub _ reg _ block _ cnt, and sub _ reg hash stores all sub uvm _ reg information in a sub uvm _ reg _ block corresponding to the sub _ reg _ block number in the top layer uvm _ reg _ block corresponding to the Ral _ cnt number. The sub uvm _ reg is numbered sub _ reg _ cnt, the storage of the sub _ reg _ field hash is analogized.
So far, the four hashes store all information required for constructing uvm register models, and a uvm register model file can be output in a top-down form only by sequentially traversing the Ral, sub _ reg _ block, sub _ reg, and sub _ reg _ field hashes from the Ral hash to the lower 4-layer nesting and outputting according to the format of the uvm register model.
In an embodiment, the system may further include: a register table definition module 3 and a register model output module 4; the register table definition module is used for defining a register table; the register table includes a base address, offset addresses of the registers, register names, widths, names, and read-write attributes of register sub-fields. The register model output module 4 is used for outputting the UVM register model.
The invention also discloses a chip verification method which comprises the rapid UVM register model generation method.
The invention further discloses a chip verification system which comprises the rapid UVM register model generation system.
In summary, the rapid generation method and system for the UVM register model, and the chip verification method and system provided by the invention can solve the problems of low efficiency and high error rate of manually writing a fussy UVM register model, and the UVM register model can be immediately output only by one table in the module excel format provided by a designer, so that the fussy manual writing process is omitted, and the accuracy of the UVM register model is ensured.
It should be noted that the present application may be implemented in software and/or a combination of software and hardware; for example, it may be implemented using Application Specific Integrated Circuits (ASICs), general purpose computers, or any other similar hardware devices. In some embodiments, the software programs of the present application may be executed by a processor to implement the above steps or functions. As such, the software programs (including associated data structures) of the present application can be stored in a computer-readable recording medium; such as RAM memory, magnetic or optical drives or diskettes, and the like. In addition, some steps or functions of the present application may be implemented using hardware; for example, as circuitry that cooperates with the processor to perform various steps or functions.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The description and applications of the invention herein are illustrative and are not intended to limit the scope of the invention to the embodiments described above. Effects or advantages referred to in the embodiments may not be reflected in the embodiments due to interference of various factors, and the description of the effects or advantages is not intended to limit the embodiments. Variations and modifications of the embodiments disclosed herein are possible, and alternative and equivalent various components of the embodiments will be apparent to those skilled in the art. It will be clear to those skilled in the art that the present invention may be embodied in other forms, structures, arrangements, proportions, and with other components, materials, and parts, without departing from the spirit or essential characteristics thereof. Other variations and modifications of the embodiments disclosed herein may be made without departing from the scope and spirit of the invention.
Claims (10)
1. A rapid UVM register model generation method is characterized by comprising the following steps:
converting the set register table into register model information;
and generating a register model according to the register model information obtained by conversion.
2. A UVM register model fast generation method according to claim 1, wherein:
the step of converting the set register table into register model information includes:
step A, reading a register table through perl script;
b, outputting register table information in a first text format through a perl script;
step C, analyzing the register table information in the first text format through the perl script;
and D, outputting register model information in a second text format according to the analyzed register table information in the first text format.
3. A UVM register model fast generation method according to claim 1, wherein:
the step of generating a register model from a register table includes:
storing all information by a perl hash storage method, and respectively storing matched Ral, sub _ reg _ block, sub _ reg and sub _ reg _ field by using 4 hashes, wherein the names of the 4 hashes are Ral, sub _ reg _ block, sub _ reg and sub _ reg _ field, the Ral hashes have two stages, the sub _ reg _ block hashes have three stages, the sub _ reg hashes have four stages, and the sub _ reg _ field hashes have five stages;
firstly initializing a Ral _ cnt, then reading register model information in a line of text format, sequentially judging whether the line is matched with Ral, sub _ reg _ block, sub _ reg and sub _ reg _ field, if not, judging whether the line is the register model information of the last line, if so, directly ending, otherwise, continuously reading the register model information in the line of text format, and continuously detecting the matching. If any one mode is matched, performing hash operation of storing the matching item;
according to the arrangement of register model information, when the register model information is matched with the Ral, setting sub _ reg _ block _ cnt to be 0, preparing for storage of the matched sub _ reg _ block, storing matching items in the Ral hash by respectively using the Ral _ cnt and the NAME as primary indexes and secondary indexes, and then adding one to the Ral _ cnt to prepare for storage of the next matching to the Ral;
when sub _ reg _ block is matched, setting 0 to the sub _ reg _ cnt to prepare for storage matched to the sub _ reg, storing the matched items in the sub _ reg _ block hash by respectively using the Ral _ cnt, the sub _ reg _ block _ cnt and the NAME as first-level, second-level and third-level indexes, and then adding one to the sub _ reg _ block _ cnt to prepare for storage matched to the sub _ reg _ block next time;
when next sub _ reg is matched, setting 0 to the sub _ reg _ field _ cnt, preparing for storage matched to the sub _ reg _ field, storing the matching items into sub _ reg hash by using Ral _ cnt, sub _ reg _ block _ cnt, sub _ reg _ cnt and NAME as first-level, second-level, third-level and fourth-level indexes respectively, and then adding one to the sub _ reg _ cnt to prepare for storage matched to the sub _ reg next time;
finally, when the sub _ reg _ field is matched, storing the matching items into the sub _ reg _ field hash by using the indexes of Ral _ cnt, sub _ reg _ block _ cnt, sub _ reg _ field _ cnt and NAME as a first-level index, a second-level index, a third-level index, a fourth-level index and a fifth-level index respectively, and then adding one to the sub _ reg _ field _ cnt to prepare for storing the next matching to the sub _ reg _ field;
after any one of the four matches is matched and stored, judging whether the register model information is the last line of register model information, if so, directly ending, otherwise, continuously reading the information of a line of text register model information format, and continuing the matching operation;
when all information of the text register model information format is read, the information of a top layer uvm _ reg _ block corresponding to the Ral _ cnt number is stored in the Ral hash, and all sub uvm _ reg _ block information in the top layer uvm _ reg _ block corresponding to the Ral _ cnt number is stored in the sub _ reg _ block hash;
the sub uvm _ reg _ block is numbered as sub _ reg _ block _ cnt, and sub _ reg hash stores all sub uvm _ reg information in a sub uvm _ reg _ block corresponding to the sub _ reg _ block number in a top layer uvm _ reg _ block corresponding to the Ral _ cnt number;
sub uvm _ reg is numbered sub _ reg _ cnt, the storage of the sub _ reg _ field hash is analogized;
so far, the four hashes store all information required for constructing uvm register models, and a uvm register model file can be output in a top-down form only by sequentially traversing the Ral, sub _ reg _ block, sub _ reg, and sub _ reg _ field hashes from the Ral hash to the lower 4-layer nesting and outputting according to the format of the uvm register model.
4. A UVM register model fast generation method according to claim 1, wherein:
the method further comprises:
defining a register table; the register table comprises a base address, an offset address and a register name of each register, and the width, the name and the read-write attributes of a register sub-field;
the method further comprises: and outputting the UVM register model.
5. A UVM register model fast generation system, the system comprising:
the register model information conversion module is used for converting the set register table into register model information;
and the register model generation module is used for generating a register model according to the register model information obtained by conversion.
6. A UVM register model fast generation system according to claim 5, characterised in that:
the register model information conversion module includes:
the register table reading unit is used for reading the register table through the perl script;
the first register table information output unit is used for outputting register table information in a first text format through perl scripts;
the register table information analysis unit is used for analyzing the register table information in the first text format through the perl script;
and the second register model information output unit is used for outputting the register model information in the second text format according to the register table information in the first text format obtained by analysis.
7. A UVM register model fast generation system according to claim 5, characterised in that:
the processing procedure of the register model generation module comprises the following steps:
storing all information by a perl hash storage method, and respectively storing matched Ral, sub _ reg _ block, sub _ reg and sub _ reg _ field by using 4 hashes, wherein the names of the 4 hashes are Ral, sub _ reg _ block, sub _ reg and sub _ reg _ field, the Ral hashes have two stages, the sub _ reg _ block hashes have three stages, the sub _ reg hashes have four stages, and the sub _ reg _ field hashes have five stages;
firstly initializing a Ral _ cnt, then reading register model information in a line of text format, sequentially judging whether the line is matched with Ral, sub _ reg _ block, sub _ reg and sub _ reg _ field, if not, judging whether the line is the register model information of the last line, if so, directly ending, otherwise, continuously reading the register model information in the line of text format, and continuously detecting the matching. If any one mode is matched, performing hash operation of storing the matching item;
according to the arrangement of register model information, when the register model information is matched with the Ral, setting sub _ reg _ block _ cnt to be 0, preparing for storage of the matched sub _ reg _ block, storing matching items in the Ral hash by respectively using the Ral _ cnt and the NAME as primary indexes and secondary indexes, and then adding one to the Ral _ cnt to prepare for storage of the next matching to the Ral;
when sub _ reg _ block is matched, setting 0 to the sub _ reg _ cnt to prepare for storage matched to the sub _ reg, storing the matched items in the sub _ reg _ block hash by respectively using the Ral _ cnt, the sub _ reg _ block _ cnt and the NAME as first-level, second-level and third-level indexes, and then adding one to the sub _ reg _ block _ cnt to prepare for storage matched to the sub _ reg _ block next time;
when next sub _ reg is matched, setting 0 to the sub _ reg _ field _ cnt, preparing for storage matched to the sub _ reg _ field, storing the matching items into sub _ reg hash by using Ral _ cnt, sub _ reg _ block _ cnt, sub _ reg _ cnt and NAME as first-level, second-level, third-level and fourth-level indexes respectively, and then adding one to the sub _ reg _ cnt to prepare for storage matched to the sub _ reg next time;
finally, when the sub _ reg _ field is matched, storing the matching items into the sub _ reg _ field hash by using the indexes of Ral _ cnt, sub _ reg _ block _ cnt, sub _ reg _ field _ cnt and NAME as a first-level index, a second-level index, a third-level index, a fourth-level index and a fifth-level index respectively, and then adding one to the sub _ reg _ field _ cnt to prepare for storing the next matching to the sub _ reg _ field;
after any one of the four matches is matched and stored, judging whether the register model information is the last line of register model information, if so, directly ending, otherwise, continuously reading the information of a line of text register model information format, and continuing the matching operation;
when all information of the text register model information format is read, the information of a top layer uvm _ reg _ block corresponding to the Ral _ cnt number is stored in the Ral hash, and all sub uvm _ reg _ block information in the top layer uvm _ reg _ block corresponding to the Ral _ cnt number is stored in the sub _ reg _ block hash;
the sub uvm _ reg _ block is numbered as sub _ reg _ block _ cnt, and sub _ reg hash stores all sub uvm _ reg information in a sub uvm _ reg _ block corresponding to the sub _ reg _ block number in a top layer uvm _ reg _ block corresponding to the Ral _ cnt number;
sub uvm _ reg is numbered sub _ reg _ cnt, the storage of the sub _ reg _ field hash is analogized;
so far, the four hashes store all information required for constructing uvm register models, and a uvm register model file can be output in a top-down form only by sequentially traversing the Ral, sub _ reg _ block, sub _ reg, and sub _ reg _ field hashes from the Ral hash to the lower 4-layer nesting and outputting according to the format of the uvm register model.
8. A UVM register model fast generation system according to claim 5, characterised in that:
the system further comprises:
the register table definition module is used for defining a register table; the register table comprises a base address, an offset address and a register name of each register, and the width, the name and the read-write attributes of a register sub-field;
the system further comprises: and the register model output module is used for outputting the UVM register model.
9. A chip verification method is characterized in that: a method for fast UVM register model generation comprising any one of claims 1 to 4.
10. A chip verification system, comprising: a UVM register model fast generation system including any of claims 5 to 8.
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1845066A (en) * | 2006-05-16 | 2006-10-11 | 北京启明星辰信息技术有限公司 | Automatic protocol recognition method and system |
| US20090222778A1 (en) * | 2008-02-28 | 2009-09-03 | Atsuko Goto | Property generating apparatus, property generating method and program |
| CN103838653A (en) * | 2012-11-27 | 2014-06-04 | 上海华虹集成电路有限责任公司 | Register automatic authentication method based on VMM RAL |
| CN106293625A (en) * | 2015-06-09 | 2017-01-04 | 中兴通讯股份有限公司 | A kind of method and apparatus of configuration register |
| US20180300431A1 (en) * | 2017-04-18 | 2018-10-18 | Raytheon Company | Universal verification methodology (uvm) register abstraction layer (ral) traffic predictor |
| CN110187919A (en) * | 2019-05-27 | 2019-08-30 | 眸芯科技（上海）有限公司 | The device of configuration register, method and system |
| CN112131829A (en) * | 2020-09-18 | 2020-12-25 | 山东云海国创云计算装备产业创新中心有限公司 | Verification method, system and related device of chip register |
-
2021
- 2021-08-10 CN CN202110912228.8A patent/CN113705161B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1845066A (en) * | 2006-05-16 | 2006-10-11 | 北京启明星辰信息技术有限公司 | Automatic protocol recognition method and system |
| US20090222778A1 (en) * | 2008-02-28 | 2009-09-03 | Atsuko Goto | Property generating apparatus, property generating method and program |
| CN103838653A (en) * | 2012-11-27 | 2014-06-04 | 上海华虹集成电路有限责任公司 | Register automatic authentication method based on VMM RAL |
| CN106293625A (en) * | 2015-06-09 | 2017-01-04 | 中兴通讯股份有限公司 | A kind of method and apparatus of configuration register |
| US20180300431A1 (en) * | 2017-04-18 | 2018-10-18 | Raytheon Company | Universal verification methodology (uvm) register abstraction layer (ral) traffic predictor |
| CN110187919A (en) * | 2019-05-27 | 2019-08-30 | 眸芯科技（上海）有限公司 | The device of configuration register, method and system |
| CN112131829A (en) * | 2020-09-18 | 2020-12-25 | 山东云海国创云计算装备产业创新中心有限公司 | Verification method, system and related device of chip register |
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