CN113691469B

CN113691469B - Message disorder rearrangement method and single board

Info

Publication number: CN113691469B
Application number: CN202110852438.2A
Authority: CN
Inventors: 金亦锋; 林晖; 王彬
Original assignee: New H3C Technologies Co Ltd Hefei Branch
Current assignee: New H3C Technologies Co Ltd Hefei Branch
Priority date: 2021-07-27
Filing date: 2021-07-27
Publication date: 2023-12-26
Anticipated expiration: 2041-07-27
Also published as: CN113691469A

Abstract

The application provides a message disorder rearrangement method and a single board, wherein the method comprises the steps of being applied to a first single board, and is characterized in that messages sent by a second single board through a plurality of HIG links are received, combined and mapped to a plurality of signal channels; the message is segmented and stored, and the head address of the message segmentation and the number of stored segments are recorded; judging whether the message is required to be sequenced, if so, taking out the message fragments for sequencing, and splicing and packaging the message fragments to form a message for sending. According to the method and the device, whether the messages need to be ordered or not is judged, the messages needing to be ordered are ordered and sent, and the problem of disorder of the messages is avoided.

Description

Message disorder rearrangement method and single board

Technical Field

The present disclosure relates to the field of communications devices, and in particular, to a method and a board for message out-of-order rearrangement.

Background

The single board and the switching network process uplink or downlink messages, each single board comprises n net boards and FPGA, and the FPGA is connected with an intranet penetration proxy server (NPS for short). By way of example, a net board may be 4 (net board 0-net board 3) connected to an FPGA through four HIG links. Here, the NPS sends the message data to the switching network through the FPGA as uplink message processing. In turn, the transmission of switching network message data to the NPS through the FPGA is referred to as downstream message processing. In the above scheme, due to errors of different network board clocks and different connected HIG links, the downlink messages are different in sequence, resulting in message disorder.

Disclosure of Invention

In order to overcome the problems in the related art, the present application provides a message out-of-order rearrangement method.

According to the embodiment of the application, the method for message out-of-order rearrangement is applied to a first single board, and the method is used for receiving and combining messages sent by a second single board through a plurality of HIG links and mapping the messages to a plurality of signal channels; the method comprises the steps of slicing and storing a message, and recording a head address of the message slicing and the number of stored slicing; judging whether the message needs to be sequenced, if so, taking out the message fragments for sequencing, and splicing and packaging the message fragments into a message for sending.

Preferably, the second board receives and merges the messages sent by the connection of the plurality of HIG links, maps the messages to a plurality of signal channels, and fragments and stores the messages in the shared memory.

Further, judging whether the messages need to be sequenced or not, including judging whether the message serial number SN of the messages is in a range of SN-SN+M or not;

if the message is within the range, taking out and sequencing the stored message fragments, and then splicing and packaging the message fragments into a message for outgoing;

if the message is smaller than the SN, the message is directly sent;

wherein M represents the maximum delay time T microsecond of the message and is obtained by the inverse of 1000/the clock of the single board, and the single board is a source board or a destination board.

Preferably, the message is fragmented and stored, and the head address of the message and the number of fragments stored are recorded, including:

dividing a RAM in a shared memory into S small memory units;

the message fragments are stored in the RAM according to the addresses, and the connection address information of each message fragment is recorded through an address linked list;

unused RAM addresses and RAM addresses released after being fetched are deposited through a second FIFO of the shared memory.

Preferably, the message is sent out from one or more second single boards, and the source of the message is judged according to the received second single board codes.

Preferably, the message in the message split package and the message output at least comprises a message start tag, a message serial number SN, a message head address and a storage fragment number.

Preferably, the message of the second single board enters a multipath signal channel, the received message information is stored in the RAM by taking the message serial number SN as an address, and the valid flag bit is used for indicating that the address is valid; when a message starting label carried by a received message is detected, starting a scheduling state machine;

starting self-accumulation searching from a message serial number SN corresponding to a message starting label carried by a message, judging whether the message is a timeout message after searching for a valid message, and calling the message if the message is the timeout message; if the message is not the overtime message, judging whether the message is the sequence message, if the message is the sequence message, calling the message, and if the message is not the sequence message, not performing any operation;

after the message is called, judging whether the message is the last message, if so, stopping searching, and if not, starting the next searching from the dispatched message serial number SN.

Preferably, the first board sends a message to the second board through a plurality of HIG links, each HIG link corresponds to a first FIFO memory, the count of the first FIFO memory of the corresponding link is increased by 1 in the message passing through the first FIFO memory, one-time message sending is completed to the second board through the HIG links, the counter of the first FIFO memory of the corresponding link is reduced by 1, the count value of the first FIFO memory is finally obtained, and the count threshold of the first FIFO memory is set;

if the count values of all the first FIFO memories do not reach the set count threshold, the subsequent messages of each HIG link are sent to the second single board packet by packet;

if the count value of a certain first FIFO memory exceeds a set count threshold, sending messages to the HIG links of other several HIGs packet by packet;

if the count values of all the first FIFO memories reach the set count threshold, sending a subsequent message to the HIG link with the smallest count value of the first FIFO memory;

if all the storage addresses of a certain first FIFO memory are occupied, the subsequent messages sent to the corresponding HIG link are discarded.

The second aspect of the embodiment of the application provides a board, which comprises a logic control chip, wherein the logic control chip applies the message disorder rearrangement method.

The technical scheme provided by the embodiment of the application can comprise the following beneficial effects:

according to the method and the device, whether the messages need to be ordered or not is judged, and the messages needing to be ordered are ordered and sent, so that the problem of disorder of the messages is avoided.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments consistent with the application and together with the application serve to explain the principles of the application.

FIG. 1 is a hardware logic block diagram of an embodiment of the present application;

FIG. 2 is a schematic flow chart of an embodiment of the present application;

FIG. 3 is a functional block diagram of the FIP downstream message of FIG. 1 of the present application;

FIG. 4 is a logic block diagram of a shared memory according to an embodiment of the present application;

FIG. 5 is a schematic diagram of a RAM slice storage flow according to an embodiment of the present application;

FIG. 6 is a flow diagram of a dispatch state machine according to an embodiment of the present application.

Detailed Description

Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples are not representative of all implementations consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present application as detailed in the accompanying claims.

The terminology used in the embodiments of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to any or all possible combinations including one or more of the associated listed items.

It should be understood that although the terms first, second, third, etc. may be used in embodiments of the present application to describe various information, these information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, a first message may also be referred to as a second message, and similarly, a second message may also be referred to as a first message, without departing from the scope of the present application. Depending on the context, furthermore, the word "if" used may be interpreted as "at … …" or "at … …" or "in response to a determination".

The application provides a message out-of-order rearrangement method which is applied between a source board and a destination board. The source board can have a plurality of blocks, and is connected with the destination board in parallel for message interactive transmission. As described in the background, the NPS transmits the message data to the switching network through the logic control chip, which is called as uplink message processing. In turn, the transmission of the switching network message data to the NPS through the logic control chip is referred to as downstream message processing. The logic control chip in the present application may be an FPGA. The method is applied to the interaction process between the first single board and the second single board, as shown in fig. 3, the interaction message from the second single board to the first single board is a downlink message, and the interaction message from the first single board to the second single board is an uplink message. The method is applicable to both uplink messages and downlink messages. A logical block diagram of hardware in an embodiment of the present application is shown in fig. 1. Taking fig. 1 as an example, a brief explanation of the functions of each module will be first described. The second single board carries out message interactive transmission through four HIG links (HIG 0-HIG 3). The RSCH module is used for converging the downlink messages. The FIP module corresponds to the processing of the downlink message part and has a message ordering function. The TSCH is an information head, and information is accessed by the TSCH information head, uploaded through the first FIFO and HIG links (HIG 0-HIG 3) for uplink messages. ILKN is a comprehensive interface. The message out-of-order rearrangement method in the embodiment of the present application is described in a downlink message, as shown in a flowchart in fig. 2. The downlink message is mainly located in the FIP part of fig. 1.

0001: the second single board sends a message to the first single board.

The message at least comprises a message starting tag and a message serial number SN, wherein the message starting tag is used for marking whether the message is the starting message of the message flow. If yes, marking by the message start label. In order to avoid the time of waiting for the arrival of the message start tag, which is caused by large disorder of the message, the message can also comprise a time stamp, namely the time of locally carrying the message to be sent, and the time stamp is used in combination with the message serial number SN.

0003: the first single board receives and merges the messages sent by the second single board through a plurality of HIG links and maps the messages to a plurality of signal channels.

With reference to fig. 1 and fig. 3, the second board sends the message to the first board through multiple HIG links and performs the combination, if there are multiple second boards, because each second board has a code, the first board can easily distinguish which second board sends the message through the SMOD tag in the message when the combination is performed. Because the second boards are independent, the message flow sent by one second board is described as an example and mapped to the multipath signal channel. The multiple signal channels are connected with the data selector, and when the message passes through the multiple signal channels to the data selector, the multiple signal channels can judge which multiple signal channels transmit the message. In the embodiment of the present application, 64 CHANNELs are selected as the multiple signal CHANNELs in consideration of cost and performance, and CHANNELs 0 to 63 are selected as the multiple signal CHANNELs.

0005: and slicing and storing the received message, and recording the head address of the message slicing and the number of the stored slicing.

In the embodiment of the present application, the message is fragmented and stored in the shared memory, and the first address of the message and the number of fragments stored are recorded, as shown in fig. 5, including:

dividing a RAM in a shared memory into S small memory units;

storing the message fragments in the RAM according to the addresses, and recording the connected address information of each message fragment through a linked list;

If a message store is configured for each of the multiple signal channels, RAM resources are insufficient and a high bandwidth memory HBM is required. In order to reduce the cost, when the maximum delay time T microsecond of the message is met, the application exemplifies the case of 4 microseconds, and as long as the message is fetched from the storage within 4 microseconds, the required RAM resource size is 4×1000/2.5×2048/1024/8=400 KB. So as long as the reserved RAM is greater than 400KB, there is no need to use a high bandwidth storage HBM in a shared RAM fashion.

In the application, for example, a RAM with a size of 1MB is taken as an example, the RAM is divided into 256B small storage units, and can be divided into 4096 small storage units, when a message needs to be fragmented, the message is fragmented and stored into the RAM by taking 256B as a small fragment, and addresses of the several RAMs are taken when the message is fragmented, and the message is put into the small storage units with corresponding addresses. In order to facilitate searching when the message is taken out, the connected address information of each message fragment is recorded through an address linked list.

0007: judging whether the message needs to be sequenced, and if so, taking out the message fragments for sequencing.

Judging whether the message needs to be sequenced, the application provides an embodiment which comprises judging whether the message serial number SN of the message is in the range of SN-SN+M;

if the message is smaller than the SN, the message is directly sent;

wherein M represents the maximum delay time T microsecond of the message and is obtained by the reciprocal of 1000/single board clock,

the single board is a source board or a destination board.

In the embodiment of the present application, considering the performance and cost of the board, the maximum delay time t=4 microseconds is set, and the clock of the board is 400 megabits, and then m=4×1000/2.5=1600, so the message sequence number SN is SN to sn+1600. If the message is within the range, ordering is needed, and if the message is smaller or larger than the range, the message is directly sent.

The message may be in the following format when entering the ordering module, as in table 1:

Start

SN

Time

Link addr

Length

TABLE 1

Wherein Start is a message Start tag for determining whether the message is a message Start message to prevent disorder. If 1 is the start tag, if 0 is not the start tag.

Link addr is the head address of the current message, and Length is the number of fragments of the current message.

Time is the timestamp of the current message transmission.

And the message slicing information enters a sequencing module, and after sequencing is finished, the message is spliced into a message and is sent outwards.

When the received message start tag is 1, the received start message is indicated, and the scheduling state machine is started.

The received message information is stored in the RAM by taking the message serial number SN as an address, and the valid flag bit is used for indicating that the address is valid, as shown in the table 2.

Valid

Time

Link addr

Length

TABLE 2

Valid is used to mark whether the message is Valid, and can be set to be Valid when 1 and invalid when 0.

As shown in fig. 6, when detecting that the received message carries a message start tag, starting a scheduling state machine;

starting self-accumulation searching from a message serial number SN corresponding to a carried message starting tag, judging whether the message is a timeout message after searching for a valid message, and calling the message if the message is the timeout message; if the message is not the overtime message, judging whether the message is the sequence message, if the message is the sequence message, calling the message, and if the message is not the sequence message, not performing any operation, and starting the next search;

0009: and taking out the packet and sending out the packet in a split manner.

And taking out the package-spliced outgoing message, wherein the package-spliced outgoing message comprises the number of fragments of the message according to the first address of the message and the storage position of each message fragment of the address in the address chain table, sequentially taking out the message fragments and splicing the package, and simultaneously, putting the address released after the package splicing back to the second FIFO (first FIFO), as shown in figure 4. It should be noted here that when a new packet needs to be stored in slices, the unused or released address is fetched into the second FIFO.

When the message needs to be taken out and sent out, the message is taken out from the address chain table according to the connected address. As shown in fig. 4, a message with a head address of 0 and corresponding address 3 is fetched from the address linked list, then address 3 and corresponding address 4 are searched, if there are 3 fragments, the message fragments corresponding to addresses 0-3-4 in the RAM can be fetched and packed.

The uplink message part is as shown in fig. 1, and the information is accessed by the TSCH information head and uploaded through the HIG links (HIG 0-HIG 3) via the first FIFO. The first single board sends a message to the second single board through a plurality of HIG links, each HIG link corresponds to a first FIFO memory, as shown in figure 1, when the message passes through the first FIFO memories, the count of the first FIFO memories of the corresponding links is increased by 1, and one message sending is completed to the second single board through the HIG links, the counter of the first FIFO memories of the corresponding links is reduced by 1, and finally the count value of the first FIFO memories is obtained, and the count threshold of the first FIFO memories is set;

Therefore, the flow balance of a plurality of HIG links can be ensured, and the message delay time is short.

The embodiment of the application also provides a single board, which comprises a logic control chip, and is characterized in that the logic control chip applies the message out-of-order rearrangement method of the embodiment, as shown in fig. 1.

The logic control chip in the embodiment of the application is an FPGA chip.

Wherein the machine-readable storage medium may be any electronic, magnetic, optical, or other physical storage device that can contain or store information, such as executable instructions, data, or the like. For example, a machine-readable storage medium may be: RAM (Radom Access Memory, random access memory), volatile memory, non-volatile memory, flash memory, a storage drive (e.g., hard drive), a solid state drive, any type of storage disk (e.g., optical disk, dvd, etc.), or a similar storage medium, or a combination thereof.

The system, apparatus, module or unit set forth in the above embodiments may be implemented in particular by a computer chip or entity, or by a product having a certain function. A typical implementation device is a computer, which may be in the form of a personal computer, laptop computer, cellular telephone, camera phone, smart phone, personal digital assistant, media player, navigation device, email device, game console, tablet computer, wearable device, or a combination of any of these devices.

It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, embodiments of the present application may take the form of a computer program product on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

Moreover, these computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

The foregoing is merely exemplary of the present application and is not intended to limit the present application. Various modifications and changes may be made to the present application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc. which are within the spirit and principles of the present application are intended to be included within the scope of the claims of the present application.

It is to be understood that the present application is not limited to the precise arrangements and instrumentalities shown in the drawings, which have been described above, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the application is limited only by the appended claims.

The foregoing description of the preferred embodiment of the present invention is not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

Claims

1. The message disorder rearrangement method is applied to a first single board and is characterized in that messages sent by a second single board through a plurality of HIG links are received, combined and mapped to a plurality of signal channels; the message is segmented and stored, and the head address of the message segmentation and the number of stored segments are recorded; judging whether the message is required to be sequenced, if so, taking out the message fragments for sequencing, and splicing and packaging the message fragments to form a message for sending.

2. The method according to claim 1, wherein the second board receives and merges the messages sent by the second board through the plurality of HIG links, maps the messages to multiple signal channels, and fragments and stores the messages in the shared memory.

3. The method of claim 2, wherein determining whether the messages need to be ordered includes determining whether a message sequence number SN of the messages is in a range of SN to sn+m, where M represents a maximum delay time T microseconds of the messages, 1000, and a reciprocal of a board clock, and the board is a source board or a destination board.

4. The method for message out-of-order rearrangement according to claim 3, wherein the fragmenting and storing the message, recording the head address and the number of stored fragments of the message, comprises:

dividing a RAM in a shared memory into S small memory units;

the message fragments are stored in the RAM according to addresses, and the connected address information of each message fragment is recorded through an address linked list;

and storing unused RAM addresses and RAM addresses released after being fetched through a second FIFO of the shared memory.

5. The method of claim 2, wherein the message is sent from one or more second boards, and the message source is determined based on the received second board code.

6. The method according to claim 5, wherein the messages in the packet-forming and outgoing include at least a message start tag, a message sequence number SN, a header address of the message, and a number of stored fragments.

7. The method of claim 6, wherein,

the message of the second single board enters a multipath signal channel, the received message information is stored in a RAM by taking a message serial number SN as an address, and valid flag bits are used for indicating that the address is valid; when a message starting label carried by a received message is detected, starting a scheduling state machine;

8. The method of claim 7, wherein the first board sends a message to the second board through a plurality of HIG links, each HIG link corresponds to a first FIFO memory, when the message passes through the first FIFO memory, the count of the first FIFO memory of the corresponding link is increased by 1, and the message is sent to the second board once through the HIG link, the counter of the first FIFO memory of the corresponding link is decreased by 1, and finally the count value of the first FIFO memory is obtained, and the count threshold of the first FIFO memory is set;

9. The single board comprises a logic control chip, and is characterized in that the logic control chip applies the message disorder rearrangement method according to any one of the claims 1-8.