CN113689899B - Memory array circuit structure and large-scale memory array circuit structure - Google Patents
Memory array circuit structure and large-scale memory array circuit structure Download PDFInfo
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- CN113689899B CN113689899B CN202110997344.4A CN202110997344A CN113689899B CN 113689899 B CN113689899 B CN 113689899B CN 202110997344 A CN202110997344 A CN 202110997344A CN 113689899 B CN113689899 B CN 113689899B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
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- G—PHYSICS
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- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
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- G—PHYSICS
- G11—INFORMATION STORAGE
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- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
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- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/18—Bit line organisation; Bit line lay-out
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- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/10—Decoders
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- G—PHYSICS
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- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
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Abstract
The invention relates to a memory array circuit structure and a large-scale memory array circuit structure, wherein the memory array is divided into an upper memory array and a lower memory array, and meanwhile, the end parts of the memory array are respectively connected with a sense amplifier, a read-write driving module and a column address decoding circuit, the memory units of the upper memory array are read out by the upper sense amplifier, and the lower memory array is read out by the lower sense amplifier, so that the number of stages of block design is reduced, the introduction of redundant peripheral circuits is avoided, the layout area of a memory is further reduced, the layout density is increased, and the improvement of the access speed of a static memory and the reduction of power consumption are realized. Compared with the structure of the traditional block design, the invention reduces the discharge amplitude of the bit line and then the load, reduces the worst path delay and the power consumption of the memory, and achieves the purpose of improving the reading speed of the whole memory; finally, the method provided by the invention is suitable for circuit architecture design of various memories, and has good application prospect and economic benefit.
Description
Technical Field
The invention belongs to the technical direction of microelectronics, and relates to the field of high-speed low-power-consumption data storage, in particular to a memory array circuit structure and a large-scale memory array circuit structure.
Background
With the development of high-speed low-power consumption requirements and manufacturing technologies of memory designs, it is difficult for the existing memories to meet the market index requirements of integrated circuits.
Various methods are currently being explored to achieve a balance between speed and power consumption, including the development of memory cells, the development of timing control modules, and the like. The memory comprises a memory cell array module, a row-column decoder module, a sense amplifier, a read-write driving module, a timing control circuit and an output circuit. The memory array is divided into four blocks, namely an upper block, a lower block, a left block and a right block, wherein each upper block and each lower block share a column decoding circuit, a sense amplifier and a write driving circuit, and the middle of the whole memory is provided with a row decoding address circuit and a time sequence control module circuit. The address signals of the memory are divided into row addresses and column addresses, when the row decoder receives the row address signals, a word line is selected to trigger a row of the memory array, and the column decoder receives the column address signals, a required word circuit schematic diagram can be found in the selected row, as shown in fig. 2.
However, as the memory capacity increases, the area of the decoder and memory array increases accordingly, as does the length of the bit lines and the corresponding load capacitance on the bit lines. When the row-column decoder selects the memory address to be accessed and performs read-write operation, the memory cells closer to the sense amplifier and the memory cells farther from the sense amplifier have great difference in reading speed, the path for accessing the memory cells closer to the sense amplifier is shorter, the shortest path is 1 memory cell, the path for accessing the memory cells farther is longer, for example, a memory array has 2m rows and 2n columns, the path is up to 2m/2 memory cells at the maximum, the metal line capacitance and the memory cell load capacitance on the bit line are heavier, and the access time is longer. The access time of the memory can only be the same as the access time of the memory address at the farthest distance, and the data readout of the memory cell at the farther distance will be an important cause for affecting the memory read speed. Meanwhile, due to the influence of the access speed, the voltage drop on the bit line is also large, so that the power consumption of the memory is increased, and the read-write time and the power consumption of the memory are greatly influenced by the too long bit line of the word line.
In order to solve this problem, in the structural design of the large-capacity memory, a method of multi-level block design may be adopted, so as to reduce delay under the worst path, improve SRAM speed and reduce power consumption, as shown in fig. 3, the memory is divided into P small blocks, each small block has the same composition architecture as that of fig. 2, each block has a memory array, a local row decoding and a column decoding, the selection of the memory unit is also based on the row address and the column address corresponding to each block, and in addition, a block address is mainly responsible for selecting a block to be read and written from among the P small blocks. Through the hierarchical word line structure and the multi-path selection bit line technology, after each address is valid, the block address is firstly decoded, 1 block in the P small blocks is selected to perform read-write operation, and then the read-write operation described in fig. 2 is performed. Therefore, when the circuit works, only the individual blocks are selected, and the row and column decoding and the sense amplifier in the unselected blocks do not work, so that the circuit has the advantage that the power consumption is not greatly influenced; the disadvantage is that if it is necessary to ensure that the lengths of the word lines and bit lines in the selected blocks remain within certain limits, more levels of classification are required, not only in the lateral direction, but also in the longitudinal direction, so that a series of problems caused by excessive bit line loading are avoided, and more decoding circuits and control circuits are required, namely, the area is sacrificed to achieve the balance of speed and power consumption.
Disclosure of Invention
Aiming at the problems of high power consumption and long conduction time of a memory array circuit structure in the prior art, the invention provides the memory array circuit structure.
The invention is realized by the following technical scheme:
the memory array circuit structure is characterized by comprising an upper memory array and a lower memory array;
the two ends of the upper memory array and the lower memory array, which are relatively far away, are respectively provided with a sense amplifier, a read-write driving module and a column address decoding circuit in sequence, and the sense amplifier, the read-write driving module and the column address decoding circuit are used for respectively meeting the signal SA logic operation of the upper memory array and the lower memory array, and the read-write driving module is connected with a data unit;
and the same sides of the upper memory array and the lower memory array are respectively connected with a row address decoding circuit.
Further, the row address decoding circuit is used for decoding the input row address signals and selecting an upper memory array or a lower memory array for input.
Further, intersections of bit lines and word lines of the upper memory array and the lower memory array respectively form memory cells.
Further, the upper and lower memory arrays have an array height equal to their respective bit line lengths.
Further, the row address decoding circuit includes a high-order address signal of a one-order address signal.
Further, the one-bit address signal is connected with sense amplifiers at both sides of the upper memory array or the lower memory array through an inverter.
The rapid reading circuit structure of the large memory array is characterized by comprising a plurality of memory array circuit structures;
the plurality of memory array quick reading circuit structures are connected through a hierarchical word line structure and a multi-path selection bit line technology.
Further, the system also comprises a preselected reading operation module, a time sequence control module, an X address buffer, a Y address buffer and an IO buffer;
the output end of the X address buffer is respectively connected with a time sequence control module and a pre-decoding circuit of a pre-selection reading operation module;
the input end of the Y address buffer is connected with a column address decoding circuit of the preselected reading operation module, and the output end of the Y address buffer is connected with the time sequence control module;
the output end of the time sequence control module is connected with a sensitive amplifier of the preselection reading operation module;
the IO buffer is connected with all the sense amplifiers in a bidirectional mode.
Compared with the prior art, the invention has the following beneficial technical effects:
the invention relates to a memory array circuit structure, which is divided into an upper memory array and a lower memory array, wherein the end parts of the upper memory array are respectively connected with a sense amplifier, a read-write driving module and a column address decoding circuit, the memory units of the upper memory array are read out by the upper sense amplifier, and the lower memory array is read out by the lower sense amplifier, so that the number of stages of block design is reduced, the introduction of redundant peripheral circuits is avoided, the layout area of a memory is further reduced, and the layout density is increased; the row decoding address circuit has one-bit address signal to divide the memory array into an upper memory array and a lower memory array, so that the length of a bit line can be shortened, the load capacitance of the bit line can be reduced, and the improvement of the access speed of the static memory and the reduction of the power consumption can be realized. Compared with the structure of the traditional block design, the invention reduces the discharge amplitude of the bit line, reduces the worst path delay and the power consumption of the memory, and achieves the purpose of improving the reading speed of the whole memory; finally, the method provided by the invention is suitable for circuit architecture design of various memories, and has good application prospect and economic benefit.
Furthermore, the one-bit address signal selects the high-bit address signal in the row decoding address, so that the continuity of the low-bit address can be ensured, and the load of the memory array circuit can be reduced.
Furthermore, the one-bit address signal is an address signal of an upper memory array and a lower memory array selected in a row decoding address circuit, so that the upper and lower division can be realized, the address and an enable signal SA of a sense amplifier are subjected to logic operation, namely NAND operation and NOR operation, and meanwhile batch processing of signals by the upper memory array and the lower memory array can be met, the overall operation efficiency is improved, and the operation energy consumption is reduced.
According to the large-scale memory array circuit structure, the plurality of memory array quick reading circuit structures are connected through the hierarchical word line structure and the multi-path selection bit line technology, so that faster operation and lower operation energy consumption can be achieved.
Drawings
FIG. 1 is a schematic diagram of a conventional memory circuit architecture;
FIG. 2 is a schematic diagram of a conventional memory circuit;
FIG. 3 is a schematic diagram of a conventional ultra-large capacity memory multi-level block design circuit;
FIG. 4 is a schematic diagram of a memory array circuit according to an embodiment of the invention;
FIG. 5 is a 1Mbit memory circuit in an embodiment of the invention.
In the figure: an upper memory array 1, a lower memory array 2, a sense amplifier 3, a read-write driving module 4, a column address decoding circuit 5, a data unit 6, a row address decoding circuit 7, an address signal 8 and a memory unit 9.
Detailed Description
The invention will now be described in further detail with reference to specific examples, which are intended to illustrate, but not to limit, the invention.
The invention relates to a memory array circuit structure, as shown in figure 4, which specifically comprises an upper memory array 1 and a lower memory array 2 through the optimization design of the whole structure of the existing static memory;
the two ends of the upper memory array 1 and the lower memory array 2 which are relatively far away are respectively provided with a sense amplifier 3, a read-write driving module 4 and a column address decoding circuit 5 in sequence, and the sense amplifier is used for respectively meeting the signal SA logic operation of the upper memory array 1 and the lower memory array 2;
the read-write driving module 4 is connected with a data unit 6; the row address decoding circuits 7 are respectively connected to the same sides of the upper memory array 1 and the lower memory array 2, so that the design can reduce the number of stages of the block design, avoid introducing redundant peripheral circuits, further reduce the layout area of the memory and increase the layout density;
further, the row address decoding circuit 7 is configured to decode an input row address signal, and select the upper memory array 1 or the lower memory array 2 to input the signal, thereby realizing signal storage.
Further, the intersections of the bit lines and the word lines of the upper memory array 1 and the lower memory array 2 respectively form memory cells 9; meanwhile, the array heights of the upper memory array 1 and the lower memory array 2 are equal to the respective bit line lengths, so that compared with the traditional memory array circuit structure, the bit line length can be shortened, the bit line load capacitance can be reduced, and the improvement of the access speed and the reduction of the power consumption of the static memory can be realized.
In a preferred embodiment of the present invention, the one-bit address signal 8 is a high-bit address signal 8 in a row decoding address, so that continuity of a low-bit address can be ensured, and the load of a memory array circuit is reduced;
furthermore, the one-bit address signal 8 is connected with the sense amplifiers 3 at two sides of the upper memory array 1 or the lower memory array 2 through an inverter, specifically, the one-bit address signal 8 is an address signal of the upper memory array 1 and the lower memory array 2 selected in the row decoding address circuit 7, so that the up-down division can be realized, the logical operation, that is, the NAND operation and the NOR operation, can be performed on the address and the enabling signal SA of the sense amplifiers 3, and meanwhile, batch processing of signals by the upper memory array 1 and the lower memory array 2 can be satisfied, the overall operation efficiency is improved, and the operation energy consumption is reduced.
Further, in a preferred embodiment, the one-bit address signal 8 selects the sense amplifier 3 on one side of the following memory array 2, and the judging and selecting processes are as follows: if the one-bit address signal 8 is 1, the one-bit address signal is output to the upper memory array 1, if the one-bit address signal 8 is 0, the one-bit address signal is output to the sense amplifier 3 at one side of the lower memory array 2, and specifically, the one-bit address signal is read by the column address decoding circuit 5 and the sense amplifier 3 at the lower end of the memory array.
The invention relates to a quick reading circuit structure of a large memory array, which comprises a plurality of memory array circuit structures;
the plurality of memory array quick reading circuit structures are connected through a hierarchical word line structure and a multi-path selection bit line technology.
Specifically, the rapid reading circuit structure of the large storage array further comprises a preselected reading operation module, a time sequence control module, an X address buffer, a Y address buffer and an IO buffer;
the output end of the X address buffer is respectively connected with a time sequence control module and a pre-decoding circuit of a pre-selection reading operation module;
the input end of the Y address buffer is connected with a column address decoding circuit 5 of the preselected reading operation module, and the output end of the Y address buffer is connected with the time sequence control module;
the output end of the time sequence control module is connected with a sensitive amplifier 3 of the preselection reading operation module;
the IO buffer is bi-directionally connected with all sense amplifiers 3.
Another preferred embodiment of the present invention is a 1Mbit memory circuit comprising a memory array circuit structure of the present invention as shown in fig. 5,
the memory array is divided into 4 memory cell arrays, the capacity of each memory cell array is 256Kbit, each memory cell array comprises 512 rows and 512 columns, circuits consisting of a column address decoding circuit 5, a sense amplifier 3 and a read-write driving module 4 are arranged on the upper side and the lower side of each memory cell array module, when addresses are effective, block selection is performed by a one-bit address to determine a block which specifically works in the four memory cell arrays, then upper bit line selection and lower bit line selection are performed in the selected block by a one-bit address signal 8, if the selected bit line is the upper bit line, data is read through the upper sense amplifier 3, otherwise, the data is read through the lower sense amplifier 3, and then the data is transmitted to an IO end.
If the conventional design architecture is used, there are 512 word lines and 512 bit lines in each memory array module, i.e., 512 memory cells on each bit line. If the physical size of one memory cell in the layout design is W (word line direction) x L (bit line direction). The load length of one bit line is 512L, if the load resistance is R and the load capacitance is C.
By adopting the architecture design circuit in the invention, the memory array is subjected to bit line design, so that the number of units on one bit line is halved, namely, only 256 memory units are arranged on one bit line, the load length is reduced to 256L, which is 1/2 of the original load, and because the load resistance and the load capacitance are both in direct proportion to the length of the load line, the load resistance is R1=R/2, and the load capacitance is C1=C/2. When the memory performs a read operation, one of the two bit lines discharges and the other bit line maintains a precharge value VDD, when the voltage V (t) on the discharged bit line decreases from VDD to 80% VDD, the following formula is satisfied according to the inherent response of the RC circuit:
v(t)＝V0×e^ (-t/RC) (where V0 is the supply voltage VDD).
From which it can be deduced
From the above formula, it can be calculated that when the load resistance R and the load capacitance C are reduced to 1/2 of the original values, the time t required for the voltage to be reduced to the same magnitude can be reduced to 1/4 of the original values.
Therefore, compared with the common architecture, the circuit structure can shorten the length of the bit line to half of the original length, reduce the load of the bit line to half of the original load, quicken the data access speed of the memory, and reduce the discharge amplitude of the bit line, thereby reducing the power consumption; compared with a multi-stage block circuit architecture, the area is saved.
Claims (6)
1. The quick reading circuit structure of the large-scale memory array is characterized by comprising a plurality of memory array circuit structures, wherein the memory array circuit structures are connected through a hierarchical word line structure and a multi-path selection bit line technology;
the system also comprises a preselected reading operation module, a time sequence control module, an X address buffer, a Y address buffer and an IO buffer;
the output end of the X address buffer is respectively connected with a time sequence control module and a pre-decoding circuit of a pre-selection reading operation module;
the input end of the Y address buffer is connected with a column address decoding circuit (5) of the preselected reading operation module, and the output end of the Y address buffer is connected with the time sequence control module;
the output end of the time sequence control module is connected with a sensitive amplifier (3) of the preselection reading operation module;
the IO buffer is connected with all the sensitive amplifiers (3) in a bidirectional way;
the memory array circuit structure comprises an upper memory array (1) and a lower memory array (2);
the two ends of the upper storage array (1) and the lower storage array (2) which are relatively far away are respectively provided with a sensitive amplifier (3), a read-write driving module (4) and a column address decoding circuit (5) in sequence, and the sensitive amplifier is used for respectively meeting the signal SA logic operation of the upper storage array (1) and the lower storage array (2), and the read-write driving module (4) is connected with a data unit (6);
the same sides of the upper storage array (1) and the lower storage array (2) are respectively connected with a row address decoding circuit (7).
2. A fast read circuit structure for a large memory array according to claim 1, wherein the row address decoding circuit (7) is configured to decode an input row address signal and select an upper memory array (1) or a lower memory array (2) for input.
3. The rapid reading circuit structure of a large memory array according to claim 1, wherein the intersections of bit lines and word lines of the upper memory array (1) and the lower memory array (2) respectively form memory cells (9).
4. A large memory array fast read circuit arrangement according to claim 1, wherein the array height of the upper memory array (1) and the lower memory array (2) is equal to their respective bit line lengths.
5. A fast read circuit arrangement for a large memory array according to claim 1, characterized in that the row address decoding circuit (7) comprises a high-order address signal of a one-order address signal (8).
6. The fast read circuit structure of a large memory array according to claim 5, wherein the one-bit address signal (8) is connected to sense amplifiers (3) on both sides of the upper memory array (1) or the lower memory array (2) through inverters.
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