CN113684133B - Neuron NOT gate logic function chip integrating micro-fluidic and microelectrode arrays and preparation method thereof - Google Patents
Neuron NOT gate logic function chip integrating micro-fluidic and microelectrode arrays and preparation method thereof Download PDFInfo
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Abstract
The invention discloses a neuron NOT logic function chip integrating micro-fluidic and microelectrode arrays and a preparation method thereof, and relates to a sensor technology and an electric stimulation regulation technology. The chip system is composed of two layers of sub-chips, and the two sub-chips are manufactured by MEMS technology. The first layer of sub-chip is a microelectrode array chip for detecting the electrophysiological regulation and control of the neuron and comprises a detection microelectrode array, a stimulation electrode and other elements; the second layer of sub-chip is a micro-fluidic chip for directional culture of neurons and comprises a cell culture tank, a micro-channel and a micro-channel. The chip realizes directional interconnection among neurons by using the micro-channel, trains the neurons at the input end through the stimulating electrode to change the discharge of the neurons at the input end, thereby realizing the control of the discharge frequency of the neurons at the output end by the neurons at the input end of the micro-channel, and further constructing a one-to-one control unit with a certain logic function on the neuron layer. The chip has integrated functions, and has the functions of directionally culturing neurons and the capability of air-conditioning control and detection.
Description
Technical Field
The invention relates to the micro-electromechanical system (MEMS) micromachining field, the electric stimulation regulation field and the nerve cell compartmentalization culture field of a biosensor, in particular to a neuron NOT logic function chip integrating micro-flow control and microelectrode arrays and a preparation method thereof.
Background
Humans have the most complex, precise material structures in the world-the brain with thinking ability. Through the daily operation of the brain, people can easily complete advanced and complex work which is difficult to be completed by the artificial intelligence at present. The mystery for revealing the advanced brain function is not only one of the top puzzles of natural science, but also a great challenge facing the current neuroscience, and is also a great obstacle for breaking through the current artificial intelligence development.
All high-level functions of the brain are implemented independently of the transfer, processing and storage of information. The brain has a variety of advanced functions such as perception, consciousness, behavior, memory, learning, etc. The brain has such complex functions because there are billions of nerves in the brain, and these neurons form a complicated neural network through synaptic connection, and different neural networks are mutually staggered and connected, so that a human brain with stronger processing capacity than that of a modern computer is formed. Whether it is a simple knee-jump response or a complex memory capacity of humans, it is closely related to the information transfer of different brain areas in the brain, whereas the information transfer of neural networks in the brain is accomplished by nerve cell pulse discharges and neurotransmitter transfer.
Microelectrode arrays (MEAs) serve as interface tools between neural networks and electronic systems, helping scientists to understand the dynamics of neural networks and their responses to biological substances in depth, and further providing possibilities for scientists to reveal the function of neural networks. The micro-fluidic technology is widely used for customizing in-vitro culture specific neural networks due to the characteristics of precise control, micro-scale control and the like. By combining microelectrode array technology with microfluidic technology, it becomes possible to develop advanced functions of neural networks in vitro.
Many studies have shown that external electrical stimulation can stimulate the learning, memory, etc. functions of the neuronal network. The function of the neural network can be better developed in vitro by external electrical stimulation.
Disclosure of Invention
The invention aims to provide a neuron NOT gate logic function chip integrating micro-flow control and microelectrode arrays and a preparation method thereof. The chip realizes that two neuron networks form a plurality of groups of one-to-one neuron interconnection in a designed microchannel through integrating the microelectrode array and the microfluidic chip. And the electric stimulation technology is used for carrying out electric stimulation on the input end of the micro-channel to influence the discharge condition of the neuron at the input end, and as the neurons at the two ends generate synaptic connection in the micro-channel, the signals of the neuron at the input end can be transmitted to the neuron at the output end, and the neuron at the output end generates different corresponding signals along with the different transmitted information. Therefore, we construct a control unit with a certain logic function on the neuron level, and by changing the electrical stimulation parameters and culturing the cell types, we can make the control unit have the function similar to an electronic NOT logic device in vitro. The invention makes it possible to develop the high-level functions of the nerve cell network in vitro, so as to promote the research work of the high-level functions of the brain in vitro development and the like.
In order to achieve the purpose, the invention adopts the following technical scheme:
a neuronal not gate logic function chip integrating a microfluidic, microelectrode array, the chip comprising two layers, a first layer microelectrode array chip comprising: the device comprises an insulating substrate, a detection electrode array, a stimulation electrode, a counter electrode, an electrode lead, a contact and a surface insulating layer; the second layer microfluidic chip includes: a cell culture tank, a microchannel, and a set of microchannels for controlling the directional growth of neurons. And the microelectrode array chip and the microfluidic chip are packaged by ionic bonding. The number of cell culture tanks was 4.
The insulating substrate is a carrier of the whole microelectrode array chip; the detection electrode arrays are respectively arranged in three groups and are respectively positioned at the input end, the output end and the center of the micro-channel; the stimulating electrode is positioned around the input end detecting electrode; counter electrodes are arranged around the detection electrode array; the counter electrode, the stimulating electrode and the detecting electrode array are all extended through leads and connected to contacts at the periphery of the insulating substrate; all lead surfaces are covered with an insulating layer. The cell culture tank in the microfluidic chip is used for culturing cells; the micro-channel is connected with the cell culture tank and the micro-channel; the microchannels restrict the passage of the cell bodies of nerve cells and guide the directional growth of axons. The microelectrode array chip and the microfluidic chip are fixedly packaged in a bonding mode, so that a novel chip capable of guiding nerve cells to grow directionally and realizing a certain logic function is formed.
The neuron NOT gate logic function chip integrating the micro-fluidic and microelectrode arrays is characterized in that the insulating substrate is made of one of quartz glass, polyvinyl chloride or polycarbonate; the side length of the insulating substrate is 20-50mm, and the thickness is 1-5mm.
The neuron NOT gate logic function chip integrating the micro-fluidic and microelectrode array comprises 45-108 circular microelectrodes, wherein the diameter of each microelectrode is 10-30 mu m, and the distance between the microelectrodes is 100-500 mu m, so that the detection electrode array can be used for nerve electrophysiological signals; the microelectrode array chip is provided with 15-36 pairs of arc-shaped stimulating electrodes which are wound on the detecting electrode at the input end and can be used for electrically stimulating cells to realize excitation or inhibition of neuron discharge.
The neuron NOT gate logic function chip integrating the micro-fluidic and micro-electrode array is characterized in that the number of the counter electrodes is 2-4, and the counter electrodes are used for providing reference potential and keeping potential stability.
The neuron NOT gate logic function chip integrating the micro-fluidic and microelectrode array is characterized in that the conductive film material selected by the microelectrode array chip is one of gold, platinum, titanium nitride or indium tin oxide; the insulating layer is made of organic or inorganic insulating material with good biocompatibility, and is one of silicon dioxide, silicon nitride, silicon oxynitride, SU8, polyimide or parylene.
The method for preparing the neuron NOT logic function chip integrated with the microfluidic and microelectrode array, which is any one of the above, comprises the following steps: preparing a first layer of microelectrode array chip and preparing a second layer of microfluidic chip; a method of preparing a first layer microelectrode array chip comprising the steps of:
1) Spin-coating a layer of photoresist on the cleaned insulating substrate, wherein the thickness of the photoresist is more than three times that of the conductive film to be sputtered, and forming patterns of a detection electrode array, a stimulation electrode, a counter electrode, a lead wire and a contact after photoetching and developing;
2) Sputtering a conductive film with the thickness of 250-500 nm on the surface of the photoresist pattern, optionally sputtering a Cr or Ti seed layer with the thickness of 10-50 nm in advance before sputtering a conductive film with the thickness of 250-500 nm on the surface of the photoresist pattern so as to increase the adhesiveness between the conductive film layer and a substrate;
3) Removing the redundant film layer by adopting a stripping process, and leaving the required electrode, lead and contact;
4) Covering an insulating layer on the surface of an insulating substrate with a prepared conductive film layer by a method of Plasma Enhanced Chemical Vapor Deposition (PECVD) silicon oxide and/or silicon nitride or spin-coating SU8, polyimide and parylene, exposing a detection electrode array, an electric stimulation electrode, a counter electrode and a contact by a photoetching or plasma beam etching method, and reserving all insulating layers covered on the surfaces of leads;
5) Preparing a platinum metal film layer with the thickness of 200-500nm on the surface of the counter electrode by adopting photoetching, sputtering and stripping processes, and omitting the step if platinum is selected as the microelectrode conductive film in the step 2);
6) By electrochemical deposition or physical dripping and adsorption, nano gold particles, nano platinum black, carbon nano tubes and other nano materials are modified on the surface of microelectrodes with different functions.
The neuron NOT gate logic function chip integrating the micro-fluidic and microelectrode arrays is characterized in that the second layer of micro-fluidic chip is prepared by pouring PDMS (polydimethylsiloxane) or PMMA (polymethyl methacrylate) into a master mold made of SU8 photoresist.
The method for preparing the second layer of micro-fluidic chip comprises the following steps:
1) Master mold manufacturing
A. Spin-coating photoresist on the cleaned silicon wafer, wherein the thickness is 5-10 mu m, the length is 400-900 mu m, and a micro-channel for directional growth of cells is exposed after photoetching development;
B. spin-coating photoresist on the silicon wafer after the previous process, wherein the thickness is 50-100 mu m, and exposing a micro-channel for nerve cell growth and flow after photoetching and development;
2) Fabrication of microfluidic devices
C. Mixing PDMS prepolymer and catalyst for 5-10 min, and pouring the mixture into a master mold;
D. removing bubbles remaining around the pattern in the master mold;
E. curing PDMS;
F. and separating the microfluidic device from the master model, and manufacturing a cell culture groove in the microfluidic device by using a puncher.
The preparation method of the neuron NOT logic function chip integrating the micro-fluidic and microelectrode arrays further comprises the following steps: and packaging the prepared microelectrode array chip and the prepared microfluidic chip through ionic bonding.
The neuron NOT gate logic function chip integrating the micro-fluidic and microelectrode arrays can stimulate the neurons at one end of the micro-channel through the electric stimulation electrode group, so that the neurons at the other end generate corresponding electrophysiological signals corresponding to the neurons at the other end.
The neuron NOT gate logic function chip integrating the micro-fluidic and microelectrode array has two types of excitatory stimulation and inhibitory stimulation, wherein the excitatory stimulation adopts low-frequency bipolar pulse waves with the frequency lower than 5Hz and the amplitude lower than 0.2V, and the inhibitory stimulation adopts high-frequency bipolar pulse waves with the frequency between 20 and 100Hz and the amplitude lower than 0.2V.
The neuron NOT gate logic function chip integrated with the micro-fluidic and microelectrode arrays cultures excitatory neurons at the input end of the micro-channel and inhibitory neurons at the output end of the micro-channel. Applying excitatory electrical stimulation to the input end, and receiving inhibitory signals of the upper-level electrical signal excitation neurons by the output end inhibitory neurons; similarly, the application of inhibitory electrical stimulation at the input produces an excitatory signal at the output. We treat excitatory electrical stimulation as "1" and inhibitory electrical stimulation as "0"; excitatory output is considered "1" and inhibitory output is considered "0". Thus we construct a NOT-like base unit on neurons.
The invention aims to provide a neuron NOT gate logic function chip integrating micro-flow control and micro-electrode array and a preparation method thereof, which are used for realizing that two different neuron networks form a plurality of groups of one-to-one neuron interconnection in a designed micro-channel through integrating the micro-electrode array and the micro-flow control chip, and stimulating one end of the neuron network by using an electric stimulation technology, so that the other end generates NOT gate-like output along with input. Compared with the existing isolated cell electrophysiological detection chip, the chip has the advantages of controllability, accuracy, high flux, convenience in use and the like, and can realize the preliminary development of the advanced functions of the neural network.
Drawings
FIG. 1 is a schematic diagram of a neuronal NOT logic functional chip architecture incorporating a microfluidic, microelectrode array;
FIG. 2 is a schematic diagram of a first layer chip microelectrode array portion of the present invention;
FIG. 3 is a schematic structural diagram of a portion of a second layer chip microfluidic chip according to the present invention;
FIG. 4 is a flow chart of a process for fabricating a microelectrode array chip according to the present invention;
FIG. 4a is a schematic illustration of spin-coating a photoresist on a glass substrate surface and exposing the photoresist to light;
FIG. 4b shows a sputter mask formed by developing a photoresist;
FIG. 4c is a sputtered Cr/Pt conductive film layer;
FIG. 4d illustrates the formation of conductive layer patterns using a lift-off process leaving the desired microelectrodes, leads and contacts;
FIG. 4e is a PECVD deposition of a SiO2 (300 nm)/Si 3N4 (500 nm) insulating layer
FIG. 4f is a schematic view of exposing the microelectrode and the insulating layer over the contact again using a photolithographic process;
FIG. 4g is a schematic diagram of selective removal of the insulating layer over the microelectrodes and contacts by CHF3 Reactive Ion Etching (RIE);
FIG. 5 is a flow chart of a portion of the fabrication process of the microfluidic device of the present invention;
FIG. 5a is a spin-on SU85 photoresist on a clean silicon wafer and exposing;
fig. 5b is a development of the SU85 photoresist after exposure;
FIG. 5c is a schematic illustration of spin-coating a SU850 photoresist on a wafer after a first photolithography and exposing the wafer to light;
FIG. 5d is a development of the exposed SU850 photoresist;
FIG. 5e is a mold with PDMS poured into the master mold;
FIG. 5f is a schematic illustration of the peeling of the PDMS microfluidic device from the master mold;
fig. 6 is a schematic diagram of a two-stage neuron implementation not gate logic function.
Reference numerals illustrate:
a-microelectrode array chip and b-microfluidic chip;
a 1-insulating substrate, a 2-detecting electrode array, a 3-stimulating electrode, a 4-counter electrode, a 5-lead, a 6-contact and a 7-insulating layer;
8-cell culture tank, 9-microchannel and 10-microchannel.
Detailed Description
The technical scheme of the invention is further described below with reference to the accompanying drawings and specific embodiments. The following examples do not constitute a limitation of the present invention.
Fig. 1 shows a neuronal NOT logic function chip integrated with a microfluidic, microelectrode array according to the present invention. The chip comprises a microelectrode array chip a and a microfluidic chip b which are formed by two layers of chips;
fig. 2 shows a microelectrode array chip of the present invention, which is composed of an insulating substrate 1, a detection electrode array 2, a stimulation electrode 3, a counter electrode 4, a lead 5, a contact 6 and an insulating layer 7.
FIG. 3 shows the portion of the microfluidic device of the present invention, which is composed of a cell culture tank 8, a microchannel 9 and a microchannel 10.
As shown in fig. 1-3, a neuron not gate logic function chip integrated with a microfluidic, microelectrode array, the chip comprising two layers, a first layer microelectrode array chip a comprising: an insulating substrate 1, a detection electrode array 2, a stimulation electrode 3, a counter electrode 4, an electrode lead 5, a contact 6 and a surface insulating layer 7; the second layer microfluidic chip b includes: 4 cell culture chambers 8, a microchannel 9, and a set of microchannels 10 for controlling the directional growth of neurons. And the microelectrode array chip a and the microfluidic chip b are packaged through ionic bonding. The conductive film material selected for the microelectrode array chip a is one of gold, platinum, titanium nitride or indium tin oxide. The insulating layer 7 is made of organic or inorganic insulating material with good biocompatibility, and is one of silicon dioxide, silicon nitride, silicon oxynitride, SU8, polyimide or parylene.
The insulating substrate 1 is a carrier of the whole chip, the substrate is made of quartz glass, the length multiplied by the width of the insulating substrate is 50mm multiplied by 50mm, and the thickness is about 1mm.
The neuron NOT gate logic function chip of the integrated micro-fluidic and microelectrode array comprises detection electrode sites of a microelectrode array part which are unfolded and distributed along the center of a substrate; the detection electrodes are 3 groups, are respectively positioned at the input end, the output end and the center of the micro-channel 10, 15 detection electrodes are respectively positioned in each group, the diameter of each detection electrode is 10 mu m, the distance between the detection electrodes is 200 mu m, and the detection electrodes can be used for nerve electrophysiological signals; the stimulating electrodes surround the input end and are arranged around a group of detecting electrodes, and the interval between the stimulating electrodes is 200 mu m. The stimulating electrodes 3 in the stimulating electrode group are formed by 15 pairs of arcs, and the stimulating electrodes are encircling the detecting electrodes at the input end and can be used for electrically stimulating cells to realize excitation or inhibition of neuron discharge. A pair of counter electrodes 4 are provided around the detection electrode array 2 for providing a reference potential and maintaining the potential stable. The counter electrode 4, the stimulating electrode 3 and the detecting electrode array 2 are all extended through leads 5 and connected to contacts 6 at the periphery of the insulating substrate; all the leads 5 are covered on the surface with an insulating layer 7.
4 cell culture tanks 8 in the microfluidic chip b are used for culturing cells; the micro-channel 9 connects the cell culture tank 8 and the micro-channel 10; the microchannels 10 restrict the passage of the cell bodies of nerve cells and guide the directional growth of axons. The microelectrode array chip a and the microfluidic chip b are fixedly packaged in a bonding mode, so that a novel chip capable of guiding nerve cells to grow directionally and realizing a certain logic function is formed.
The preparation method of the first layer microelectrode array part of the neuron NOT gate logic function chip integrating the microfluidic and microelectrode arrays comprises the following steps (as shown in figure 4):
a) Cleaning the glass sheet for 10-20 minutes by using boiled concentrated sulfuric acid solution, and removing residual organic impurities or inorganic impurities on the substrate by using strong oxidizing property of the glass sheet;
b) Spin-coating a layer of photoresist on the cleaned glass sheet, wherein the thickness of the photoresist is more than three times that of a conductive film to be sputtered, and patterning a detection electrode, an electric stimulation electrode, a counter electrode, a lead wire and a contact by adopting a photoetching process (positive photoresist AZ 1500);
c) Sputtering a 50nm Cr seed layer on the surface of the photoresist pattern to increase the adhesiveness between the conductive film layer and the substrate, and sputtering a 250nm Pt layer;
d) Removing the redundant Pt layer by adopting a stripping process, and leaving a required detection electrode, an electric stimulation electrode, a counter electrode, a lead and a contact;
e) Deposition of SiO using plasma enhanced chemical vapor deposition (PECVD, 300 ℃ C.) 2 (300nm)/Si 3 N 4 (500 nm) an insulating layer;
f) Exposing the detection electrode array, the stimulating electrode, the counter electrode and the insulating layer above the contact again by using a photoetching process, and passing through CHF 3 Reactive Ion Etching (RIE) selectively removes the insulating layer on the microelectrodes and contacts; the insulating layer covered on the surfaces of all the leads 5 is reserved;
g) The residual photoresist on the microelectrode array chip is removed by using acetone and rinsed clean with deionized water.
h) And electroplating a layer of platinum nano particles on the microelectrode array detection electrode by adopting an electrochemical timing current method, so as to improve the electrical characteristics of the detection electrode.
The preparation method of the second layer microfluidic chip of the neuron NOT gate logic function chip integrated with the microfluidic and microelectrode arrays comprises the following steps (as shown in figure 5):
1) Preparation of female mold
a) Spin-coating a layer of negative photoresist with the model SU85 on the cleaned silicon wafer, wherein the thickness is 5 mu m, and the length is 550 mu m;
b) Developing the photoresist to form a pattern on the first mask plate, exposing the micro-channel 10 for cell directional growth;
c) Spin coating a photoresist with the model SU850 on the silicon wafer subjected to the first photoetching, wherein the thickness is 100 mu m;
d) And developing the photoresist to form a pattern on a second mask plate, exposing a micro-channel 9 for the growth and flow of nerve cells, and manufacturing a master model serving as a fluidic device by photolithography.
2) PDMS mould
e) The weight ratio of Sylgard type 184 PDMS prepolymer to catalyst of Dow Corning company is 10:1, and mixing thoroughly for 5-10 minutes, and adding into a container for holding a female die for casting. Removing bubbles remaining around the pattern in the master mold with nitrogen in a vacuum dryer; PDMS was cured in an oven at 70 ℃.
f) When the PDMS is fully crosslinked or cured (the PDMS mixture will become transparent), the PDMS microfluidic device is detached from the master using a blade and a culture tank for culturing cells is punched out of the device using a punch.
And the micro-electrode array layer of the neuron NOT gate logic function chip integrating the micro-flow control and micro-electrode array and the micro-flow control chip layer are etched by plasma to activate the surface, and then are attached to form the whole chip.
Fig. 6 is a schematic diagram of a neuron-not gate logic function chip integrated with a microfluidic, microelectrode array to implement a logic-not gate function at the neuron level.
Example 1:
the neuron NOT gate logic function chip integrated with the micro-fluidic and microelectrode arrays is adopted to detect the electrophysiological signals of the primary cortical neurons
(1) The procedure for on-chip culture of primary cortical neurons was as follows:
a) Carrying out aseptic treatment on the microelectrode array chip, and coating the chip by using laminin (laminin);
b) The cell culture solution on the chip is replaced every 2-3 days, the culture is continued for 7-14 days, and the cultured neurons are subjected to fluorescent staining, so that the neurons can grow to the micro-channels in a directional manner after 5 days of culture.
(2) Detection of electrophysiological signals of nerve cells
a) Connecting the chip with the primary neurons with an interface circuit and accessing the chip into an electrophysiological signal detection instrument of Cerebus company;
b) Glutamate was added to the culture microelectrode array to stimulate nerve cell firing and the nerve cell firing status was recorded.
(3) Neuron detection on one end of an electro-stimulation chip and response of a neuron on the other end
a) Connecting the chip with the primary neurons with an interface circuit and accessing the chip into an electrophysiological signal detection instrument of Cerebus company;
b) And connecting an electric stimulation instrument of a Multichannel company with an electric stimulation electrode at the input end of the chip, respectively applying high-frequency electric stimulation and low-frequency electric stimulation, and recording the discharge condition of neurons at the output end.
The present invention is not described in detail in part as being well known to those skilled in the art. The above examples are merely illustrative of preferred embodiments of the invention, which are not exhaustive of all details, nor are they intended to limit the invention to the particular embodiments disclosed. Various modifications and improvements of the technical scheme of the present invention will fall within the protection scope of the present invention as defined in the claims without departing from the design spirit of the present invention.
Claims (8)
1. The neuron NOT gate logic function chip integrated with the micro-fluidic and micro-electrode array is characterized in that the neuron NOT gate logic function chip integrates the micro-electrode array and the micro-fluidic chip to realize that two neuron networks form a plurality of groups of one-to-one neuron interconnection in a designed micro-channel; the neuron NOT gate logic function chip comprises two layers, and the first layer microelectrode array chip (a) comprises: an insulating substrate (1), a detection electrode array (2), a stimulation electrode (3), a counter electrode (4), an electrode lead (5), a contact (6) and a surface insulating layer (7); the second layer microfluidic chip (b) includes: a cell culture tank (8), a micro-channel (9) and a group of micro-channels (10) for controlling the directional growth of neurons; the microelectrode array chip and the microfluidic chip are packaged through a plasma bonding process;
the insulating substrate (1) is a carrier for the entire microelectrode array chip (a); the detection electrode arrays (2) are respectively arranged at the input end, the output end and the center of the micro-channel (10) in three groups; the stimulating electrode (3) is positioned around the input end detecting electrode; counter electrodes (4) are arranged around the detection electrode array (2); the counter electrode (4), the stimulating electrode (3) and the detecting electrode array (2) are all extended through leads (5) and connected to contacts (6) at the periphery of the insulating substrate; the surfaces of all the leads (5) are covered with an insulating layer (7); the cell culture tank (8) in the microfluidic chip (b) is used for culturing cells; the micro flow channel (9) is connected with the cell culture tank (8) and the micro channel (10); the microchannels (10) limit the passage of the cell bodies of the nerve cells and guide the directional growth of the axons; the microelectrode array chip (a) and the microfluidic chip (b) are fixedly packaged in a bonding mode to form a chip capable of guiding nerve cells to grow directionally and realizing logic functions; the neuron NOT gate logic function chip can stimulate the neuron at one end of the micro channel (10) through the stimulating electrode, so that the neuron at the other end generates the corresponding electrophysiological signal corresponding to the neuron; the detection electrodes in the detection electrode array (2) are composed of 45-108 circular microelectrodes with the diameter of 10-30 mu m and the distance between the microelectrodes of 100-500 mu m and are used for nerve electrophysiological signals; the microelectrode array chip is provided with 15-36 pairs of arc-shaped stimulating electrodes which are wound on the detecting electrode at the input end and are used for electrically stimulating cells to realize excitation or inhibition of neuron discharge.
2. The integrated microfluidic, microelectrode array neuron not gate logic function chip of claim 1, wherein: the insulating substrate (1) is made of one of quartz glass, polyvinyl chloride or polycarbonate; the side length of the insulating substrate (1) is 20-50mm, and the thickness is 1-5mm.
3. The integrated microfluidic, microelectrode array neuron not gate logic function chip of claim 1, wherein: the electrical pulse for stimulating the neuron comprises excitatory stimulation and inhibitory stimulation, wherein the excitatory stimulation adopts low-frequency bipolar pulse waves with the frequency lower than 5Hz and the amplitude lower than 0.2V, and the inhibitory stimulation adopts high-frequency bipolar pulse waves with the frequency between 20 and 100Hz and the amplitude lower than 0.2V.
4. The integrated microfluidic, microelectrode array neuron not gate logic function chip of claim 1, wherein: the number of the counter electrodes (4) is 2-4, and the counter electrodes are used for providing reference potential and keeping potential stable.
5. The integrated microfluidic, microelectrode array neuron not gate logic function chip of claim 1, wherein: the conductive film material selected by the microelectrode array chip (a) is one of gold, platinum, titanium nitride or indium tin oxide; the insulating layer (7) is made of one of silicon dioxide, silicon nitride, silicon oxynitride, SU8, polyimide or parylene.
6. A method for preparing a neuronal NOT logic function chip integrated with a microfluidic, microelectrode array according to any of claims 1-5, comprising: preparing a first layer of microelectrode array chip (a) and a second layer of micro-fluidic chip (b), and packaging the first layer of microelectrode array chip (a) and the second layer of micro-fluidic chip (b) into a chip system in a plasma bonding mode;
the method for preparing the first layer microelectrode array chip (a) comprises the following steps:
1) spin coating a layer of photoresist on the cleaned insulating substrate (1), wherein the thickness of the photoresist is more than three times that of a conductive film to be sputtered, and forming patterns of a detection electrode array (2), a stimulation electrode (3), a counter electrode (4), a lead (5) and a contact (6) after photoetching development;
2) Sputtering a conductive film with the thickness of 250-500 nm on the surface of the photoresist pattern, optionally sputtering a Cr or Ti seed layer with the thickness of 10-50 nm in advance before sputtering a conductive film with the thickness of 250-500 nm on the surface of the photoresist pattern so as to increase the adhesiveness between the conductive film layer and a substrate;
3) Removing the redundant conductive film layer by adopting a stripping process, and leaving the required electrode, the lead (5) and the contact (6);
4) The insulating layer is covered on the surface of the insulating substrate (1) with the prepared conductive film layer by a method of Plasma Enhanced Chemical Vapor Deposition (PECVD) silicon oxide and/or silicon nitride or spin coating SU8, polyimide and parylene, and the insulating layer covered on the surfaces of all leads (5) is reserved by a photoetching or plasma beam etching method to expose the detection electrode array (2), the stimulation electrode (3), the counter electrode (4) and the contacts (6);
5) Preparing a platinum metal film layer with the thickness of 200-500nm on the surface of the counter electrode (4) by adopting photoetching, sputtering and stripping processes, and omitting the step if platinum is selected as the microelectrode conductive film in the step 2);
6) The nano material or sensitive film material is modified on the surface of microelectrode with different functions by electrochemical deposition or physical dripping and adsorption.
7. The method of manufacturing according to claim 6, wherein: the second layer of microfluidic chip (b) is prepared by pouring polydimethylsiloxane or polymethyl methacrylate into a master mold made of SU8 photoresist.
8. The method of manufacturing according to claim 6, wherein: a method of preparing a second layer of microfluidic chip (b), comprising the steps of:
1) Master mold manufacturing
A. Spin-coating photoresist on the cleaned silicon wafer, wherein the thickness is 5-10 mu m, the length is 400-900 mu m, and a micro-channel (10) for directional growth of cells is exposed after photoetching development;
B. spin-coating photoresist on the silicon wafer after the previous process, wherein the thickness is 50-200 mu m, and exposing a micro-channel (9) for nerve cell growth and flow after the photoetching development;
2) Fabrication of microfluidic devices
C. Mixing the polydimethylsiloxane prepolymer and the catalyst for 5-10 minutes, and pouring the mixture into a master mold;
D. removing bubbles remaining around the pattern in the master mold;
E. curing PDMS;
F. the microfluidic device was separated from the master model, and a cell culture tank (8) was fabricated in the microfluidic device using a puncher.
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