CN113627120B - Superconducting integrated circuit layout optimization method and device, storage medium and terminal - Google Patents
Superconducting integrated circuit layout optimization method and device, storage medium and terminal Download PDFInfo
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Abstract
The invention discloses a superconducting integrated circuit layout optimization method and device, a storage medium and a terminal, wherein the method comprises the following steps: performing modularized treatment on the netlist to be laid out to obtain segmentation modules, and performing layout optimization on all segmentation modules to obtain an optimized circuit layout; wherein, the layout optimization of the segmentation module comprises: determining the size of a layout space required by the segmentation module; performing position arrangement optimization on all logic gate units in the partition module; mapping the result to a layout plan to obtain the layout of the segmentation module; placing all the confluence buffer units in the segmentation module into a layout, performing position optimization on all the units in the layout through a second global optimizer, and performing clock optimization on all the logic gate units containing clocks in the layout; the invention realizes the automatic layout optimization of the large-scale superconducting integrated circuit, replaces the original manual design flow, improves the design scale of the superconducting integrated circuit and shortens the design iteration period.
Description
Technical Field
The present invention relates to the technical field of superconducting integrated circuit layout, and in particular, to a method and apparatus for optimizing a superconducting integrated circuit layout, a storage medium, and a terminal.
Background
Superconducting integrated circuits refer to integrated circuits based on josephson junctions and superconducting materials, including Single-Flux-Quantum (SFQ) circuits, among other applications.
The SFQ circuit is a relatively special superconducting integrated circuit, which mainly consists of Josephson junctions, and digital logic '0' and '1' are represented by the existence of magnetic flux quanta. The tiny and quantized nature of the flux quanta significantly reduces the effects of crosstalk and power consumption compared to conventional semiconductor CMOS (Complementary Metal Oxide Semiconductor) circuits, and the narrow voltage pulses generated in the junction as the flux quanta enter and exit the loop also allow them to achieve extremely high frequencies. The circuit has the advantages of ultra-high working speed and extremely low power consumption, and has remarkable prospect in the application of ultra-wide bandwidth Analog-to-Digital Converter (ADC), superconducting computers and the like.
Because superconducting integrated circuits such as SFQ circuits and the like adopt gate-level running water, special clock tree structures and the like, the existing electronic design automation tools (EDA) with commercial and open sources are insufficient to support the superconducting integrated circuits to meet the requirement of large-scale automatic design, and for the superconducting integrated circuits such as SFQ circuits and the like with ten thousand junction levels and above, manual layout optimization takes a great amount of time, and the iteration period of a chip is seriously influenced.
Disclosure of Invention
The technical problem to be solved by the invention is that the existing electronic design automation tool cannot meet the requirements of large-scale automatic design of superconducting integrated circuits such as SFQ circuits and the like, and manual layout optimization takes a great amount of time, so that the iteration period of a chip is seriously affected.
In order to solve the above technical problems, the present invention provides a superconducting integrated circuit layout optimization method, including:
obtaining a circuit netlist of a circuit to be placed, and preprocessing the circuit netlist to obtain a netlist to be placed;
performing modularized processing on the netlist to be laid out to obtain at least one segmentation module, and performing layout optimization on all segmentation modules respectively to obtain an optimized circuit layout;
wherein performing layout optimization on the segmentation module includes:
determining and storing the size of a layout space required by each stage of logic depth group in the segmentation module;
based on the size of a layout space required by each stage of logic depth group in the segmentation module, performing position arrangement optimization on all logic gate units in the segmentation module through a first global optimizer to obtain a preliminary optimization result;
mapping the preliminary optimization result into a layout plan, and adding the unit information of all the logic gate units into the layout plan to obtain the layout of the segmentation module;
placing all the confluence buffer units in the segmentation module into the layout by a preset placing mode, performing position optimization on all the units in the layout by a second global optimizer, and performing clock optimization on all the logic gate units containing clocks in the layout;
the optimization target of the first global optimizer is that the linear combination of the length mean value of the interconnection line and the length variance of the interconnection line is minimum, and the constraint condition is that the movement in the random y-axis direction is carried out; the optimization objective of the second global optimizer is that the linear combination of the length of the interconnection line, the time sequence constraint, the congestion condition and the compensation term is minimum, and the constraint condition is that the x-axis direction, the y-axis direction, the rotation is performed with the first probability and the replacement of the unit layout type is performed with the second probability.
Optimally, preprocessing the circuit netlist to obtain a netlist to be placed comprises the following steps:
and removing all interconnection line units except the bus buffer unit in the circuit netlist to obtain a netlist to be placed, and carrying out circuit statistics on the netlist to be placed.
Optimally, performing modularized processing on the netlist to be placed to obtain at least one segmentation module comprises the following steps:
dividing the netlist to be laid out based on preset dividing conditions to obtain at least one dividing module;
the preset segmentation conditions are that the segmentation is performed transversely by a minimum segmentation algorithm, and the segmentation is performed longitudinally by the principle that logic depths are kept consistent.
Preferably, before performing layout optimization on all the segmentation modules, the method further comprises:
performing layout optimization on all the segmentation modules through a third global optimizer;
the optimization objective of the third global optimizer is as follows: the product of the difference between the abscissa and the difference between the abscissa of the minimum and the maximum coordinates of each of the division modules is minimum, and the linear combination of the total distance of the interconnect manhattan distances between all the division modules and the variance of the manhattan distances of all the interconnect lines is minimum; the constraint conditions of the third global optimizer are: the difference between the horizontal coordinates of the minimum coordinates and the maximum coordinates of each dividing module is smaller than a first threshold, the difference between the vertical coordinates of the minimum coordinates and the maximum coordinates of each dividing module is smaller than a second threshold, the sum of the lengths of any two dividing modules is smaller than a third threshold, and the sum of the widths of any two dividing modules is smaller than a fourth threshold.
Optimally, determining the size of the layout space required by each stage of logic depth group in the segmentation module comprises:
the height acquisition mode of all the level logic depth groups is as follows: obtaining the number of units in all the level logic depth groups, selecting the maximum number of units as a height reference value, and setting the heights of all the level logic depth groups according to the height reference value;
the width calculation mode of each logic depth group is as follows: the number of cells, the number of clock terminals, and the number of signal lines in the current stage logic depth group.
Optimally, placing all the confluence buffer units in the segmentation module into the layout by a preset placement mode comprises the following steps:
extracting all confluence buffer units in the segmentation module to form a temporary queue;
acquiring a first confluence buffer unit of the temporary queue as a unit to be placed;
judging whether the previous stage unit of the unit to be placed is placed or not, if yes, placing the unit to be placed back to the tail end of the temporary queue, and re-acquiring the first confluence buffer unit of the current temporary queue as the unit to be placed, and re-judging the unit to be placed;
wherein placing the unit to be placed includes:
and acquiring the position midpoints of all the previous stage units of the unit to be placed as reference midpoints, placing the unit to be placed based on the reference midpoints, and recording the placement positions of the unit to be placed into a database of the confluence buffer unit.
Optimally, performing clock optimization on all logic gate units containing clocks in the layout comprises:
if the logic gate containing the clock is called a clock unit;
calculating all leaf nodes based on the coordinate positions of the clock units and a preset fan-out value;
and performing position optimization on the clock unit through a fourth global optimizer;
the optimization target of the fourth global optimizer is that the total length of all the clock unit interconnection lines is shortest; the constraint conditions of the fourth global optimizer are: the clock unit is rotated.
In order to solve the technical problem, the invention also provides a superconducting integrated circuit layout optimizing device, which is characterized by comprising a pretreatment mechanism and an optimizing mechanism;
the pretreatment mechanism is used for obtaining a circuit netlist of a circuit to be placed and carrying out pretreatment on the circuit netlist to obtain the netlist to be placed;
the optimizing mechanism is used for carrying out modularized processing on the netlist to be laid out to obtain at least one segmentation module, and carrying out layout optimization on all the segmentation modules respectively to obtain an optimized circuit layout;
wherein performing layout optimization on the segmentation module includes:
determining and storing the size of a layout space required by each stage of logic depth group in the segmentation module;
based on the size of a layout space required by each stage of logic depth group in the segmentation module, performing position arrangement optimization on all logic gate units in the segmentation module through a first global optimizer to obtain a preliminary optimization result;
mapping the preliminary optimization result into a layout plan, and adding the unit information of all the logic gate units into the layout plan to obtain the layout of the segmentation module;
placing all the confluence buffer units in the segmentation module into the layout by a preset placing mode, performing position optimization on all the units in the layout by a second global optimizer, and performing clock optimization on all the logic gate units containing clocks in the layout;
the optimization target of the first global optimizer is that the linear combination of the length mean value of the interconnection line and the length variance of the interconnection line is minimum, and the constraint condition is that the movement in the random y-axis direction is carried out; the optimization objective of the second global optimizer is that the linear combination of the length of the interconnection line, the time sequence constraint, the congestion condition and the compensation term is minimum, and the constraint condition is that the x-axis direction, the y-axis direction, the rotation is performed with the first probability and the replacement of the unit layout type is performed with the second probability.
In order to solve the above technical problem, the present invention also provides a storage medium having stored thereon a computer program, characterized in that the program when executed by a processor implements the superconducting integrated circuit layout optimization method.
In order to solve the technical problem, the present invention further provides a terminal, which is characterized by comprising: a processor and a memory;
the memory is used for storing a computer program, and the processor is used for executing the computer program stored by the memory so as to enable the terminal to execute the superconducting integrated circuit layout optimization method.
One or more embodiments of the above-described solution may have the following advantages or benefits compared to the prior art:
by applying the superconducting integrated circuit layout optimization method provided by the embodiment of the invention, the automatic layout optimization of the large-scale superconducting integrated circuit can be realized, namely, the superconducting integrated circuit netlist is converted into the physical layout by performing multiple optimization on each segmentation module, the original manual design flow is replaced, the design scale of the superconducting integrated circuit is improved, and the design iteration period is shortened. After the preprocessing operation, the method can effectively generate a data structure suitable for segmenting the superconducting integrated circuit netlist, and improves the segmentation operation effect; the circuit netlist is divided into a plurality of dividing modules, so that the subsequent optimized layout result is better; the invention adopts a layout device optimized for the Bit-Slice structure, so that the layout result is more in line with the structure and data flow mode of the superconducting integrated circuit.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification, illustrate the invention and together with the embodiments of the invention, serve to explain the invention, without limitation to the invention. In the drawings:
FIG. 1 is a flow chart of a method for optimizing a layout of a superconducting integrated circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram showing the effect of preprocessing a circuit netlist in accordance with a first embodiment of the present invention;
FIG. 3 is a schematic diagram showing the effect of modular processing of a netlist to be placed in accordance with one embodiment of the present invention;
fig. 4 is a schematic diagram showing an effect of layout optimization for all the partition modules in the first embodiment of the present invention;
FIG. 5 is a schematic flow chart of layout optimization of a pair of segmentation modules according to an embodiment of the present invention;
FIG. 6 is a schematic diagram showing the effect of determining the size of the layout space required for each stage of logic depth group in the partition module according to the first embodiment of the present invention;
FIG. 7 is a schematic flow chart of a first global optimizer as a modified simulated annealing algorithm in accordance with a first embodiment of the present invention;
FIG. 8 is a schematic diagram showing the effect of performing position optimization on a clock unit by a fourth global optimizer in accordance with the first embodiment of the present invention;
FIG. 9 is a schematic diagram of a layout optimizing apparatus for a second superconducting integrated circuit according to an embodiment of the present invention;
fig. 10 shows the structural intent of the fourth terminal of the embodiment of the present invention.
Detailed Description
The following will describe embodiments of the present invention in detail with reference to the drawings and examples, thereby solving the technical problems by applying technical means to the present invention, and realizing the technical effects can be fully understood and implemented accordingly. It should be noted that, as long as no conflict is formed, each embodiment of the present invention and each feature of each embodiment may be combined with each other, and the formed technical solutions are all within the protection scope of the present invention.
Because superconducting integrated circuits such as SFQ circuits and the like adopt gate-level running water, special clock tree structures and the like, the existing electronic design automation tools (EDA) with commercial and open sources are insufficient to support the superconducting integrated circuits to meet the requirement of large-scale automatic design, and for the superconducting integrated circuits such as SFQ circuits and the like with ten thousand junction levels and above, manual layout optimization takes a great amount of time, and the iteration period of a chip is seriously influenced.
Example 1
In order to solve the technical problems in the prior art, the embodiment of the invention provides a superconducting integrated circuit layout optimization method.
FIG. 1 is a flow chart of a method for optimizing a layout of a superconducting integrated circuit according to an embodiment of the present invention; referring to fig. 1, the superconducting integrated circuit layout optimization method according to the embodiment of the invention comprises the following steps.
Step S101, obtaining a circuit netlist of a circuit to be placed, and preprocessing the circuit netlist to obtain the netlist to be placed.
Specifically, a circuit netlist of a circuit to be placed after logic synthesis is obtained, and then the circuit netlist is preprocessed to obtain the circuit netlist to be placed. FIG. 2 is a schematic diagram showing the effect of preprocessing a circuit netlist in accordance with a first embodiment of the present invention; referring to FIG. 2, preprocessing a circuit netlist includes: in addition to the bus buffer cells, interconnect line cells in the circuit netlist are removed to facilitate optimization of subsequent global layouts. Meanwhile, in the stage, circuit information statistics is carried out on the netlist to be placed, and if unrecognizable units exist in the netlist to be placed, the unrecognizable units are marked as macro units; and if the situation that the circuit netlist cannot be analyzed normally is found in the modification stage, the exception is thrown out, the current program is directly exited, and the circuit layout optimization of the current circuit to be laid out is finished.
Step S102, carrying out modularization processing on the netlist to be laid out to obtain at least one segmentation module, and carrying out layout optimization on all segmentation modules respectively to obtain an optimized circuit layout.
Specifically, the netlist to be placed is segmented based on preset segmentation conditions, and at least one segmentation module is obtained. FIG. 3 is a schematic diagram showing the effect of modular processing of a netlist to be placed in accordance with one embodiment of the present invention; referring to fig. 3, the preset dividing condition is controlled by the user, and if the user does not input the dividing condition constraint, the dividing is performed according to the program default dividing condition. Preferably, the default segmentation condition can be set to be that the segmentation is performed transversely by a minimum segmentation algorithm, and the segmentation is performed longitudinally by the principle that the logic depth is consistent. It should be noted that after the division based on the above-mentioned preset dividing condition, the netlist to be placed may be divided into a plurality of dividing modules, and may still be an integral (i.e. the netlist to be placed).
When the netlist to be laid out is divided into a plurality of divided modules, top-level layout optimization can be performed on all the divided modules through a third global optimizer so as to obtain the position layout of each divided module. Fig. 4 is a schematic diagram showing an effect of layout optimization for all the partition modules in the first embodiment of the present invention; referring to fig. 4, the optimization objective of the third global optimizer is set as: the product of the difference between the abscissa and the ordinate of the minimum and maximum coordinates of each segment module is minimum, that is, if the minimum coordinates of the segment modules are (x_min, y_min) and the maximum coordinates are (x_max, y_max), the (y_max-y_min) of each segment module is minimum; at the same time, the minimum linear combination of the total distance of the Manhattan distances of the interconnection lines between all the division modules and the variance of the Manhattan distances of all the interconnection lines is required. Meanwhile, the constraint conditions of the third global optimizer are set as follows: the difference between the minimum coordinate and the maximum coordinate of each split module is smaller than a first threshold, the difference between the minimum coordinate and the maximum coordinate of each split module is smaller than a second threshold, the sum of the lengths of any two split modules is smaller than a third threshold, and the sum of the widths of any two split modules is smaller than a fourth threshold.
Preferably, according to the optimization target and the constraint condition, the top-level layout optimization problem can be solved by using the existing convex optimization solver, and finally the optimized positions of the segmentation modules are obtained.
Further, since there is no constraint imposed on the wiring of the interconnect lines, the wiring space between the layout blocks may be relatively small, and the wiring space size needs to be calculated according to the condition of the interconnect lines between the layout blocks. Specific calculation methods of the wiring space size include a final relative wiring width determination process and a movement process. Wherein the final relative wiring width determination process for each two interconnected segmented modules is: setting the initial minimum wiring space width of two interconnected split modules as 1, analyzing each interconnection line between the two split modules, checking a rectangular area formed by the starting point and the end point of each interconnection line, if the rectangular areas formed by the interconnection lines between the two split modules are overlapped, repeating the process until the final relative wiring width of the two interconnected split modules is obtained. The final relative wiring widths of all the two mutually connected divided modules are obtained in the above manner. The moving process is as follows: and finding out a layout midpoint of the whole layout, taking the layout midpoint as a midpoint, and moving all the split modules towards a direction away from the midpoint based on the final relative wiring widths of all the two interconnected split modules.
It should be noted that, when the netlist to be placed is divided into a division module (i.e. a netlist body to be placed), the top-level layout optimization process may be performed, but the netlist to be placed after top-level optimization is still output as the netlist body to be placed.
After the top layer optimization of each split module is completed, layout optimization is performed on each split module, and the process of performing layout optimization on each split module is the same, and the global layout optimization process of only one split module is taken as an example for illustration. The layout optimization of the segmentation module includes the following steps. FIG. 5 is a schematic flow chart of layout optimization of a pair of segmentation modules according to an embodiment of the present invention; reference is made to fig. 5.
In step 201, the size of the layout space required for each level of logical depth group in the segmentation module is determined and stored.
Specifically, the size of the layout space required for all stages of logic depths is estimated based on the number of units, clock terminals and signal lines included in each stage of logic depths, and the calculation result is stored in a layout planning dictionary. FIG. 6 is a schematic diagram showing the effect of determining the size of the layout space required for each stage of logic depth group in the partition module according to the first embodiment of the present invention; referring to fig. 6, the layout space size required for all the stage logic depths is obtained by: the height acquisition mode of all the level logic depth groups is as follows: obtaining the number of units in all the level logic depth groups, selecting the maximum number of units as a height reference value, and setting the heights of all the level logic depth groups according to the height reference value; for example: the first stage logic depth group is 5 logic gate units, the second stage logic depth group is 3 logic gate units, the third stage logic depth group is 6 logic gate units, and finally, the heights of all the stage logic depth groups are 6. The width calculation mode of each logic depth group is as follows: the number of cells, the number of clock terminals, and the number of signal lines in the current stage logic depth group. For example: the width of the current stage logic depth group=a×cell number+b×log2 (clock end number) +c×signal line number+d×compensation function.
It should be noted that, multi-core operation can be performed on all the partition modules, so that the layout plan of all the partition modules can be synchronously calculated; after the layout planning of all the sub-modules is completed, a user can enter each segmentation module as required to check the optimization result, and the layout planning result is modified according to the design requirement.
Step S202, based on the size of the layout space required by each stage of logic depth group in the segmentation module, performing position arrangement optimization on all logic gate units in the segmentation module through a first global optimizer, and obtaining a preliminary optimization result.
Specifically, on the basis of the size of a layout space required by each stage of logic depth group in a known segmentation module, the position arrangement optimization of each logic gate unit in the segmentation module in the layout space is completed through a first global optimizer, and a preliminary optimization result is obtained. Wherein the optimization objective of the first global optimizer is that the linear combination of the interconnect length mean and the interconnect length variance is minimal, and the constraint is that the movement in the random y-axis direction. FIG. 7 is a schematic flow chart of a first global optimizer as a modified simulated annealing algorithm in accordance with a first embodiment of the present invention; referring to FIG. 7, the first global optimizer may preferably select a variety of global optimizers, here exemplified by a modified simulated annealing algorithm, with the minimum of the linear combination of interconnect length mean and interconnect length variance as the optimization goal. In the simulated annealing process, a certain number of logic gate units are firstly selected to move in the random y-axis direction, the random distance is moved, the number of units selected by a single operation and the random distance are gradually reduced along with the temperature reduction, and the movement of the units is stopped when the temperature reaches the minimum temperature. After a single operation, it is determined whether to accept the operation according to the Metropolis criterion.
And step S203, mapping the preliminary optimization result into a layout plan, and adding the unit information of all the logic gate units into the layout plan to obtain the layout of the segmentation module.
Specifically, after the global layout optimization is completed, mapping the result of the global layout optimization, namely the preliminary optimization result, into a layout plan, and adding the unit information of all the logic gate units into the layout plan to obtain the layout of the segmentation module so as to convert the virtual circuit diagram into the layout with the spatial position attribute and the process attribute. Wherein the cell information includes process information of the logic gate cell, shape of the logic gate cell, and port position distribution information.
And S204, placing all the confluence buffer units in the segmentation module into the layout by a preset placement mode, performing position optimization on all the units in the layout by a second global optimizer, and performing clock optimization on all the logic gate units containing clocks in the layout.
Specifically, the placement of all the bus buffer units in the split module needs to be optimized first, and all the bus buffer units in the split module are placed at proper positions in the layout. All the bus buffer unit placement processes specifically include: extracting all confluence buffer units in the segmentation module and forming a temporary queue randomly; then, a first confluence buffer unit of the temporary queue is obtained and is used as a unit to be placed; judging whether a previous stage unit of the unit to be placed is placed or not, if yes, placing the unit to be placed back to the tail end of the temporary queue, and re-acquiring a first confluence buffer unit of the current temporary queue as the unit to be placed; the above process is repeated until all of the bus buffer units in the split module are placed. Further, the process of placing the unit to be placed includes: and acquiring the position midpoints of all the previous stage units of the unit to be placed as reference midpoints, placing the unit to be placed based on the reference midpoints, namely judging whether redundant layout space exists near the reference midpoints, if not, randomly moving to the periphery until a position is found to be placed, and recording the placement position of the unit to be placed into a database of the confluence buffer unit after the placement is completed.
And then, carrying out position optimization on all units in the layout by a second global optimizer. The optimization target of the second global optimizer is that the linear combination of the length of the interconnection line, the time sequence constraint, the congestion condition and the compensation term is minimum, and the constraint condition of the second global optimizer is that the second global optimizer rotates in the x-axis direction and the y-axis direction with the first probability and replaces the unit layout type with the second probability. Further, the selection range of the first probability and the second probability is 0.01-0.1. Preferably, the second global optimizer may select a variety of global optimizers, i.e. the second global optimizer may still be an example of a modified simulated annealing algorithm.
And finally, performing clock optimization on all logic gate units containing clocks in the layout. FIG. 8 is a schematic diagram showing the effect of performing position optimization on a clock unit by a fourth global optimizer in accordance with the first embodiment of the present invention; referring to fig. 8, to realize the local layout optimization for the clock tree, if the partition module is a clock tree driving module, the program will establish a virtual clock tree according to the clock tree conditions set by the user, and optimize the unit rotation direction for the position of the virtual clock tree. Further, performing clock optimization on all logic gate units containing clocks in the layout comprises: if the logic gate containing the clock is called a clock unit; calculating all leaf nodes based on the coordinate positions of all clock units in the layout and a preset fan-out value; and performing position optimization on the clock unit through a fourth global optimizer. The optimization target of the fourth global optimizer is that the total length of all clock unit interconnection lines is shortest; the constraint conditions of the fourth global optimizer are: the clock unit is rotated.
After the layout optimization of all the segmentation modules is completed, a user can output optimized netlist files (verilog) and layout information (DEF files or il files) as required to serve as guide information files for the follow-up clock tree synthesis and wiring optimization.
The superconducting integrated circuit layout optimization method provided by the embodiment of the invention can realize automatic layout optimization of a large-scale superconducting integrated circuit, namely, the superconducting integrated circuit netlist is converted into a physical layout by performing multiple optimization on each segmentation module, so that the original manual design flow is replaced, the design scale of the superconducting integrated circuit is improved, and the design iteration period is shortened. After the preprocessing operation, the method can effectively generate a data structure suitable for segmenting the superconducting integrated circuit netlist, and improves the segmentation operation effect; the circuit netlist is divided into a plurality of dividing modules, so that the subsequent optimized layout result is better; the invention adopts a layout device optimized for the Bit-Slice structure, so that the layout result is more in line with the structure and data flow mode of the superconducting integrated circuit.
Example two
In order to solve the technical problems in the prior art, the embodiment of the invention provides a superconducting integrated circuit layout optimization device.
FIG. 9 is a schematic diagram of a layout optimizing apparatus for a second superconducting integrated circuit according to an embodiment of the present invention; referring to fig. 9, the superconducting integrated circuit layout optimizing apparatus according to the embodiment of the present invention includes a pretreatment mechanism and an optimizing mechanism.
The pretreatment mechanism is used for obtaining a circuit netlist of a circuit to be identified, and carrying out pretreatment on the circuit netlist to obtain a netlist to be laid out;
the optimizing mechanism performs modularized processing on the netlist to be laid out to obtain at least one segmentation module, and performs global layout optimization on all segmentation modules to obtain an optimized circuit layout;
the global layout optimization of the segmentation module comprises the following steps:
determining and storing the size of a layout space required by each level of logic depth group in the segmentation module;
based on the size of a layout space required by each stage of logic depth group in the segmentation module, carrying out position arrangement optimization on all logic gate units in the segmentation module through a first global optimizer, and obtaining a preliminary optimization result;
mapping the preliminary optimization result into a layout plan, adding the unit information of all logic gate units into the layout plan, and obtaining the layout of the segmentation module;
placing all the confluence buffer units in the segmentation module into the layout by a preset placing mode, performing position optimization on all the units in the layout by a second global optimizer, and performing clock optimization on all the logic gate units containing clocks in the layout;
the optimization target of the first global optimizer is that the linear combination of the length mean value of the interconnection line and the length variance of the interconnection line is minimum, and the constraint condition is that the movement in the random y-axis direction is carried out; the optimization objective of the second global optimizer is that the linear combination of interconnect line length, timing constraints, congestion conditions and compensation terms is minimal, and the constraints are x-axis direction, y-axis direction, rotation with a first probability, and cell layout type replacement with a second probability.
The superconducting integrated circuit layout optimization device provided by the embodiment of the invention can realize automatic layout optimization of a large-scale superconducting integrated circuit, namely, the superconducting integrated circuit netlist is converted into a physical layout by performing multiple optimization on each segmentation module, so that the original manual design flow is replaced, the design scale of the superconducting integrated circuit is improved, and the design iteration period is shortened. After the preprocessing operation, the device can effectively generate a data structure suitable for segmenting the superconducting integrated circuit netlist, and improves the segmentation operation effect; the circuit netlist is divided into a plurality of dividing modules, so that the subsequent optimized layout result is better; the invention adopts a layout device optimized for the Bit-Slice structure, so that the layout result is more in line with the structure and data flow mode of the superconducting integrated circuit.
Example III
To solve the above-mentioned technical problems in the prior art, an embodiment of the present invention further provides a storage medium storing a computer program, where the computer program when executed by a processor can implement all the steps in the superconducting integrated circuit layout optimization method of the embodiment.
The specific steps of the superconducting integrated circuit layout optimization method and the beneficial effects obtained by applying the readable storage medium provided by the embodiment of the invention are the same as those of the first embodiment, and are not described in detail herein.
It should be noted that: the storage medium includes: various media that can store program code, such as ROM, RAM, magnetic or optical disks.
Example IV
In order to solve the technical problems in the prior art, the embodiment of the invention also provides a terminal.
Fig. 10 is a schematic structural diagram of a fourth terminal according to the embodiment of the present invention, and referring to fig. 10, the terminal according to the embodiment includes a processor and a memory that are connected to each other; the memory is used for storing a computer program, and the processor is used for executing the computer program stored in the memory, so that the terminal can realize all the steps in the superconducting integrated circuit layout optimization method in the first embodiment when executing the computer program.
The specific steps of the superconducting integrated circuit layout optimization method and the beneficial effects obtained by the terminal provided by the embodiment of the invention are the same as those of the first embodiment, and are not repeated here.
It should be noted that the memory may include a random access memory (Random Access Memory, abbreviated as RAM) and may further include a non-volatile memory (non-volatile memory), such as at least one magnetic disk memory. The same processor may be a general processor, including a central processing unit (Central Processing Unit, CPU for short), a network processor (Network Processor, NP for short), etc.; but also digital signal processors (Digital Signal Processing, DSP for short), application specific integrated circuits (Application Specific Integrated Circuit, ASIC for short), field programmable gate arrays (Field Programmable Gate Array, FPGA for short) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.
Although the embodiments of the present invention are disclosed above, the embodiments are only used for the convenience of understanding the present invention, and are not intended to limit the present invention. Any person skilled in the art can make any modification and variation in form and detail without departing from the spirit and scope of the present disclosure, but the scope of the present disclosure is still subject to the scope of the present disclosure as defined by the appended claims.
Claims (10)
1. A superconducting integrated circuit layout optimization method, comprising:
obtaining a circuit netlist of a circuit to be placed, and preprocessing the circuit netlist to obtain a netlist to be placed;
performing modularized processing on the netlist to be laid out to obtain at least one segmentation module, and performing layout optimization on all segmentation modules respectively to obtain an optimized circuit layout;
wherein performing layout optimization on the segmentation module includes:
determining and storing the size of a layout space required by each stage of logic depth group in the segmentation module;
based on the size of a layout space required by each stage of logic depth group in the segmentation module, performing position arrangement optimization on all logic gate units in the segmentation module through a first global optimizer to obtain a preliminary optimization result;
mapping the preliminary optimization result into a layout plan, and adding the unit information of all the logic gate units into the layout plan to obtain the layout of the segmentation module;
placing all the confluence buffer units in the segmentation module into the layout by a preset placing mode, performing position optimization on all the units in the layout by a second global optimizer, and performing clock optimization on all the logic gate units containing clocks in the layout;
the optimization target of the first global optimizer is that the linear combination of the length mean value of the interconnection line and the length variance of the interconnection line is minimum, and the constraint condition is that the movement in the random y-axis direction is carried out; the optimization objective of the second global optimizer is that the linear combination of the length of the interconnection line, the time sequence constraint, the congestion condition and the compensation term is minimum, and the constraint condition is that the x-axis direction, the y-axis direction, the rotation is performed with the first probability and the replacement of the unit layout type is performed with the second probability.
2. The method of claim 1, wherein preprocessing the circuit netlist to obtain a netlist to be placed comprises:
and removing all interconnection line units except the bus buffer unit in the circuit netlist to obtain a netlist to be placed, and carrying out circuit statistics on the netlist to be placed.
3. The method of claim 1, wherein modularly processing the netlist to be placed to obtain at least one split module comprises:
dividing the netlist to be laid out based on preset dividing conditions to obtain at least one dividing module;
the preset segmentation conditions are that the segmentation is performed transversely by a minimum segmentation algorithm, and the segmentation is performed longitudinally by the principle that logic depths are kept consistent.
4. The method of claim 1, further comprising, prior to layout optimizing all of the segmentation modules:
performing layout optimization on all the segmentation modules through a third global optimizer;
the optimization objective of the third global optimizer is as follows: the product of the difference between the abscissa and the difference between the abscissa of the minimum and the maximum coordinates of each of the division modules is minimum, and the linear combination of the total distance of the interconnect manhattan distances between all the division modules and the variance of the manhattan distances of all the interconnect lines is minimum; the constraint conditions of the third global optimizer are: the difference between the horizontal coordinates of the minimum coordinates and the maximum coordinates of each dividing module is smaller than a first threshold, the difference between the vertical coordinates of the minimum coordinates and the maximum coordinates of each dividing module is smaller than a second threshold, the sum of the lengths of any two dividing modules is smaller than a third threshold, and the sum of the widths of any two dividing modules is smaller than a fourth threshold.
5. The method of claim 1, wherein determining the size of the layout space required for each level of logical depth groups in the segmentation module comprises:
the height acquisition mode of all the level logic depth groups is as follows: obtaining the number of units in all the level logic depth groups, selecting the maximum number of units as a height reference value, and setting the heights of all the level logic depth groups according to the height reference value;
the width calculation mode of each logic depth group is as follows: the number of cells, the number of clock terminals, and the number of signal lines in the current stage logic depth group.
6. The method according to claim 1, wherein placing all bus buffer units in the segmentation module into the layout by a preset placement method comprises:
extracting all confluence buffer units in the segmentation module to form a temporary queue;
acquiring a first confluence buffer unit of the temporary queue as a unit to be placed;
judging whether the previous stage unit of the unit to be placed is placed or not, if yes, placing the unit to be placed back to the tail end of the temporary queue, and re-acquiring the first confluence buffer unit of the current temporary queue as the unit to be placed, and re-judging the unit to be placed;
wherein placing the unit to be placed includes:
and acquiring the position midpoints of all the previous stage units of the unit to be placed as reference midpoints, placing the unit to be placed based on the reference midpoints, and recording the placement positions of the unit to be placed into a database of the confluence buffer unit.
7. The method of claim 1, wherein clock optimizing all logic gate units in the layout that contain clocks comprises:
if the logic gate containing the clock is called a clock unit;
calculating all leaf nodes based on the coordinate positions of the clock units and a preset fan-out value;
and performing position optimization on the clock unit through a fourth global optimizer;
the optimization objective of the fourth global optimizer is as follows: the total length of all the clock unit interconnection lines is shortest; the constraint conditions of the fourth global optimizer are: the clock unit is rotated.
8. A superconducting integrated circuit layout optimizing device is characterized by comprising a pretreatment mechanism and an optimizing mechanism;
the pretreatment mechanism is used for obtaining a circuit netlist of a circuit to be placed and carrying out pretreatment on the circuit netlist to obtain the netlist to be placed;
the optimizing mechanism is used for carrying out modularized processing on the netlist to be laid out to obtain at least one segmentation module, and carrying out layout optimization on all the segmentation modules respectively to obtain an optimized circuit layout;
wherein performing layout optimization on the segmentation module includes:
determining the size of a layout space required by each stage of logic depth group in the segmentation module;
based on the size of a layout space required by each stage of logic depth group in the segmentation module, performing position arrangement optimization on all logic gate units in the segmentation module through a first global optimizer to obtain a preliminary optimization result;
mapping the preliminary optimization result into a layout plan, and adding the unit information of all the logic gate units into the layout plan to obtain the layout of the segmentation module;
placing all the confluence buffer units in the segmentation module into the layout by a preset placing mode, performing position optimization on all the units in the layout by a second global optimizer, and performing clock optimization on all the logic gate units containing clocks in the layout;
the optimization target of the first global optimizer is that the linear combination of the length mean value of the interconnection line and the length variance of the interconnection line is minimum, and the constraint condition is that the movement in the random y-axis direction is carried out; the optimization objective of the second global optimizer is that the linear combination of the length of the interconnection line, the time sequence constraint, the congestion condition and the compensation term is minimum, and the constraint condition is that the x-axis direction, the y-axis direction, the rotation is performed with the first probability and the replacement of the unit layout type is performed with the second probability.
9. A storage medium having stored thereon a computer program, which when executed by a processor implements the superconducting integrated circuit layout optimization method of any one of claims 1 to 7.
10. A terminal, comprising: a processor and a memory;
the memory is configured to store a computer program, and the processor is configured to execute the computer program stored in the memory, to cause the terminal to execute the superconducting integrated circuit layout optimization method according to any one of claims 1 to 7.
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