CN113625989A

CN113625989A - Data operation device, method, electronic device, and storage medium

Info

Publication number: CN113625989A
Application number: CN202110808803.XA
Authority: CN
Inventors: 曹庆新; 李炜
Original assignee: Shenzhen Intellifusion Technologies Co Ltd
Current assignee: Shenzhen Intellifusion Technologies Co Ltd
Priority date: 2021-07-16
Filing date: 2021-07-16
Publication date: 2021-11-09

Abstract

The application is applicable to the technical field of computers, and provides a data operation device, a method, an electronic device and a storage medium, wherein the data operation device comprises: the data acquisition module is used for acquiring data to be operated; the data alignment module is used for comparing the exponent data of the two floating point data if the data to be operated comprises the two floating point data, determining the larger exponent data as target exponent data, and generating two target mantissa data with aligned data bits; the target operation module is used for performing target operation on the two target mantissa data and determining first mantissa result data; the index operation module is used for determining first index result data according to the target index data; and the operation result output module is used for outputting operation result data, and the operation result data comprises first operation result data determined according to the first mantissa result data and the first exponent result data. The embodiment of the application can accurately and efficiently realize the operation between floating point numbers.

Description

Data operation device, method, electronic device, and storage medium

Technical Field

The present application relates to the field of computer technologies, and in particular, to a data operation device, a data operation method, an electronic device, and a storage medium.

Background

Floating point numbers are widely used today because they can flexibly represent a wide range of values with relatively few data bits. In the process of calculating floating point numbers, the positions of decimal points of different floating point numbers are not fixed, so that the operation between the floating point numbers has certain complexity.

Disclosure of Invention

In view of this, embodiments of the present application provide a data operation device, a data operation method, an electronic device, and a storage medium, so as to solve the problem in the prior art how to accurately and efficiently implement operations between floating point numbers.

A first aspect of an embodiment of the present application provides a data operation apparatus, including:

the data acquisition module is used for acquiring data to be operated;

the data alignment module is used for comparing the exponent data of the two floating point data if the data to be operated comprises the two floating point data, determining the larger exponent data as target exponent data, and generating two target mantissa data with aligned data bits; for floating point data corresponding to smaller exponent data, selecting target number bit high-order data of mantissa data of the floating point data according to a difference value between the target exponent data and the smaller exponent data, and generating target mantissa data after the floating point data is shifted and aligned, wherein the target number is equal to the difference value subtracted by the bit number of the mantissa data of the floating point data;

the target operation module is used for performing target operation on the two target mantissa data and determining first mantissa result data;

the index operation module is used for determining first index result data according to the target index data;

and the operation result output module is used for outputting operation result data, and the operation result data comprises first operation result data determined according to the first mantissa result data and the first exponent result data.

A second aspect of an embodiment of the present application provides a data operation method, including:

acquiring data to be operated;

if the data to be operated comprises two floating point data, comparing the exponent data of the two floating point data, determining the larger exponent data as target exponent data, and generating two target mantissa data with aligned data bits; for floating point data corresponding to smaller exponent data, selecting target number bit high-order data of mantissa data of the floating point data according to a difference value between the target exponent data and the smaller exponent data, and generating target mantissa data after the floating point data is shifted and aligned, wherein the target number is equal to the difference value subtracted by the bit number of the mantissa data of the floating point data;

performing target operation on the two target mantissa data to determine first mantissa result data;

determining first index result data according to the target index data;

and outputting operation result data, wherein the operation result data comprises first operation result data determined according to the first mantissa result data and the first exponent result data.

A third aspect of embodiments of the present application provides an electronic device, including the data operation apparatus according to the first aspect.

A fourth aspect of embodiments of the present application provides a computer-readable storage medium storing a computer program which, when executed by a processor, causes an electronic device to implement the steps of the data operation method according to the second aspect.

A fifth aspect of embodiments of the present application provides a computer program product, which, when run on an electronic device, causes the electronic device to perform the data operation method as described in the second aspect.

Compared with the prior art, the embodiment of the application has the advantages that: in the embodiment of the application, data to be operated are obtained through a data obtaining module, then, when the data to be operated comprise two floating point data, the exponent data of the two floating point data are compared through a data alignment module, the larger exponent data are determined to be target exponent data, and target mantissa data with aligned data bits corresponding to each floating point data are generated; then, performing target operation on the two target mantissa data through a target operation module to obtain first mantissa result data; and determining first exponent result data according to the target exponent data through the exponent operation module, so that the operation result data can be output according to the first mantissa result data and the first exponent result data through the operation result output module. Before target operation is carried out, two target mantissa data with aligned data bits corresponding to two floating point data can be generated through the data alignment module, so that the target operation can be accurately and efficiently completed; in addition, in the data alignment module, the floating point data corresponding to the smaller exponent data is specifically shifted and aligned by selecting the target number bit high order data of the mantissa data of the floating point data, so that compared with the existing shifting mode through a shift register, the method can save operation resources, improve hardware processing efficiency, efficiently realize data bit alignment, and further improve data operation efficiency.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings used in the embodiments or the description of the prior art will be briefly described below.

FIG. 1 is a diagram illustrating a first floating point data provided by an embodiment of the present application;

FIG. 2 is a diagram illustrating a second floating point data provided by an embodiment of the present application;

FIG. 3 is a diagram of a first data operation apparatus according to an embodiment of the present application;

FIG. 4 is a diagram illustrating a second data operation apparatus according to an embodiment of the present application;

FIG. 5 is a diagram illustrating a third data operation apparatus according to an embodiment of the present disclosure;

FIG. 6 is a schematic diagram of a multiplication module according to an embodiment of the present disclosure;

FIG. 7 is a diagram illustrating a fourth data operation apparatus according to an embodiment of the present application;

FIG. 8 is a diagram illustrating a fifth data operation apparatus according to an embodiment of the present application;

FIG. 9 is a diagram illustrating a sixth data operation apparatus according to an embodiment of the present application;

FIG. 10 is a diagram illustrating a normalization module according to an embodiment of the present application;

fig. 11 is a schematic flow chart illustrating an implementation of a data operation method according to an embodiment of the present application;

fig. 12 is a schematic diagram of an electronic device provided in an embodiment of the present application.

Detailed Description

In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.

In order to explain the technical solution described in the present application, the following description will be given by way of specific examples.

It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It is also to be understood that the terminology used in the description of the present application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in the specification of the present application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It should be further understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

As used in this specification and the appended claims, the term "if" may be interpreted contextually as "when", "upon" or "in response to a determination" or "in response to a detection". Similarly, the phrase "if it is determined" or "if a [ described condition or event ] is detected" may be interpreted contextually to mean "upon determining" or "in response to determining" or "upon detecting [ described condition or event ]" or "in response to detecting [ described condition or event ]".

In addition, in the description of the present application, the terms "first," "second," "third," and the like are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.

In order to solve the above problems, an embodiment of the present application provides a data operation device, a method, an electronic device, and a storage medium, where the data operation device includes a data acquisition module, a data alignment module, a target operation module, an exponent operation module, and an operation result output module, where data to be operated is acquired by the data acquisition module, and then, when it is detected that the data to be operated includes two floating point data, the data alignment module compares the exponent data of the two floating point data, determines a larger exponent data as a target exponent data, and generates a target mantissa data, corresponding to each floating point data, with aligned data bits; then, performing target operation on the two target mantissa data through a target operation module to obtain first mantissa result data; and determining first exponent result data according to the target exponent data through the exponent operation module, so that the operation result data can be output according to the first mantissa result data and the first exponent result data through the operation result output module. Before target operation is carried out, two target mantissa data with aligned data bits corresponding to two floating point data can be generated through the data alignment module, so that the target operation can be accurately and efficiently completed; in addition, in the data alignment module, the floating point data corresponding to the smaller exponent data is specifically shifted and aligned by selecting the target number bit high order data of the mantissa data of the floating point data, so that compared with the existing shifting mode through a shift register, the method can save operation resources, improve hardware processing efficiency, efficiently realize data bit alignment, and further improve data operation efficiency.

For ease of understanding, some of the relevant concepts of the embodiments of the present application are first explained below:

the floating point data (i) refers to data corresponding to a floating point number, and may specifically be standard format data of the floating point number. The floating point number refers to data in which the position of the decimal point is not fixed, and can flexibly represent a numerical value in a larger range. The standard format data of a general floating-point number may be represented by fig. 1, and includes a sign bit (sign), an exponent data section (exponent) and a fraction data section (fraction). At this time, the actual Value (Value) of the floating point number is equal to the sign bit multiplied by the Value of the exponent data field multiplied by the Value of the fraction data field:

Value＝sign×exponent×fraction

wherein "×" represents a multiplication number.

Specifically, the floating-point data may be data conforming to the IEEE binary floating-point arithmetic standard, which logically employs a triplet { S, E, M } to represent a number N, which specifies a base number of 2, sign bits S of 0 and 1 for positive and negative, respectively, mantissa M of original code, and a level code E of shift code. According to the floating point number normalization method, the most significant bit of the mantissa field is always 1, so the standard provides that this bit is not stored, but is considered hidden to the left of the decimal point, and therefore the mantissa field represents a value of 1.M (actually stored is M), which allows the representation range of the mantissa to be one bit more than it actually stores. In order to represent the positive and negative of the exponent, the step E is usually represented by a shift code, and the exponent E of the data is added with a fixed offset to be used as the step of the number, so that the positive and negative exponents can be avoided, the original size sequence of the data can be maintained, and the comparison operation is convenient.

Illustratively, FIG. 2 shows a diagram of half-precision floating-point data under the IEEE754 standard. The leftmost bit (i.e., the most significant bit) of the half-precision floating-point data is a sign bit (sign), followed by an exponent data segment (also referred to as a level E) having a bit width of 5 bits (bits), and the rightmost bit is a fraction data segment (also referred to as a mantissa M) having a bit width of 10 bits. Specifically, the method comprises the following steps:

for sign bit sign, when its value is 0, it means that the floating-point number is positive; a value of 1 indicates that the floating point number is negative.

For the mantissa M, it contains an implicit bit 1, not shown, in addition to the 10-bit long data shown in the figure. The 10-bit data is understood to be a number after the decimal point of a half-precision floating-point number.

For the index data segment exponennt, the following cases are included:

when the exponent bits are all 0 and the mantissa bits are all 0, the floating-point number represents 0;

when the exponent bits are all 0 and the mantissa bits are not all 0, the exponent bits are represented as denormal value, and the denormal floating-point number is a very small number;

when the exponent bits are all 1 and the mantissa bits are all 0, infinity is indicated, and at this time, if the sign bit is 0, positive infinity (+ ∞) is indicated; if the sign bit is 1, negative infinity (— ∞);

when the exponent bits are all 1 and the mantissa bits are not all 0, it represents not one number (represented by NaN);

in other cases, the value of the exponent bit minus 15 (the quintic power of 2 minus 1, i.e., the value raised by the exponentiation of the exponent bit 5 minus 1) is the actual exponent value it represents, e.g., 11110 represents 30-15, which is 15.

To sum up, for the Value of a half-precision floating point number (the sign bit, the corresponding values of the exponent data segment and the fraction data segment are abbreviated as S, E, M respectively), the calculation method is as follows:

Value＝(-1)^S×2^E-15×1.M

the fixed point data is data corresponding to a fixed point number, the fixed point number is a fixed and unchangeable number of decimal points, and the fixed point number can comprise a fixed point integer and a fixed point decimal number. Wherein the fixed point integer refers to a fixed point number with a decimal point fixed at the last position, and is also called as a pure integer; the fixed point decimal is the fixed point number after the decimal point is fixed at the highest position, and is also called a pure decimal.

The fixed-point data may be integer data representing a pure integer in binary form in a computer, for example, 16-bit integer data.

And thirdly, for the rectangles carrying the R labels in each drawing, a Register (Register) is shown, and is used for data to be output to the next module or unit, so that the sequential execution time sequence of each module or unit of the data operation device is ensured.

(IV) for the ladder with "M" designation carried in each drawing, represented is a selector for gating one line out from at least two lines of inputs.

The first embodiment is as follows:

fig. 3 shows a schematic structural diagram of a first data operation device provided in an embodiment of the present application, where the data operation device includes a data acquisition module 31, a data alignment module 32 connected to the data acquisition module, a target operation module 33 and an index operation module 34 connected to the data alignment module 32, and an operation result output module 35 connected to both the target operation module 33 and the index operation module 34 and capable of acquiring data output by the two modules. Wherein:

and the data acquisition module 31 is used for acquiring data to be operated.

In the embodiment of the present application, the data obtaining module may obtain the data to be operated from other modules in the data operation device or from the outside of the data operation device. The data to be computed may include floating point data and/or fixed point data that conform to a standard format. For example, half-precision floating-point data compliant with the IEEE754 standard may be included, or 16-bit integer data may be included. After acquiring the data to be operated, the data acquisition module 31 outputs the data to be operated to the data alignment module 32.

The data alignment module 32 is configured to, if the data to be operated includes two floating point data, compare exponent data of the two floating point data, determine a larger exponent data as a target exponent data, and generate two target mantissa data with aligned data bits; and for floating point data with smaller exponent data in the two floating point data, selecting target number bit high order data of mantissa data of the floating point data according to a difference value between the target exponent data and the exponent data of the floating point data, and generating target mantissa data after the floating point data is shifted and aligned, wherein the target number is equal to the difference value subtracted from the number of bits of the mantissa data of the floating point data.

The data alignment module 32 obtains the data to be operated output by the data obtaining module 31, and determines the data format of the data to be operated. If the data to be operated includes two floating point data, in order to facilitate subsequent operations, data alignment operation needs to be performed on the two floating point data with unfixed decimal point positions, so that the decimal point positions of the two floating point data are aligned, which is specifically embodied as mantissa data alignment. Specifically, one floating point data includes exponent data and mantissa data, and the exponent data is data stored in the exponent data segment shown in fig. 1 and is capable of representing an exponent value corresponding to the floating point number; the mantissa data is data stored in the fractional data field shown in fig. 1, and can represent a valid data value corresponding to floating point data.

Specifically, the data alignment module may compare the exponent data of two floating point data, determine the larger exponent data as target exponent data, that is, the exponent data after the floating point data are aligned, and output the target exponent data to the exponent operation module 34. And, according to the target exponent data and the mantissa data of the two floating point data, two target mantissa data with aligned data bits are generated, and the two target mantissa data are output to the target operation module 33.

Specifically, two target mantissa data of data alignment are generated, specifically, in two floating point data, the floating point data with the smaller exponent data is mantissa-aligned to the floating point data with the larger exponent data. That is, for floating point data having large exponent data, the mantissa data of the floating point data is directly used as target mantissa data, and for floating point data having small exponent data, the mantissa data is right-shifted to obtain target mantissa data aligned with the floating point data having large exponent data.

Generally, the right shift of the data is realized through a shift register, and in the embodiment of the present application, the data alignment module performs data bit selection through a selector to equivalently realize the right shift of the data. Specifically, for the floating point data corresponding to the smaller exponent data, the number of bits of the data bits to be currently selected, which is referred to as a target number, may be determined according to a difference between the target exponent data and the two exponent data, which are the smaller exponent data, and the number of bits of mantissa data of the floating point data. And then, extracting high-order data of a target number of bits from the mantissa data of the floating point data with smaller exponent data, and filling data bits at the tail of the floating point data, wherein the number of the filled data bits is equal to the difference, and the value of the filled data bits is 0, so that right shift of the mantissa data is realized, and the target mantissa data after the mantissa data is shifted and aligned is obtained. For example, let 16-bit mantissa data that needs to be right shifted: "0000000011111011", when the difference is 2, the target number is 16-2 to 14, and at this time, the 14-bit upper data "00000000111110" of the 16-bit mantissa data is selected, and the tail of the data is filled with 0 numbers (i.e., 20 numbers) equal to the difference 2, thereby obtaining the target mantissa data "0000000011111000" corresponding to the mantissa data. The method for selecting the data bit realizes the right shift of the data, can save the operation resources, improve the hardware processing efficiency, efficiently realize the alignment of the data bit and improve the data operation efficiency compared with the prior mode of adopting a shift register.

Optionally, the two floating point data specifically include a first floating point data and a second floating point data, the first floating point data includes a first exponent data and a first mantissa data, the second floating point data includes a second exponent data and a second mantissa data, and the two target mantissa data includes a first target mantissa data and a second target mantissa data; the data alignment module comprises:

the index comparison unit is used for acquiring and comparing the first index data and the second index data, if the first index data is larger than the second index data, the first index data is determined as target index data, and the difference value of the first index data and the second index data is input to the first selection unit; if the first index data is smaller than the second index data, determining the second index data as target index data, and inputting the difference value of the second index data and the first index data to a second selection unit;

the first selection unit is used for acquiring first mantissa data; if the input of the difference is detected, selecting the target number bit high order data of the first mantissa data according to the difference, and generating the first target mantissa data after the first mantissa shift alignment, otherwise, directly taking the first mantissa data as the first target mantissa data;

the second selection unit is used for acquiring second mantissa data; and if the input of the difference is detected, selecting the target number bit high order data of the second mantissa data according to the difference, and generating the second target mantissa data after the second mantissa is shifted and aligned, otherwise, directly taking the second mantissa data as the second target mantissa data.

Referring to fig. 4, fig. 4 is a schematic diagram illustrating a second data operation apparatus according to an embodiment of the present disclosure. In fig. 4, the data alignment module specifically includes an index comparison unit, a first selection unit, and a second selection unit.

Specifically, after determining that the data to be operated includes first floating point data and second floating point data, the data alignment module inputs first exponent data of the first floating point data and second exponent data of the second floating point data to the exponent comparison unit for comparison. Meanwhile, the first mantissa data corresponding to the first floating point data is input to the first selection unit, and the second mantissa data corresponding to the second floating point data is input to the second selection unit.

If the comparison of the first exponent data and the second exponent data determines that the first exponent data is smaller than the second exponent data, the exponent comparing unit determines the second exponent data as target exponent data, outputs the target exponent data to the exponent operating module 34, and determines that the first mantissa data needs to be shifted to the right. At this time, a difference value obtained by subtracting the first exponent data from the second exponent data is input to the first selection unit to instruct the first selection unit to shift the first mantissa data to the right according to the difference value.

Conversely, if the exponent comparing unit determines that the first exponent data is greater than the second exponent data, the exponent comparing unit determines the first exponent data as target exponent data, outputs the target exponent data to the exponent operating module 34, and determines that the second mantissa data needs to be right-shifted. At this time, a difference value obtained by subtracting the second exponent data from the first exponent data is input to the second selection unit to instruct the second selection unit to shift the second mantissa data to the right according to the difference value.

Specifically, when the first exponent data is equal to the second exponent data, the data bits of the first floating point data and the second floating point data are aligned, and neither the first mantissa data nor the second mantissa data needs to be shifted, so that the data does not need to be output to the first selection unit or the second selection unit. In this case, the target exponent data (i.e., the first exponent data and the second exponent data) may be input to the exponent operation block 34.

After the first selection unit acquires the input first mantissa data, if the difference transmitted by the exponent comparison unit is detected, the first selection unit performs right shift on the first mantissa data according to the difference. Specifically, a target number is determined according to the difference and the number of bits of the first mantissa data, and then, after the target number bit high-order data of the first mantissa data is selected, 0 consistent with the difference number is added to the tail of the target number bit high-order data, so that the mantissa data after the first mantissa shift alignment is generated as the first target mantissa data. If the first selection unit does not acquire the data transmitted by the exponent comparison unit, it indicates that the first mantissa data does not need to be right-shifted, and the first mantissa data is directly used as first target mantissa data. After the first target mantissa data is determined, the first target mantissa data is transmitted to the target operation module 34.

Similarly, after the second selection unit acquires the input second mantissa data, if the difference transmitted by the exponent comparison unit is detected, the second selection unit performs right shift on the second mantissa data according to the difference. Specifically, a target number is determined according to the difference and the number of bits of the second mantissa data, and then, after the target number bit high-order data of the second mantissa data is selected, 0 corresponding to the difference number is added to the tail of the target number bit high-order data, thereby generating the mantissa data after the second mantissa shift alignment as the second target mantissa data. If the second selection unit does not acquire the data transmitted by the exponent comparison unit, it indicates that the first mantissa data does not need to be right-shifted, and the second mantissa data is directly used as second target mantissa data. After the second target mantissa data is determined, the second target mantissa data is transmitted to the target operation module 33.

In the embodiment of the application, the data alignment module is specifically refined, and through the mutual cooperation of the index comparison unit, the first selection unit and the second selection unit, the data alignment of two floating point data is accurately and orderly realized, and the accuracy of subsequent data operation is ensured.

And the target operation module 33 is configured to perform target operation on the two target mantissa data, and determine first mantissa result data.

The target operation module 33 can obtain two target mantissa data with aligned data bits, which are input by the data alignment module, and perform target operation on the two target mantissa data to obtain corresponding result data, which is referred to as first mantissa result data. After obtaining the first mantissa result data, the target operation module transmits the first mantissa result data to the operation result output module 35.

Specifically, the target operation in the embodiment of the present application may specifically be an operation that can be performed on the premise of data alignment of floating point data, except for a multiplication operation. Illustratively, the target operation may include an addition operation, a subtraction operation, an arithmetic shift operation, a logical shift operation, a comparison operation, a maximum value finding operation, a minimum value finding operation, and the like.

Further, after the two target mantissa data are subjected to target operation, carry is generated, and then carry identification is transmitted to the exponent operation module, as shown in fig. 4.

And an index operation module 34, configured to determine first index result data according to the target index data.

The index operation module acquires target index data transmitted by the data alignment module, and determines index data of final operation result data, namely first index result data, on the basis of the target index data.

Further, as shown in fig. 4, the exponent operation module 34 includes an exponent carry unit, and if the exponent operation module obtains the carry flag transmitted by the target operation module, 1 is added to the target exponent data through the exponent carry unit to obtain the first exponent result data. And if the target operation module does not transmit the carry identification to the target operation module, directly taking the target index data as the first index result data.

After obtaining the first exponent result data, the exponent operation module transmits the first exponent result data to the operation result output module 35.

The operation result output module 35 is configured to output operation result data, where the operation result data includes first operation result data determined according to the first mantissa result data and the first exponent result data.

The operation result output module can specifically obtain first exponent result data transmitted by the exponent operation module and first mantissa result data transmitted by the target operation module. According to the first exponent result and the first mantissa data, first operation result data can be obtained through combination, and then the first operation result data is used as operation result data and is output to other devices or other modules of the device to be processed or stored in the next step.

Further, as shown in fig. 4, the transportation result output module includes a saturation unit, and the saturation unit is specifically configured to output the first mantissa result data after performing data truncation according to a required data output bit number (for example, for floating point data, the output bit number may be 40 bits, and for fixed point data, the output bit number may be 16 bits). The method can be further used for saturating the first mantissa result data to the maximum value or the minimum value when the data overflow of the first mantissa result data is detected, so as to prevent the operation result data from being output wrongly.

Optionally, the data alignment module 32 is further configured to, if the data to be operated includes fixed-point data, directly input the fixed-point data to the target operation module;

correspondingly, the target operation module is also used for performing target operation according to the fixed point data and determining second operation result data;

correspondingly, in the operation result output module, the operation result data includes the second operation result data.

In this embodiment of the application, the data to be calculated may further include fixed point data. For the fixed point data, since the position of the decimal point is fixed, the data alignment operation is not required, and therefore, when the fixed point data is acquired, the data alignment module 32 does not process the fixed point data, and directly transmits the fixed point data to the target operation module for operation. Correspondingly, the target operation module according to the embodiment of the present application may perform a target operation on fixed-point data in addition to floating-point data, and the result data obtained by performing the operation on the fixed-point data is referred to as second operation result data. Correspondingly, in the operation result output module, the output operation result data may include the second operation result data.

In the embodiment of the application, the data to be operated is flexibly processed by the data alignment module, the target operation module and the operation result output module, so that the data operation device can be used for operating floating-point data and accurately operating fixed-point data, namely, the operation of two data types is flexibly realized by one device, and each module of the device can be flexibly multiplexed, thereby reducing the hardware cost.

Optionally, the data operation device further includes a multiplication module, configured to, if two data to be subjected to multiplication are obtained, perform multiplication on the two data to be subjected to multiplication to obtain multiplication result data;

correspondingly, the data acquisition module is connected with the multiplication module and is used for acquiring data to be operated from the multiplication module, wherein the data to be operated comprises the multiplication result data.

As shown in fig. 5, the data operation apparatus in the embodiment of the present application further includes a multiplication module 36 connected to the data acquisition module. Generally, no matter the multiplication operation of fixed point data or the multiplication operation of floating point data, it is not necessary to perform data alignment in advance, so in the embodiment of the present application, if the data operation device acquires two data to be subjected to multiplication, the two data may be directly input to the multiplication module first to perform multiplication, so as to obtain corresponding multiplication result data. And then, if further target operation is needed, the multiplication result data is taken as data to be operated and transmitted to the data acquisition module so as to carry out subsequent processing of modules such as the data alignment module, the target operation module and the like. That is, in the embodiment of the present application, the data to be operated of the data obtaining module may come from the multiplication module, and the data to be operated including the multiplication result data may be obtained by obtaining the data from the multiplication module.

Further, the multiplication module specifically includes, as shown in fig. 6, three preprocessing modules, namely a preprocessing module 1, a preprocessing module 2, and a preprocessing module 3, an exponent adding unit, and a mantissa multiplying unit.

The preprocessing module 1, the preprocessing module 2, and the preprocessing module 3 can respectively obtain three input operands opmx1, opmx2, and opmx 3. Each operand may be, for example, 16-bit floating point data or fixed point data.

Firstly, inputting an operand into a corresponding preprocessing module, and if the operand is fixed-point data, directly outputting the operand to the next stage without processing the operand by the preprocessing module; and if the operation data is floating point data, the corresponding preprocessing module preprocesses the operand. Illustratively, the floating point data is 16-bit half-precision floating point data, then the preprocessing includes:

a1: obtaining the data of the exponent data section of the floating point data, subtracting the exponent offset value 15, and solving the binary complement of the data to obtain a 5-bit complement corresponding to the exponent data section as the exponent data;

a2: after extracting the data of the decimal data section of the floating point data, adding a hidden bit 1 and a sign bit to obtain an effective mantissa raw code corresponding to the floating point data; and determining a binary complement corresponding to the effective mantissa original code as mantissa data, wherein the number of bits of the binary complement is equal to 12 bits which are 1 (sign bit) +1 (implicit bit) +10 (decimal data segment number).

A3: the exponent data and mantissa data in the complement format described above are output (5+12 ═ 17 bits).

Then, for the operand opmx1, which is data that does not need to be multiplied, the processed data m1 is directly transmitted backward and then transmitted to the data obtaining module for subsequent target operation.

For operands opmx2 and opmx3, the operands opmx2 and opmx3 need to be multiplied, and specifically, when the operands are floating point data, the two 12-bit mantissa data processed by the preprocessing module 2 and the preprocessing module 3 are input to the mantissa multiplying unit to obtain a 24-bit mantissa multiplication result; inputting the two 5-bit exponential data obtained by the processing of the preprocessing module 2 and the preprocessing module 3 into an exponential adding unit to obtain a 6-bit exponential adding result; the result of the multiplication by the 24-bit mantissa and the result of the addition by the 6-bit exponent are combined, sign bit expansion is performed, and the result is expanded to 32-bit floating point data m2 and output. When the two operands are fixed point data, the two 16-bit fixed point data are directly input into the mantissa multiplication unit, and 32-bit fixed point data m2 is obtained and output.

In the embodiment of the application, because the multiplication operation module is further included before the data acquisition module, the multiplication operation without data to the data acquisition module can be preferentially executed in the data operation device, and then the target operation with data alignment is executed, so that unnecessary data alignment operation is reduced, the occupation of hardware resources is reduced, and the operation efficiency is improved.

Optionally, the data operation device further includes an accumulator, and correspondingly, the data obtaining module is connected to the accumulator and is configured to obtain data to be operated from the accumulator, where the data to be operated includes accumulated data stored in the accumulator;

correspondingly, the operation result output module is connected with the accumulator and is used for outputting the operation result data to the accumulator so that the accumulator updates the stored accumulated data.

In the embodiment of the present application, the data operation device further includes an accumulator 37, configured to accumulate and store the output operation result data to obtain accumulated data. And the accumulator is also connected with the data acquisition module, and accumulated data of the accumulator can be transmitted to the data acquisition module. Correspondingly, the data obtaining 1 module may obtain the data to be transported from the accumulator, where the data to be transported includes the accumulated data stored in the accumulator.

Specifically, as shown in fig. 7, after the accumulator 37 is connected to the operation result output module, when the operation result output module obtains the operation result data, the operation result data can be output to the accumulator, and the accumulator adds the current operation result data to the accumulated data of the accumulator to obtain the updated accumulated data and stores the updated accumulated data, so that the data acquisition module can acquire the data next time.

Further, the accumulator may be composed of a plurality of registers, thereby being capable of storing accumulated data having a large data amount. Illustratively, as shown in FIG. 8, the accumulator may be comprised of 4 registers c 1-c 4, each of which may store 10 bits of data, such that the accumulator may store 40 bits of accumulated data. In fig. 8, the data acquisition module has 3 data acquisition sources: the data m1 directly output by the multiplication module after preprocessing, the data m2 obtained by the multiplication module after preprocessing and multiplication, and the accumulated data m3 output by the accumulator.

In the embodiment of the application, the data operation device can realize the accumulative operation of data through the arrangement of the accumulator, so that less hardware resources can be applied to realize more complex operation, and the hardware cost is reduced.

Optionally, the data operation device further includes a normalization processing module connected to the operation result output module, and configured to normalize the first operation result data to obtain normalized result data.

As shown in fig. 9, the data arithmetic device according to the embodiment of the present invention further includes a normalization processing module 38 connected to the operation result output module 35, and the normalization processing module can normalize the first operation result data corresponding to the floating point data according to a preset standard format of the floating point data, obtain normalized processing data, that is, result data conforming to the standard format of the floating point data, and output the normalized processing data.

In the embodiment of the application, the first operation result data obtained by operating the floating point data can be normalized by the normalization processing module after being output from the operation result output module, so that the output of the operation result can be normalized, and the accuracy of the operation result is improved.

Optionally, the normalization processing module includes:

a leading 0 calculation sub-module 381, configured to obtain the first operation result data, and calculate the leading 0 number of the first operation result data;

an operation result data adjusting submodule 382, configured to adjust first result mantissa data and first result exponent data of the first operation result data according to the preamble 0 number, to obtain second mantissa result data and second exponent result data;

a normalized result data determining submodule 383, configured to obtain normalized result data according to the second mantissa result data and the second exponent result data.

The normalization processing module in the embodiment of the application specifically comprises a preamble 0 calculation submodule, an operation result data adjustment submodule and a normalization result data determination submodule.

And the leading 0 calculation submodule is used for acquiring the first operation result data output by the operation result output module and calculating the number of the high bits of the first operation result data which are continuously 0 from the high bits of the first operation result data, namely the leading 0 number.

The operation result data adjusting submodule may specifically adjust first mantissa result data and first exponent result data of the first operation result data according to the number of leading 0 transmitted by the leading 0 calculating submodule, and remove the leading 0 with high redundancy to obtain normalized second mantissa result data and second exponent result data, so that the subsequently obtained mantissa can standardly represent floating point data in the 1.M format. Specifically, according to the leading 0 quantity, left shifting is carried out on the first mantissa result data to obtain second mantissa result data; and subtracting the leading 0 quantity from the first exponential result data to obtain second exponential result data. Specifically, if the first operation result data is complement data, the first mantissa result data is left-removed of leading 0 of high-order redundancy, and then the complement to original code operation is performed to obtain second mantissa result data; the first exponent result data, after subtracting the leading 0 number, needs to be added with an exponent offset value (15 for 16-bit half precision floating point data).

And the normalized result data determining submodule adjusts the bit number of the second mantissa result data to be consistent with the exponent bit number specified by the standard format according to the second mantissa result data, the second mantissa result data and a preset floating point data standard format, adjusts the mantissa of the second mantissa data to be consistent with the mantissa bit number specified by the standard format, and then splices the sign bit of the first operation result data with the adjusted exponent data in the standard format and the mantissa data in the standard format to obtain the normalized result data.

By way of example and not limitation, as shown in fig. 10, the leading 0 computation submodule may be included in a computation unit z1, a computation unit z2, a computation unit z3, and an addition unit. If the first operation result data inputted to the normalization processing module is data having a bit width of 40, the data can be divided and the 16-bit upper data (data of 24 th to 39 th bits) can be inputted to the calculation unit z1 to perform the leading 0 calculation. If the number of leading 0 s calculated by the calculating unit z1 is less than 16, it indicates that the number of leading 0 s currently counted by the calculating unit z1 is the number of leading 0 s of the first operation result data, and the first operation result data is directly transmitted to the operation result data adjusting submodule by the adding unit. If the number of leading 0 s calculated by the calculating unit z1 is equal to 16, it indicates that the number of leading 0 s of the current first operation result data may exceed 16, at this time, the number 16 of leading 0 s counted by z1 is input to the adding unit, and the calculating unit z2 is instructed to continue calculating the next 16-bit data (data of the 8 th bit to the 23 th bit of the first operation result data). If the number of leading 0 s calculated by the calculating means z2 is less than 16, it means that the number of leading 0 s in the first arithmetic result data is less than 32, and at this time, the number of leading 0 s calculated by the calculating means z2 is input to the adding means, and is added to the number 16 of leading 0 s calculated by the calculating means z1, so that the number of leading 0 s in the first arithmetic result data can be obtained. If the number of leading 0 s calculated by the calculating unit z2 is equal to 16, it indicates that the number of leading 0 s in the first operation result data may be greater than 32, at this time, the number 16 of leading 0 s calculated by the calculating unit z2 is input to the adding unit, and the calculating unit z3 is instructed to continue to calculate the last 8-bit data (data from 0 th bit to 7 th bit in the first operation result data), and then the number of leading 0 s counted by the calculating unit z3 is input to the adding unit, and the adding unit calculates and adds the numbers of leading 0 s counted by the three calculating units z1, z2, and z3, so as to obtain the number of leading 0 s in the first operation result data, and the number of leading 0 s is input to the operation result data adjusting submodule. Illustratively, if the bit width of the first operation result data is 40, the maximum value of the leading 0 number is 40, and therefore, the leading 0 number can be represented by data with a bit width of 6. In the foregoing embodiment, the calculation efficiency of the number of leading 0 s can be improved by the stepwise coordination of three calculation units z1 to z 3.

Illustratively, the operation result data adjusting submodule may include a sign bit separating unit, a mantissa separating unit, a left shift unit, a complement converting unit, a carry control unit, a mantissa generating unit, an exponent generating unit, and an exponent first adjusting unit, as shown in fig. 10. Specifically, the operation result data adjusting submodule acquires first operation result data, and divides the sign bit, the first mantissa result data, and the first exponent result data of the first operation result data by the sign bit separating unit, the mantissa separating unit, and the exponent separating unit. The operation result data adjusting submodule can also obtain the quantity of leading 0 input by the leading 0 calculating submodule. Then, the index generating unit acquires first index result data obtained by separation of the index separating unit and subtracts the leading 0 quantity, and the obtained value is output to the index first adjusting unit; after the left shift unit obtains the leading 0 quantity, the first mantissa result data obtained from the mantissa separation unit is subjected to left shift operation, and then the first mantissa result data is input into the complement conversion unit to obtain the mantissa data in the original code format, and the carry required by the mantissa data in the original code format is input into the carry identifier through the carry control unit and the exponent first adjusting unit, so that the exponent first adjusting unit outputs accurate second mantissa result data. Meanwhile, the carried mantissa data is transmitted to a mantissa generating unit, the mantissa generating unit reserves implicit bit 1 and 10-bit effective mantissa data and rounding reserved bits grs (g: a protection bit I; r: a rounding bit; s: a paste bit), and second mantissa result data is obtained.

Illustratively, the normalized result data determination submodule, as shown in fig. 10, includes an exponent second adjustment unit, a carry control unit, a right shift unit, and a rounding unit, and adjusts the second mantissa result data and the second exponent result data to data in accordance with the standard format bit number by mutual adjustment control of these several units. And then splicing the sign bit of the first operation result data with the exponent data in the standard format and the mantissa data in the standard format after adjustment to obtain normalized result data.

In the embodiment of the application, after the leading 0 number is calculated by the leading 0 calculation submodule, the operation result data adjustment submodule can accurately adjust the first result mantissa data and the first result exponent data of the first operation result data according to the leading 0 number to obtain the second mantissa result data and the second mantissa result data, and the normalization result data is obtained according to the second mantissa result data and the second mantissa result data by the normalization result data determination submodule, so that the normalization of the operation result is accurately and orderly realized.

In the embodiment of the application, data to be operated are obtained through a data obtaining module, then, when the data to be operated comprise two floating point data, the exponent data of the two floating point data are compared through a data alignment module, the larger exponent data are determined to be target exponent data, and target mantissa data with aligned data bits corresponding to each floating point data are generated; then, performing target operation on the two target mantissa data through a target operation module to obtain first mantissa result data; and determining first exponent result data according to the target exponent data through the exponent operation module, so that the operation result data can be output according to the first mantissa result data and the first exponent result data through the operation result output module. Before target operation is carried out, two target mantissa data with aligned data bits corresponding to two floating point data can be generated through the data alignment module, so that the target operation can be accurately and efficiently completed; in addition, in the data alignment module, the floating point data corresponding to the smaller exponent data is specifically shifted and aligned by selecting the target number bit high order data of the mantissa data of the floating point data, so that compared with the existing shifting mode through a shift register, the method can save operation resources, improve hardware processing efficiency, efficiently realize data bit alignment, and further improve data operation efficiency.

Example two:

fig. 11 shows a schematic flow chart of a data operation method provided in an embodiment of the present application, where an execution subject of the data operation method may be an electronic device, which is detailed as follows:

in S1101, data to be operated on is acquired.

In S1102, if the data to be operated includes two floating point data, comparing exponent data of the two floating point data, determining a larger exponent data as a target exponent data, and generating two target mantissa data with aligned data bits; and for floating point data with smaller exponent data in the two floating point data, selecting target number bit high order data of mantissa data of the floating point data according to a difference value between the target exponent data and the exponent data of the floating point data, and generating target mantissa data after the floating point data is shifted and aligned, wherein the target number is equal to the difference value subtracted from the number of bits of the mantissa data of the floating point data.

In S1103, a target operation is performed on the two target mantissa data, and first mantissa result data is determined.

In S1104, first index result data is determined according to the target index data.

In S1105, operation result data is output, where the operation result data includes first operation result data determined according to the first mantissa result data and the first exponent result data.

Optionally, if the two floating point data include a first floating point data and a second floating point data, the first floating point data includes a first exponent data and a first mantissa data, the second floating point data includes a second exponent data and a second mantissa data, and the two target mantissa data include a first target mantissa data and a second target mantissa data; step S1102 specifically includes:

acquiring and comparing the first index data and the second index data, if the first index data is smaller than the second index data, determining the second index data as target index data, and inputting a difference value between the second index data and the first index data to a first selection unit; if the first index data is larger than the second index data, determining the first index data as target index data, and inputting the difference value of the first index data and the second index data to a second selection unit;

the first selection unit realizes that: acquiring first mantissa data; if the input of the difference is detected, selecting the target number bit high order data of the first mantissa data according to the difference, and generating the first target mantissa data after the first mantissa shift alignment, otherwise, directly taking the first mantissa data as the first target mantissa data;

the second selection unit is used for realizing that: acquiring second mantissa data; and if the input of the difference is detected, selecting the target number bit high order data of the second mantissa data according to the difference, and generating the second target mantissa data after the second mantissa is shifted and aligned, otherwise, directly taking the second mantissa data as the second target mantissa data.

Optionally, the step S1102 further includes:

if the data to be operated comprises fixed point data, directly inputting the fixed point data to a target operation module;

correspondingly, the step S1103 further includes:

performing target operation according to the fixed point data, and determining second operation result data;

correspondingly, in step S1105, a target operation is performed according to the fixed point data, and second operation result data is determined.

Optionally, before the step S1101, the method further includes:

if two data to be subjected to multiplication operation are obtained, the two data to be subjected to multiplication operation are subjected to multiplication operation to obtain multiplication result data;

correspondingly, the step S1101 includes:

and acquiring data to be operated from a multiplication operation module, wherein the data to be operated comprises the multiplication result data.

Optionally, after the step S1105, the method further includes:

and normalizing the first operation result data to obtain normalized result data.

Optionally, the normalizing the first operation result data to obtain normalized result data includes:

acquiring the first operation result data, and calculating the leading 0 quantity of the first operation result data;

adjusting first result mantissa data and first result exponent data of the first operation result data according to the preamble 0 number to obtain second mantissa result data and second exponent result data;

and obtaining normalized result data according to the second mantissa result data and the second exponent result data.

It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application. In addition, each step of the embodiments of the present application is a step executed by each unit or module of the first embodiment, and please refer to the related description of the first embodiment for a detailed execution process, which is not described herein again.

Example three:

fig. 12 is a schematic diagram of an electronic device provided in an embodiment of the present application. As shown in fig. 12, the electronic apparatus 12 of this embodiment includes: a processor 120, a memory 121, and a computer program 122, such as a data computation program, stored in the memory 121 and executable on the processor 120. The processor 120 includes a data operation device 123, and when the processor 120 executes the computer program 122, the data operation device 123 implements functions of modules/units in the above-described embodiments of the apparatus, such as the functions of the data acquisition module 31 to the operation result output module 35 shown in fig. 3. Alternatively, when the processor 120 runs the computer program 122 through the data operation device 123, the steps in the above-described embodiments of the data operation method, for example, steps S1101 to S1105 shown in fig. 11, are implemented.

Illustratively, the computer program 122 may be partitioned into one or more modules/units that are stored in the memory 121 and executed by the processor 120 to accomplish the present application. The one or more modules/units may be a series of computer program instruction segments capable of performing specific functions, which are used to describe the execution of the computer program 122 in the electronic device 12.

The electronic device 12 may be a desktop computer, a notebook, a palm top computer, a cloud server, or other computing devices. The electronic device may include, but is not limited to, a processor 120, a memory 121. Those skilled in the art will appreciate that fig. 12 is merely an example of electronic device 12 and does not constitute a limitation of electronic device 12 and may include more or fewer components than shown, or some components may be combined, or different components, e.g., the electronic device may also include input-output devices, network access devices, buses, etc.

The Processor 120 may be a Central Processing Unit (CPU), other general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic device, discrete hardware component, or the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.

The storage 121 may be an internal storage unit of the electronic device 12, such as a hard disk or a memory of the electronic device 12. The memory 121 may also be an external storage device of the electronic device 12, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), and the like, which are provided on the electronic device 12. Further, the memory 121 may also include both an internal storage unit and an external storage device of the electronic device 12. The memory 121 is used for storing the computer program and other programs and data required by the electronic device. The memory 121 may also be used to temporarily store data that has been output or is to be output.

It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-mentioned division of the functional units and modules is illustrated, and in practical applications, the above-mentioned function distribution may be performed by different functional units and modules according to needs, that is, the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-mentioned functions. Each functional unit and module in the embodiments may be integrated in one processing unit, or each unit may exist alone physically, or two or more units are integrated in one unit, and the integrated unit may be implemented in a form of hardware, or in a form of software functional unit. In addition, specific names of the functional units and modules are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working processes of the units and modules in the system may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and reference may be made to the related descriptions of other embodiments for parts that are not described or illustrated in a certain embodiment.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus/electronic device and method may be implemented in other ways. For example, the above-described apparatus/electronic device embodiments are merely illustrative, and for example, the division of the modules or units is only one logical division, and there may be other divisions when actually implemented, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.

The integrated modules/units, if implemented in the form of software functional units and sold or used as separate products, may be stored in a computer readable storage medium. Based on such understanding, all or part of the flow in the method of the embodiments described above can be realized by a computer program, which can be stored in a computer-readable storage medium and can realize the steps of the embodiments of the methods described above when the computer program is executed by a processor. Wherein the computer program comprises computer program code, which may be in the form of source code, object code, an executable file or some intermediate form, etc. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording medium, usb disk, removable hard disk, magnetic disk, optical disk, computer Memory, Read-Only Memory (ROM), Random Access Memory (RAM), electrical carrier wave signals, telecommunications signals, software distribution medium, and the like. It should be noted that the computer readable medium may contain content that is subject to appropriate increase or decrease as required by legislation and patent practice in jurisdictions, for example, in some jurisdictions, computer readable media does not include electrical carrier signals and telecommunications signals as is required by legislation and patent practice.

The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.

Claims

1. A data operation device, comprising:

the data acquisition module is used for acquiring data to be operated;

the data alignment module is used for comparing the exponent data of the two floating point data if the data to be operated comprises the two floating point data, determining the larger exponent data as target exponent data, and generating two target mantissa data with aligned data bits; for floating point data with smaller exponent data in the two floating point data, selecting target number bit high order data of mantissa data of the floating point data according to a difference value between the target exponent data and the exponent data of the floating point data, and generating target mantissa data after the floating point data is shifted and aligned, wherein the target number is equal to the difference value subtracted from the number of bits of the mantissa data of the floating point data;

2. The data arithmetic device of claim 1, wherein if the two floating point data include a first floating point data and a second floating point data, the first floating point data includes a first exponent data and a first mantissa data, the second floating point data includes a second exponent data and a second mantissa data, and the two target mantissa data includes a first target mantissa data and a second target mantissa data; the data alignment module comprises:

the index comparison unit is used for acquiring and comparing the first index data and the second index data, if the first index data is smaller than the second index data, the second index data is determined as target index data, and the difference value between the second index data and the first index data is input to the first selection unit; if the first index data is larger than the second index data, determining the first index data as target index data, and inputting the difference value of the first index data and the second index data to a second selection unit;

3. The data operation device of claim 1, wherein the data alignment module is further configured to directly input fixed-point data to the target operation module if the data to be operated includes the fixed-point data;

the target operation module is also used for performing target operation according to the fixed point data and determining second operation result data;

in the operation result output module, the operation result data includes the second operation result data.

4. The data operation device according to claim 1, wherein the data operation device further includes a multiplication module, configured to, if two data to be subjected to multiplication are obtained, perform multiplication on the two data to be subjected to multiplication to obtain multiplication result data;

the data acquisition module is connected with the multiplication module and used for acquiring data to be operated from the multiplication module, wherein the data to be operated comprises multiplication result data.

5. The data arithmetic device of claim 1, wherein the data arithmetic device further comprises an accumulator, and the data obtaining module is connected to the accumulator and is configured to obtain data to be operated from the accumulator, where the data to be operated includes accumulated data stored in the accumulator;

the operation result output module is connected with the accumulator and used for outputting the operation result data to the accumulator so as to update the stored accumulated data by the accumulator.

6. The data arithmetic device according to any one of claims 1 to 5, further comprising a normalization processing module connected to the arithmetic result output module, for normalizing the first arithmetic result data to obtain normalized result data.

7. The data operation device of claim 6, wherein the normalization processing module comprises:

a leading 0 calculation submodule, configured to obtain the first operation result data, and calculate the leading 0 number of the first operation result data;

an operation result data adjusting submodule, configured to adjust first result mantissa data and first result exponent data of the first operation result data according to the number of leading 0 s, to obtain second mantissa result data and second exponent result data;

and the normalized result data determining submodule is used for obtaining normalized result data according to the second mantissa result data and the second exponent result data.

8. A method of data manipulation, comprising:

acquiring data to be operated;

if the data to be operated comprises two floating point data, comparing the exponent data of the two floating point data, determining the larger exponent data as target exponent data, and generating two target mantissa data with aligned data bits; for floating point data with smaller exponent data in the two floating point data, selecting target number bit high order data of mantissa data of the floating point data according to a difference value between the target exponent data and the exponent data of the floating point data, and generating target mantissa data after the floating point data is shifted and aligned, wherein the target number is equal to the difference value subtracted from the number of bits of the mantissa data of the floating point data;

determining first index result data according to the target index data;

9. An electronic device, characterized in that it comprises a data arithmetic device according to any one of claims 1 to 7.

10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, causes an electronic device to carry out the steps of the data calculation method according to claim 8.