CN113590209B - Chip starting control method, chip and electronic equipment - Google Patents
Chip starting control method, chip and electronic equipment Download PDFInfo
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- CN113590209B CN113590209B CN202111147035.4A CN202111147035A CN113590209B CN 113590209 B CN113590209 B CN 113590209B CN 202111147035 A CN202111147035 A CN 202111147035A CN 113590209 B CN113590209 B CN 113590209B
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
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- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
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Abstract
The invention provides a chip starting control method, a chip and electronic equipment, wherein the chip comprises a CPU (central processing unit), a starting management module, a first OTP (one time programmable) module, a second OTP module, a one-time memory and an erasable memory; the first OTP module is provided with the write permission of the executable code of the one-time memory, and the second OTP module is provided with the write permission of the executable code of the one-time memory and the erasable memory; the starting management module is used for reading data in the first OTP module and the second OTP module according to priority, switching a starting address of the CPU in a bit-determining mode, and finally selecting the starting address of the CPU as an address of the one-time memory. The invention can select to start the firmware from the one-time memory or start the firmware from the erasable memory, and the one-time memory can close the start of the erasable memory, thereby ensuring the normal start of the chip.
Description
Technical Field
The present disclosure relates to the field of integrated circuit chip design technologies, and in particular, to a chip start control method, a chip, and an electronic device.
Background
The start-up design of the chip is always one of the key points of the chip design. Many devices are scrapped and failed, and a large part of reasons are that the chips fail due to the fact that the chips cannot be started, and finally the whole device is scrapped. When the chip is started, some initialization operations and configuration management need to be performed inside the chip. The chip boot code, also called firmware, is usually produced by packaging together with the chip, and is used to complete the most basic tasks of the chip, such as initialization, function startup, and booting operation of business software.
The conventional chip is usually started from the initial address of the disposable memory, and after the validity verification of the firmware in the erasable memory is completed in the software code of the disposable memory, the chip jumps to the software firmware of the erasable memory to run. Since the firmware in the one-time memory cannot be modified after the chip is taped, if the firmware stored in the one-time memory has a problem, the SOC may not be started normally. However, the direct starting from the erasable memory will affect the security of the chip, which easily results in the chip not being started normally.
Disclosure of Invention
In view of this, the embodiments of the present disclosure provide a chip start control method, a chip, and an electronic device, in which the invention can select to start firmware from a one-time memory or start firmware from an erasable memory, and the one-time memory can shut off the start of the erasable memory, thereby ensuring normal start of the chip.
In order to achieve the above purpose, the invention provides the following technical scheme:
a chip start-up control method applied to a control module of the chip, the control module including a start-up management module for controlling an OTP module including a first OTP module and a second OTP module, the method comprising:
configuring the first OTP module and the second OTP module according to priority;
configuring executable code writing authority of a one-time memory in the first OTP module, and configuring executable code writing authority of the one-time memory and an erasable memory in the second OTP module;
the start management module firstly reads data in the first OTP module, if bit data in the first OTP module is not empty, a start address is selected according to the configuration of the first OTP module, and if not, the start address is selected according to the configuration of the second OTP module;
when the starting management module selects a starting address, the starting management module switches the starting address of the chip CPU in a bit-determining mode, and when the OTP module is fully written, the starting address of the CPU is designated as the address of a one-time memory or the address of an erasable memory;
the bit-wise determination mode comprises the following steps: the starting address of the CPU is determined by writing a bit into the OTP module in sequence, the CPU starting address is judged once by writing a bit every time, the starting management module switches the CPU starting address every time a bit is written, and the CPU starting address is designated as the address of the disposable memory or the address of the erasable memory when the OTP module is full.
Further, in the bit-wise determination mode, the start management module switches the CPU start address according to the parity of the total number of bits after 1 is written each time.
Further, the bit-wise determination further includes: when one bit written in sequence is judged once, when the number of the total number of the bits written in 1 is an odd number, the CPU starting address is judged as a one-time memory address, and when the number of the total number of the bits written in 1 is an even number, the CPU starting address is judged as an erasable memory address.
Further, the bit-wise determination further includes: when one bit written in sequence is judged once, when the number of the total number of the bits written in 1 is an odd number, the CPU starting address is judged as an erasable memory address, and when the number of the total number of the bits written in 1 is an even number, the CPU starting address is judged as a one-time memory address.
Further, the method further includes configuring the boot management module, and when all bit data in the second OTP module is empty, setting a default boot address of the CPU as an address of the erasable memory or an address of the one-time memory.
The invention also provides a chip, which comprises a control module and a storage module, wherein the control module comprises a CPU and a starting management module, and the storage module comprises a first OTP module, a second OTP module, a one-time memory and an erasable memory;
executable code writing permission of a one-time memory is configured in the first OTP module, and executable code writing permission of the one-time memory and an erasable memory is configured in the second OTP module;
the starting management module is used for reading data in the first OTP module and the second OTP module according to priority, switching a starting address of the CPU in a bit-determining mode, and finally selecting the starting address of the CPU as an address of a one-time memory or an address of an erasable memory;
when the start management module reads the data in the first OTP module and the second OTP module according to priority, the data in the first OTP module is read first, if bit data in the first OTP module is not empty, a start address is selected according to the configuration of the first OTP module, if not, the data in the second OTP module is read, and the start address is selected according to the configuration of the second OTP module.
Furthermore, the control module further comprises an address management unit, wherein the address management unit is used for configuring the starting address of the CPU, and the starting management module controls and executes the selection of the starting address of the CPU.
Further, the control module further includes a first write control module and a second write control module, where the first write control module is configured to control write permission of the first OTP module, and only allows executable code in the one-time memory to perform a write operation on the first OTP module; the second write control module is used for controlling the write permission of the second OTP module and allowing executable codes in the one-time memory and the erasable memory to write the second OTP module.
The invention also provides electronic equipment comprising the chip.
The chip starting control method can configure the chip to start from the disposable memory or the erasable memory, and can finally permanently close the writing of the erasable memory, and has the configuration advantages of flexibility and safety.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings needed to be used in the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present disclosure, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic diagram of a chip structure according to an embodiment of the disclosure;
fig. 2 is a flowchart of a chip start control method according to an embodiment of the disclosure.
Detailed Description
The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.
The embodiments of the present disclosure are described below with specific examples, and other advantages and effects of the present disclosure will be readily apparent to those skilled in the art from the disclosure in the specification. It is to be understood that the described embodiments are merely illustrative of some, and not restrictive, of the embodiments of the disclosure. The disclosure may be embodied or carried out in various other specific embodiments, and various modifications and changes may be made in the details within the description without departing from the spirit of the disclosure. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure.
It is noted that various aspects of the embodiments are described below within the scope of the appended claims. It should be apparent that the aspects described herein may be embodied in a wide variety of forms and that any specific structure and/or function described herein is merely illustrative. Based on the disclosure, one skilled in the art should appreciate that one aspect described herein may be implemented independently of any other aspects and that two or more of these aspects may be combined in various ways. For example, an apparatus may be implemented and/or a method practiced using any number of the aspects set forth herein. Additionally, such an apparatus may be implemented and/or such a method may be practiced using other structure and/or functionality in addition to one or more of the aspects set forth herein.
It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present disclosure, and the drawings only show the components related to the present disclosure rather than the number, shape and size of the components in actual implementation, and the type, amount and ratio of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
In addition, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the aspects may be practiced without these specific details.
As shown in fig. 1, an embodiment of the present disclosure provides a chip including a CPU, an address management unit, a one-time memory, an erasable memory, a first write control module, a second write control module, a first OTP module, a second OTP module, and a boot management module.
The CPU starting address can be the address of a one-time memory or the address of an erasable memory. The CPU starting address is selected by the address management unit and is finally controlled by the starting management module.
The first OTP module and the second OTP module are configured according to priority, when the chip is started, the start management module firstly reads data in the first OTP module, and if the data in the first OTP module is not empty, the start address is selected according to the configuration of the first OTP module; if the first OTP module is empty, a chip enable address is selected according to a configuration of the second OTP.
Both writing of the first OTP module and the second OTP module is controlled by the write control module: the first write control module controls the write permission of the first OTP module and only allows executable codes in the one-time memory to write the first OTP module; the second write control module controls write permission of the second OTP module, and the second write control module allows executable codes on the one-time memory and the erasable memory to write to the second OTP module.
The method for the boot management module to read the data in the two OTP modules to determine to select the one-time memory or the erasable memory for booting is as follows: the start address of the CPU can be determined to be a one-time memory or an erasable memory by sequentially writing one bit into the OTP. The starting management module judges one bit written in each time by a bit-based determination method, one bit is added in each time, the starting management module switches the CPU starting address of the address management unit when one bit is added in each time, and the CPU starting address appointed by the starting management module is ensured to be the address of the one-time memory or the address of the erasable memory when the OTP module is fully written finally.
Next, referring to fig. 2, the chip start control method of the present invention will be described in further detail.
When the chip is started, the starting management module firstly reads data in the first OTP module, when bit data in the first OTP module is not empty, the written bits are read, and the starting address of the CPU set by the address management unit is determined to be a one-time memory or an erasable memory according to the written bits.
When all bits in the first OTP module are empty (0), the startup management module reads all written bits in the second OTP module and determines the startup address of the CPU to be a one-time memory or an erasable memory according to the written bits. The bit-based determination method comprises the following steps: the starting management module switches the CPU starting address every time one bit is written, and specifies the CPU starting address as the address of a one-time memory or the address of an erasable memory repeatedly until the OTP module is full.
According to a preferred embodiment of the present disclosure, the start management module switches the CPU start address according to the parity of the number of total bits after 1 is written each time. Specifically, when only one bit of the second OTP module is written with 1, the CPU start address is determined as the one-time memory address (or the erasable memory address), and when two bits of the second OTP module are written with 1, the CPU start address is determined as the erasable memory address (or the one-time memory address) … … repeatedly till the second OTP module is full, and then the start management module configures the CPU start address to be determined as the one-time memory address or the erasable memory address. When all bits in the second OTP module are empty, the boot management module defaults the boot address of the CPU to the address of the erasable memory (or the address of the one-time memory).
When all bits of the first OTP module are empty, the start management module is configured to follow the second OTP module, when one bit of the first OTP module is written with 1, the start management module configures the CPU start address as an erasable memory address, the operation is repeated like the second OTP module, the CPU start address is switched, and when the first OTP module is fully written, the CPU start address is designated as the address of the one-time memory or the address of the erasable memory.
The present disclosure is further illustrated by the following specific examples.
Example 1
A general-purpose digital chip, preferably a microcontroller chip or a processor chip, of the present embodiment has a CPU, an address management unit, a one-time memory, an erasable memory, a first write control module, a second write control module, a first OTP module, a second OTP module, and a start management module inside.
When the chip is started, the starting management module firstly reads data in the first OTP module, when bit data in the first OTP module is not empty, the written bits are read, and the starting address of the CPU set by the address management unit is determined to be a one-time memory or an erasable memory according to the written bits. For example, it writes 1 bit, and the boot management module determines it as an erasable memory boot. The starting management module sets a starting address of the address management unit and configures the starting address of the CPU into an erasable memory; if all the bits of the first OTP module are full, and the total number of bits is even, the start management module sets the start address of the CPU as the address of the one-time memory.
When all bits in the first OTP module are empty (0), the startup management module reads all written bits in the second OTP module and determines the startup address of the CPU to be a one-time memory or an erasable memory according to the written bits. When all bits in the second OTP module are empty, the starting management module defaults that the starting address of the CPU is the address of the erasable memory, and when only one bit in the second OTP module is written into 1, the starting address of the CPU is judged to be the address of the one-time memory; and by parity judgment, when the number of written bits is odd, the starting management module judges that the starting address is a one-time memory address, when the number of written bits is even, the starting address is an erasable memory address, when the second OTP module is fully written, the starting management module is provided with odd bits, and the starting management module configures the CPU starting address to judge that the starting address is the one-time memory address.
The writing authority of a second OTP module in the chip is controlled by a second writing control module, which allows codes running in the one-time memory and codes in the erasable memory to write data into the second OTP module; the writing authority of the first OTP module in the chip is controlled by a first writing control module, which only allows codes running in the one-time memory to write the first OTP module.
In the chip design, the address management unit jointly determined by the two OTP modules and the start management module can control the start address of the chip to be a one-time memory or an erasable memory, and a user can finally fix the address management unit to be the start of the one-time memory or the erasable memory by writing the OTP. The chip supports boot from a one-time memory or an erasable memory, and reduces the risk caused by firmware errors in the one-time memory. And because the two OTP modules have different authorities and have priority configurations, the direct start of the erasable memory can be started or disabled through the OTP module configuration, the direct start function of the erasable memory can be controlled to be closed by the one-time memory program, the erasable memory cannot be started, and the one-time memory can be started again. Meanwhile, if the firmware of the disposable memory has partial problems, the erasable memory can be configured to permanently close the direct start of the erasable memory, so that the flexibility and the safety are higher.
The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present disclosure should be covered within the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.
Claims (9)
1. A chip start-up control method applied to a control module of the chip, the control module including a start-up management module for controlling an OTP module, wherein the OTP module includes a first OTP module and a second OTP module, the method comprising:
configuring the first OTP module and the second OTP module according to priority;
configuring executable code writing authority of a one-time memory in the first OTP module, and configuring executable code writing authority of the one-time memory and an erasable memory in the second OTP module;
the start management module firstly reads data in the first OTP module, if bit data in the first OTP module is not empty, a start address is selected according to the configuration of the first OTP module, and if not, the start address is selected according to the configuration of the second OTP module;
when the starting management module selects a starting address, the starting address of the chip CPU is switched in a bit-determining mode, and when the OTP module is fully written, the starting address of the CPU is designated as the address of a one-time memory or the address of an erasable memory;
the bit-wise determination mode comprises the following steps: the starting address of the CPU is determined by writing a bit into the OTP module in sequence, the CPU starting address is judged once by writing a bit every time, the starting management module switches the CPU starting address every time a bit is written, and the CPU starting address is designated as the address of the disposable memory or the address of the erasable memory when the OTP module is full.
2. The chip start-up control method according to claim 1, wherein in the bit-wise determination mode, the start-up management module switches the CPU start-up address according to parity of a total number of bits after 1 is written each time.
3. The chip start-up control method according to claim 2, wherein the bit-wise determination further comprises: when one bit written in sequence is judged once, when the number of the total number of the bits written in 1 is an odd number, the CPU starting address is judged as a one-time memory address, and when the number of the total number of the bits written in 1 is an even number, the CPU starting address is judged as an erasable memory address.
4. The chip start-up control method according to claim 2, wherein the bit-wise determination further comprises: when one bit written in sequence is judged once, when the number of the total number of the bits written in 1 is an odd number, the CPU starting address is judged as an erasable memory address, and when the number of the total number of the bits written in 1 is an even number, the CPU starting address is judged as a one-time memory address.
5. The chip start-up control method according to any one of claims 1 to 4, further comprising configuring the start-up management module, and when all bit data in the second OTP module is empty, setting a start-up address of a default CPU as an address of an erasable memory or an address of a one-time memory.
6. The chip is characterized by comprising a control module and a storage module, wherein the control module comprises a CPU and a starting management module, and the storage module comprises a first OTP module, a second OTP module, a one-time memory and an erasable memory;
executable code writing permission of a one-time memory is configured in the first OTP module, and executable code writing permission of the one-time memory and an erasable memory is configured in the second OTP module;
the starting management module is used for reading data in the first OTP module and the second OTP module according to priority, switching a starting address of the CPU in a bit-determining mode, and finally selecting the starting address of the CPU as an address of a one-time memory or an address of an erasable memory;
when the start management module reads the data in the first OTP module and the second OTP module according to priority, the data in the first OTP module is read firstly, if bit data in the first OTP module is not empty, a start address is selected according to the configuration of the first OTP module, if not, the data in the second OTP module is read, and the start address is selected according to the configuration of the second OTP module;
wherein the bit-wise determination comprises: the starting address of the CPU is determined by writing a bit into the first OTP module and the second OTP module in sequence, the CPU starting address is switched by the starting management module when the bit written in each time is judged once, and when the bit written in each time is judged once, the CPU starting address is designated as the address of the one-time memory or the address of the erasable memory repeatedly until the first OTP module and the second OTP module are full.
7. The chip of claim 6, wherein the control module further comprises an address management unit, and the address management unit is configured to configure a boot address of the CPU, and the boot management module controls the selection of the boot address of the CPU.
8. The chip according to claim 7, wherein the control module further includes a first write control module and a second write control module, the first write control module is configured to control write permission of the first OTP module, and only allow the first OTP module to be written by executable code in the one-time memory; the second write control module is used for controlling the write permission of the second OTP module and allowing executable codes in the one-time memory and the erasable memory to write the second OTP module.
9. An electronic device, characterized in that it comprises a chip according to any one of claims 6 to 8.
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| TWI262507B (en) * | 2005-05-19 | 2006-09-21 | Ememory Technology Inc | Method for accessing memory |
| KR102398205B1 (en) * | 2017-06-12 | 2022-05-16 | 삼성전자주식회사 | Memory device comprising otp memory cell and program method thereof |
| CN107908359B (en) * | 2017-11-03 | 2020-12-29 | 清华大学深圳研究生院 | OTP memory, data writing and reading method thereof and security chip |
| CN112083961B (en) * | 2020-08-05 | 2022-01-14 | 北京智芯微电子科技有限公司 | Embedded chip boot loading method |
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