CN113555372B - Partition filling unit and multi-voltage-domain low-power-consumption chip - Google Patents
Partition filling unit and multi-voltage-domain low-power-consumption chip Download PDFInfo
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- CN113555372B CN113555372B CN202110744849.XA CN202110744849A CN113555372B CN 113555372 B CN113555372 B CN 113555372B CN 202110744849 A CN202110744849 A CN 202110744849A CN 113555372 B CN113555372 B CN 113555372B
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- 238000005192 partition Methods 0.000 title claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 70
- 238000002955 isolation Methods 0.000 claims abstract description 49
- 239000002184 metal Substances 0.000 claims abstract description 25
- 238000009792 diffusion process Methods 0.000 claims abstract description 23
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 6
- 239000000945 filler Substances 0.000 claims description 6
- 238000000638 solvent extraction Methods 0.000 claims description 3
- 230000000903 blocking effect Effects 0.000 claims 1
- 230000005611 electricity Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000012938 design process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a partition filling unit and a multi-voltage-domain low-power-consumption chip, wherein the partition filling unit comprises: the substrate layer, the polycrystalline silicon layer, the diffusion layer and the metal layer are sequentially stacked; the diffusion layer comprises an N + diffusion layer and a P + diffusion layer; the substrate layer is divided into a first substrate and a second substrate, and when the dividing filling units are arranged on the left side and the right side of the isolation units, the substrates of the isolation units are isolated. By implementing the embodiment of the invention, the flexibility of the arrangement of the isolation unit can be improved.
Description
Technical Field
The invention belongs to the technical field of chip design, and particularly relates to a partition filling unit and a multi-voltage-domain low-power-consumption chip.
Background
With the higher and higher integration level of chips, more and more abundant functions and the practical requirements of mobile markets, the chip design with low power consumption is more and more advocated. Under different application scenes of a product, if some scenes are not frequently used, the power supply of the scenes is expected to be cut off so as to save the electric quantity; some scenarios require operation at high voltages; some scenarios require operation at low voltages. This is mapped on the chip, which is equivalent to that some modules which do not need to work frequently are powered off when not working, so as to reduce power consumption; some high performance, high frequency modules require high voltage to be supplied; some low performance, low frequency modules require a low voltage to be supplied. Then, a multi-voltage domain low power consumption design is needed to implement the design, as shown in fig. 1, in the multi-voltage domain low power consumption design scheme, a power gating module, a power switch, an always on cell (i.e., a standard cell that always has power), and an isolation cell (i.e., an ISO cell); in the chip design process, when an ISO unit is placed, the place where the ISO unit is placed needs to have both a gated power and an always on power, and the physical and logical connections are required to be accurate, so that a power short circuit caused when a substrate is powered by multiple power sources is avoided, and a design violation is caused. Therefore, the placing position of the ISO unit has great limitation and lower flexibility.
Disclosure of Invention
The embodiment of the invention provides a partition filling unit and a multi-voltage-domain low-power-consumption chip, which can improve the flexibility of the arrangement of an isolation unit.
An embodiment of the present invention provides a partition filling unit, including: the substrate layer, the polycrystalline silicon layer, the diffusion layer and the metal layer are sequentially stacked; the diffusion layer comprises an N + diffusion layer and a P + diffusion layer; the substrate layer is divided into a first substrate and a second substrate, and when the dividing filling units are arranged on the left side and the right side of the isolation units, the substrates of the isolation units are isolated.
Further, the metal layer comprises a metal layer for VDD power supply, and the metal layer for VDD power supply is partitioned into a first metal layer and a second metal layer.
Further, the substrate layer is an N-well substrate.
Correspondingly, another embodiment of the invention provides a multi-voltage-domain low-power-consumption chip, which comprises a power gating module, a turn-off power module, a power switch, a standard unit for keeping power on all the time and a plurality of isolation units, and is characterized in that the left side and the right side of each isolation unit are respectively provided with one isolation filling unit.
The embodiment of the invention has the following beneficial effects:
the embodiment of the invention provides a partition filling unit and a multi-voltage-domain low-power-consumption chip, wherein the partition filling unit comprises a substrate layer, a polycrystalline silicon layer, a diffusion layer and a metal layer which are sequentially stacked; the diffusion layer comprises an N + diffusion layer and a P + diffusion layer; the substrate layer is divided into a first substrate and a second substrate, and when the separation filling units are arranged on the left side and the right side of the isolation unit, the substrates of the isolation unit are isolated. In the invention, after the substrate layer for separating the filling unit is separated into the first substrate and the second substrate which are separated from each other, the first substrate and the second substrate still have power rails for supplying power, thereby meeting the design requirements; when the partition filling units are arranged on the left side and the right side of the isolation unit, one substrate of the first partition filling unit positioned at one end of the left side of the isolation unit is connected with the substrate of the isolation unit, and the other substrate of the first partition filling unit is connected with the standard unit. One substrate of the second isolation filling unit positioned at one end of the right side of the isolation unit is connected with the substrate of the isolation unit, and the other substrate of the second isolation filling unit is connected with the other standard unit, so that the substrate of the isolation unit is isolated from the substrate of the standard unit, if the two standard units and the isolation unit are supplied with power by different power supplies, because the two substrates in the isolation filling unit are mutually separated, the power supplies of the substrates of the two standard units and the isolation unit are mutually independent, no influence is caused, and the power short circuit is avoided. By adopting the mode, the position of the isolation unit in the chip can be randomly placed without setting a specific position, the restriction of the arrangement position of the existing isolation unit is eliminated, and the flexibility of chip design is greatly improved.
Drawings
Fig. 1 is a schematic structural diagram of a multi-voltage-domain low-power chip in the prior art.
Fig. 2 is a chip layout for partitioning filler cells according to an embodiment of the present invention.
Fig. 3 is a chip layout of a filler unit according to an embodiment of the present invention.
Fig. 4 is a schematic layout diagram of partition filling units according to an embodiment of the present invention.
Fig. 5 is another chip layout for partitioning filler cells according to an embodiment of the present invention.
Description of reference numerals: the structure comprises a substrate layer 1, a polycrystalline silicon layer 2, a diffusion layer 3, a P + diffusion layer 4, an N + diffusion layer 5, a metal layer 6, a first substrate 7, a second substrate 8, a first metal layer 9, a second metal layer 10, a first partition filling unit 11, a second partition filling unit 12, an isolation unit 13, a first standard unit 14 and a second standard unit 15.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 2, an embodiment of the present invention provides a partition filling unit, including: the substrate layer 1, the polycrystalline silicon layer 2, the diffusion layer 3 and the metal layer 6 are sequentially stacked; the diffusion layer 3 includes a P + diffusion layer 4 and an N + diffusion layer 5; the substrate layer 1 is divided into a first substrate 7 and a second substrate 8, and when the dividing filling units are arranged at the left side and the right side of the isolation unit, the substrates of the isolation unit are isolated. Preferably, the substrate layer 1 is an N-well substrate layer.
Specifically, in an actual situation, a filler cell (filling cell) in a process selected by chip production is taken as a reference, as shown in fig. 3, but of course, the size of the filling cell can be flexibly selected according to the estimation of a back-end implementation engineer on the chip area, the substrate of the filling cell is disconnected, and the contact layer of the substrate is removed, so that the isolated filling cell shown in fig. 2 is formed. When the chip is laid out, the isolation filling units are arranged at the left side and the right side of the isolation unit (namely the two sides of the substrate of the isolation unit connected with the substrate of the other external logic units), and the substrate of the isolation unit is isolated.
As shown in fig. 4, after the substrate layer of the isolated filler unit is isolated into the first substrate 7 and the second substrate 8 which are separated from each other, the first substrate 7 and the second substrate 8 still have VDD power supplied by their own power rail (power rail) to meet the design requirement; after the partition filling units are arranged on the left side and the right side of the isolation unit, one substrate of the first partition filling unit 11 positioned at one end of the left side of the isolation unit is connected with the substrate of the isolation unit 13, and the other substrate of the first partition filling unit 11 is connected with the first standard unit 14. One substrate of the second partition filling unit 12 positioned at one end of the right side of the isolation unit 13 is connected with the substrate of the isolation unit 13, and the other substrate of the second partition filling unit 12 is connected with the second standard unit 15, so that the substrate of the isolation unit 13 is isolated from the substrates of the first standard unit 14 and the second standard unit 15, if the two standard units and the isolation unit 13 are supplied with power by different power supplies, because the two substrates in the partition filling unit are mutually separated, the power supplies of the substrates of the two standard units and the isolation unit 13 are mutually independent, no influence is caused, and the power short circuit is avoided. By adopting the mode, the position of the isolation unit 13 in the chip can be randomly placed without setting a specific position, the restriction of the arrangement position of the existing isolation unit is eliminated, and the flexibility of chip design is greatly improved.
In a preferred embodiment, as shown in fig. 5, the metal layer 6 comprises a metal layer for VDD power supply and a metal layer for VSS power supply, and the metal layer for VDD power supply is partitioned into a first metal layer 9 and a second metal layer 10. In this embodiment, the metal layer for VDD power supply is also isolated, which is suitable for the situation where the power supply of VDD of the isolation unit needs to be isolated.
On the basis of the above embodiments, the invention correspondingly provides a multi-voltage-domain low-power-consumption chip, which includes a power gating module, a power supply module capable of being turned off, a power switch, a standard unit always powered on and a plurality of isolation units, wherein any one of the partition filling units of the invention is arranged on the left side and the right side of each isolation unit.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention.
Claims (4)
1. A partition filler unit, comprising: the substrate layer, the polycrystalline silicon layer, the diffusion layer and the metal layer are sequentially stacked;
the diffusion layer comprises an N + diffusion layer and a P + diffusion layer; the substrate layer is partitioned into a first substrate and a second substrate, and when the partitioning filling units are distributed on the left side and the right side of the isolation units of the multi-voltage-domain low-power-consumption chip, the substrates of the isolation units are isolated.
2. The blocking fill cell of claim 1, wherein the metal layer comprises a metal layer for VDD supply, and wherein the metal layer for VDD supply is blocked into a first metal layer and a second metal layer.
3. The cut-off fill cell of claim 1, wherein the substrate layer is an N-well substrate.
4. A multi-voltage-domain low-power-consumption chip comprises a power gate control module, a turn-off power module, a power switch, a standard unit for keeping electricity always on and a plurality of isolation units, and is characterized in that the left side and the right side of each isolation unit are respectively provided with a partition filling unit according to any one of claims 1-3.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110744849.XA CN113555372B (en) | 2021-06-30 | 2021-06-30 | Partition filling unit and multi-voltage-domain low-power-consumption chip |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110744849.XA CN113555372B (en) | 2021-06-30 | 2021-06-30 | Partition filling unit and multi-voltage-domain low-power-consumption chip |
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| CN113555372A CN113555372A (en) | 2021-10-26 |
| CN113555372B true CN113555372B (en) | 2022-06-07 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2004221231A (en) * | 2003-01-14 | 2004-08-05 | Nec Electronics Corp | Apparatus and method for generating layout pattern and method for manufacturing semiconductor device using the same |
| EP3321769A1 (en) * | 2003-05-07 | 2018-05-16 | Conversant Intellectual Property Management Inc. | Managing power on integrated circuits using power islands |
| US7895548B2 (en) * | 2007-10-26 | 2011-02-22 | Synopsys, Inc. | Filler cells for design optimization in a place-and-route system |
| US8677292B2 (en) * | 2009-04-22 | 2014-03-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cell-context aware integrated circuit design |
| JP6031675B2 (en) * | 2012-10-01 | 2016-11-24 | 株式会社ソシオネクスト | Layout structure and layout method of semiconductor device |
| JP6115408B2 (en) * | 2013-08-29 | 2017-04-19 | 三菱電機株式会社 | Semiconductor device |
| US10331838B2 (en) * | 2016-12-12 | 2019-06-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device with fill cells |
| US11138360B2 (en) * | 2018-10-31 | 2021-10-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device with filler cell region, method of generating layout diagram and system for same |
| US11675949B2 (en) * | 2019-02-21 | 2023-06-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Space optimization between SRAM cells and standard cells |
| CN110555269B (en) * | 2019-09-02 | 2023-04-18 | 飞腾信息技术有限公司 | Top-level clock tree structure of system on chip |
| CN110752203B (en) * | 2019-10-30 | 2021-03-23 | 珠海格力电器股份有限公司 | Low-power-consumption chip and preparation method thereof |
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