CN113539311A

CN113539311A - Biasing method for reducing parasitic leakage of diode gating array

Info

Publication number: CN113539311A
Application number: CN202110724690.5A
Authority: CN
Inventors: 李阳; 蔡道林; 宋志棠; 崔紫荆; 李程兴
Original assignee: Shanghai Institute of Microsystem and Information Technology of CAS
Current assignee: Shanghai Institute of Microsystem and Information Technology of CAS
Priority date: 2021-06-29
Filing date: 2021-06-29
Publication date: 2021-10-22

Abstract

The invention relates to a bias method for reducing parasitic leakage of a diode gating array, wherein the diode gating array comprises at least two crossed bit lines and at least two word lines, diodes are arranged at the crossed points of the bit lines and the word lines, gating signals are applied to a plurality of adjacent bit lines, other bit lines are grounded, the word line where a gating unit is located is grounded, and a voltage V which is greater than an operating voltage and less than the reverse breakdown voltage of the diodes is applied to other word lines_pAnd the gating units are positioned on the same word line. The invention can reduce the parasitic electric leakage of the array and improve the reliability of the storage unit.

Description

Biasing method for reducing parasitic leakage of diode gating array

Technical Field

The invention relates to the technical field of integrated circuits, in particular to a biasing method for reducing parasitic leakage of a diode gating array.

Background

The memory is an important component of an integrated circuit, and with the continuous development of information technology, various newly proposed technologies and products put higher requirements on the aspects of capacity, speed, reliability, embedded application and the like of the memory. The mainstream semiconductor memory in the market at present cannot meet the increasing new requirements, and especially, in the current semiconductor technology level, the simple scaling down of the memory cell size will cause many reliability problems, so that a great deal of investment and research is made in the industry and academia for some new semiconductor memory technologies with excellent comprehensive capability. Phase change memories, resistive memories, ferroelectric memories, magnetoresistive memories are currently the most promising ones. These memories have now begun to gradually replace traditional memories (DRAM, FLASH, etc.), taking up a portion of the market share.

Diodes are one of the mainstream gating devices for various emerging types of memories. Compared with other gates, the memory cell device using the diode as the gate has the advantages of simple structure, small cell area, easy integration and relatively mature manufacturing process, and has good prospect in the market of super-large-capacity embedded chips in the future. The diode array is mainly composed of a plurality of Bit-lines (BL) crossed in a cross, a plurality of Word-lines (WL) and diodes at the crossed points. When a certain diode in the gating array is gated, the bit line BL where the unit is located is gated_nApplying operation voltage to perform read-write operation, and gating word line WL on which the unit is located_nGrounding for flowing out operation current, grounding other bit lines for ensuring WL_nThe voltage drop across the other cells is 0V (half-gated), and the other word lines are applied with a larger voltage V_p(greater than the operating voltage V)_inLess than the diode reverse breakdown voltage) causes most of the other cells to be in the reverse off state.

The parasitic triode leakage phenomenon is the most difficult problem to solve in the current diode array. In the gated array, when the diode is in forward conduction, most of conduction current comes from minority carrier diffusion movement, and hole diffusion current mainly exists in an N region. The holes are recombined with the majority electrons during the diffusion process and converted into majority drift current. For high density memory arrays, the adjacent diodes on the word line are very close together and minority carriers are emptyThe hole is easily diffused to the non-gated diode and generates a reverse leakage current I_cThis phenomenon is very similar to the triode amplification principle, and is called parasitic triode effect. With the density of the memory becoming larger and the distance between adjacent cells becoming closer, the parasitic PNP transistor will cause adjacent Bit Lines (BL) when normal biasing method is used_n-1，BL_n+1) The leakage of (a) will be larger and directly affect the memory state of the neighboring half-strobed cell. Due to the particularity of the process and the material, the leakage current of the type is difficult to completely solve from the root.

Disclosure of Invention

The technical problem to be solved by the invention is to provide a biasing method for reducing parasitic leakage of a diode gating array, which can reduce parasitic leakage of the array and improve reliability of a storage unit.

The technical scheme adopted by the invention for solving the technical problems is as follows: the diode array comprises at least two crossed bit lines and at least two word lines, diodes are arranged at the crossed points of the bit lines and the word lines, a gating signal is applied to a plurality of adjacent bit lines, other bit lines are grounded, the word line where the gating unit is located is grounded, and a voltage V which is greater than an operating voltage and less than the reverse breakdown voltage of the diodes is applied to other word lines_pAnd the gating units are positioned on the same word line.

For the same word line 2 when applying the strobe signalⁿAnd simultaneously applying gating signals to adjacent diodes, wherein n is a positive integer.

A layer of storage medium is arranged between the bit lines and the word lines of the diode array.

The gating signal is provided by a pulse generator.

The gating signal is a current signal or a voltage signal.

The diode array forms a three-dimensional stacked structure in a mode of overlapping word lines and bit lines.

Advantageous effects

Due to the adoption of the technical scheme, compared with the prior art, the invention has the following advantages and positive effects: by improving the data writing method of the diode gated array, the parasitic leakage current of adjacent bit lines is greatly reduced or completely eliminated, the adjacent ungated memory units are guaranteed not to be interfered by the leakage current, the whole memory array can be correctly read and written, a plurality of data can be written at one time, and the data writing efficiency is improved.

Drawings

FIG. 1 is a schematic diagram of a prior art biasing method for gating an intermediate diode;

FIG. 2 is a schematic diagram of the gating of multiple diodes using the biasing method of the present invention;

FIG. 3 is a schematic diagram of a parasitic leakage condition that exists in a prior art diode array;

fig. 4 is a schematic diagram of the case where two diodes are simultaneously conducting in the forward direction after the biasing method of the present invention is adopted.

Detailed Description

The invention will be further illustrated with reference to the following specific examples. It should be understood that these examples are for illustrative purposes only and are not intended to limit the scope of the present invention. Further, it should be understood that various changes or modifications of the present invention may be made by those skilled in the art after reading the teaching of the present invention, and such equivalents may fall within the scope of the present invention as defined in the appended claims.

The invention relates to a bias method for reducing parasitic leakage of a diode gating array, which mainly comprises the steps of applying a gating voltage V to a plurality of adjacent bit lines simultaneously for a crisscross diode gating array_inThe other bit line and word line are not changed by using the traditional bias, namely the word line WL where the gating unit is positioned_nGrounding, grounding of other bit lines, and applying larger voltage V to other word lines_p(greater than the operating voltage V)_inLess than the diode reverse breakdown voltage). The method is represented in a diode-gated memory array by simultaneously reading and writing a plurality of adjacent memory cells (typically positive integer powers of 2,4,8 …) on the same word line using specific voltage or current pulses, while the bias voltages of the other bit lines and word lines remain unchanged,i.e. multiple bits are written simultaneously.

At least the following basic devices are required to implement this embodiment: the diode array comprises at least two criss-cross bit lines and at least two word lines, and diodes are arranged at the intersections of the bit lines and the word lines; at least one pulse generator that generates a specific voltage or current pulse. A layer of storage medium is added between the bit lines and word lines of the crisscross diode array to store data. The pulse generator provides read and write pulses for the storage medium and bias voltages for the diode array.

Fig. 1 is a device or system architecture implementing the present method and using a normal bias method to gate the middle diode. Diode-gated memory arrays add memory material to the diode array, with a pulse generator providing a bias voltage to the memory array. The normal bias method is that the bit line BL where the gating unit is located_nApplying operation voltage to perform read-write operation, and gating word line WL on which the unit is located_nGrounding for flowing out operation current, grounding other bit lines for ensuring WL_nThe voltage drop across the other cells is 0V (half-gated), and the other word lines are applied with a larger voltage V_p(greater than the operating voltage V)_inLess than the diode reverse breakdown voltage) causes most of the other cells to be in the reverse off state. The magnitude of the voltage is determined by the diode characteristic curve and the memory material properties, where V_inIs 0V-2.7V, V_p4V. At this time, the operating current will be from BL_nFlowing to WL via the memory material and diode_nBut because of the parasitic PNP triode, the same word line WL exists_nThere is a reverse leakage current in the upper adjacent diode.

It can be seen that when the pulse generator provides a bias to the diode array, the strobe current will be sourced by the strobe bit line BL_nThrough the diode at the cross point, and then through the gated word line WL_nAnd (4) flowing out. When the diode is gated, most of conduction current comes from minority carrier diffusion movement, and when the minority carrier diffusion length Lp is larger, the current is diffused to an adjacent diode on the same word line to form reverse parasitic leakage, so that the miswriting of a storage medium is caused, and the reliability of stored data is influenced. To is directed atThe parasitic triode is used for electric leakage, the scheme adopted by the embodiment is that a plurality of bit lines are directly gated to simultaneously read and write a plurality of units, diffusion current can only flow out of the word lines, leakage current is avoided, and the read-write efficiency can be improved.

As shown in fig. 2, here for the purpose of eliminating the BL shown in fig. 1_n+1The voltage on the bit line is raised from 0V to V by the leakage current_inAnd simultaneously gating the two diodes. FIG. 3 is a graph of leakage current present in the array when a single diode is gated on in FIG. 1, where BL_n+1The current in (c) is a reverse leakage, the presence of which affects the data reliability of the non-gated memory cell. Fig. 4 shows the effect of writing data by the multi-bit write-once method in fig. 2, and two diodes are simultaneously gated, and are both in forward conduction, so that the original reverse leakage is eliminated, and for the memory array, two data are simultaneously written, and the writing speed is doubled.

Therefore, the invention greatly reduces or thoroughly eliminates the parasitic leakage current of the adjacent bit lines by improving the data writing method of the diode gating array, ensures that the adjacent ungated memory cells are not interfered by the leakage current, ensures that the whole memory array can be correctly read and written, can write a plurality of data at a time and improves the data writing efficiency. Under the conditions of continuous reduction of the size of the future microelectronic process and continuous progress of the technology, the method is the best solution for reducing the parasitic leakage of the array and improving the reliability of the memory unit.

Claims

1. A bias method for reducing parasitic leakage of a diode gating array, the diode array comprises at least two criss-cross bit lines and at least two word lines, and diodes are arranged at the intersections of the bit lines and the word lines_pAnd the gating units are positioned on the same word line.

2. The biasing method for reducing parasitic leakage in a diode-gated array of claim 1, wherein the gating signal is applied to 2 of the same word lineⁿAnd simultaneously applying gating signals to adjacent diodes, wherein n is a positive integer.

3. The biasing method for reducing parasitic leakage of the diode-gated array as claimed in claim 1, wherein a layer of storage medium is disposed between the bit lines and the word lines of the diode array.

4. The biasing method for reducing parasitic leakage of a diode gated array of claim 1 wherein the gating signal is provided by a pulse generator.

5. The biasing method for reducing parasitic leakage of a diode-gated array of claim 1, wherein the gating signal is a current signal or a voltage signal.

6. The biasing method for reducing parasitic leakage of a diode-gated array of claim 1, wherein the diode array is formed in a three-dimensional stacked structure by stacking word lines and bit lines.