CN113516957B - Gate drive circuit and display panel - Google Patents
Gate drive circuit and display panel Download PDFInfo
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- CN113516957B CN113516957B CN202110741748.7A CN202110741748A CN113516957B CN 113516957 B CN113516957 B CN 113516957B CN 202110741748 A CN202110741748 A CN 202110741748A CN 113516957 B CN113516957 B CN 113516957B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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Abstract
The application discloses a grid driving circuit and a display panel, which are used for driving the display panel, wherein the grid driving circuit comprises a grid driving circuit and a reset signal generating circuit; the input end of the reset signal generating circuit receives at least one of the clock signals and the grid driving signal output by the last stage of grid driving unit to generate a reset signal; the output end outputs a reset signal to the reset end of the last stage of grid drive unit; the reset signal generating circuit generates a reset signal, wherein the starting time of the reset signal in each frame is not earlier than the ending time of the grid driving signal of the last stage of grid driving unit of the current frame, and the ending time of the reset signal is not later than the starting time of the frame starting signal of the next frame. The method and the device utilize the existing signals, generate the reset signals through the reset signal generating circuit, reset the last stages of gate driving units, reduce the number of the signals and increase the stability of the gate driving circuit in the blank time.
Description
Technical Field
The application relates to the technical field of display, in particular to a gate driving circuit and a display panel.
Background
As mainstream display devices in the display industry, liquid crystal display devices are being designed and manufactured in a more and more manner. At present, most of liquid crystal display screens adopt a grid driving circuit to replace an external grid driving chip of a grid driver (gate driver), and narrow frames of panels are realized.
In the conventional gate driving circuit, the output of n-a stage is used as a starting signal of n stage, and the output of n + b stage is used as a reset signal of n stage, but a reset signal is often needed to the last stage or several stages of gate driving units of the gate driving circuit to enable the last stage or several stages of gate driving units of the gate driving circuit to stop outputting high signals. At present, a method generally adopted is to directly increase a reset signal, so that the cost of one more signal is increased, or a frame start signal of a first stage of a gate driving circuit is used as the reset signal, and the stability risk of the gate driving circuit in the last stages or Dummy stages in the blank time is increased, so that the reliability risk of the gate driving circuit is increased.
Disclosure of Invention
The application aims to provide a gate driving circuit and a display panel, which do not need to additionally increase the number of signals, reduce the number of signals and increase the stability of the gate driving circuit in blank time while resetting the last stages or the last stage of gate driving units.
The application discloses a grid driving circuit, which comprises a plurality of rows of scanning lines, at least two clock signal lines and a plurality of cascaded grid driving units, wherein the at least two clock signal lines output at least two different clock signals; the plurality of cascaded gate driving units correspond to the plurality of rows of scanning lines, and each gate driving unit is connected with a corresponding clock signal line to receive the corresponding clock signal, generate a gate driving signal and output the gate driving signal to the corresponding scanning line; the gate driving circuit further comprises a reset signal generating circuit; the input end of the reset signal generating circuit receives at least one of the clock signals and the grid driving signal output by the last stage of grid driving unit to generate a reset signal; the output end outputs the reset signal to the reset end of the last stage of grid driving unit; the reset signal generating circuit generates a reset signal, wherein the starting time of the reset signal in each frame is not earlier than the ending time of the gate driving signal of the last stage gate driving unit of the current frame, and the ending time of the reset signal is not later than the starting time of the frame starting signal of the next frame.
Optionally, the gate driving units are divided into at least two groups, the corresponding gate driving units in each group of gate driving units are sequentially cascaded, the gate driving units in different groups are connected to different clock signal lines, and the gate driving units in the same group are connected to the same clock signal line; the reset signal generating circuit receives a grid driving signal output by the last stage of grid driving unit in all the grid driving units; and the output end of the reset signal generating circuit simultaneously outputs the reset signals to the reset end of the last stage of grid driving unit in each group of grid driving units.
Optionally, the display panel has N scan lines, the gate driving circuit has N +1 gate driving units, the first N gate driving units correspond to the N scan lines, the (N + 1) th gate driving unit is a virtual gate driving unit, and a gate driving signal output by the virtual gate driving unit is output to a reset end of the nth gate driving unit; and the output end of the reset signal generating circuit outputs the reset signal to the reset end of the virtual grid driving unit.
Optionally, the starting time of the reset signal and the ending time of the gate driving signal of the last stage of gate driving unit are the same time.
Optionally, the reset signal generating circuit includes a reset control module, a reset signal output module and a voltage maintaining module; the output end of the last stage of grid driving unit is connected to the control end of the reset control module, and the input end of the reset control module is connected to a standard high level; the output end of the reset control module is connected to the control end of the reset signal output module; the input end of the reset signal output module is connected to at least one of the clock signals; the voltage maintaining module is arranged between the control end of the reset signal output module and the output end of the reset signal output module; the output end of the reset signal output module outputs the reset signal and outputs the reset signal to the reset end of the last stage of gate drive unit.
Optionally, the reset signal generating circuit includes a reset control module, a reset signal output module and a voltage maintaining module; the output end of the last stage of grid driving unit is connected to the control end of the reset control module, and the input end of the reset control module is connected to the control end of the reset control module; the output end of the reset control module is connected to the control end of the reset signal output module; the input end of the reset signal output module is connected to at least one of the clock signals; the voltage maintaining module is arranged between the control end of the reset signal output module and the output end of the reset signal output module; the output end of the reset signal output module outputs the reset signal and outputs the reset signal to the reset end of the last stage of gate drive unit.
Optionally, the clock signal at least includes a first clock signal and a second clock signal, and the first clock signal is input to the input end of the reset signal output module; the reset signal generating circuit further comprises a pull-down module, wherein the input end of the pull-down module receives a low-voltage signal, the control end of the pull-down module receives the second clock signal, and the output end of the pull-down module is connected with the output end of the reset signal output module.
Optionally, the clock signal at least includes a first clock signal, and the first clock signal is input to the input end of the reset signal output module; the reset signal generating circuit further comprises a pull-down module, wherein the input end of the pull-down module receives a low-voltage signal, the control end of the pull-down module receives a frame starting signal, and the output end of the pull-down module is connected with the output end of the reset signal output module.
Optionally, the reset control module includes a first transistor, the reset signal output module includes a second transistor, and the pull-down module includes a third transistor and a fourth transistor; the voltage maintaining module comprises a first capacitor; the clock signals comprise at least a first clock signal and a second clock signal; the output end of the last stage of grid electrode driving unit is connected to the control end of the first transistor, and the input end of the first transistor is connected to a standard high level; the output end of the first transistor is connected to the control end of the second transistor; an input end of the second transistor is connected to the first clock signal; the first capacitor is arranged between the control end of the second transistor and the output end of the second transistor; the output end of the second transistor outputs the reset signal and outputs the reset signal to the reset end of the last stage of grid electrode driving unit; the control end of the third transistor receives the second clock signal, the input end of the third transistor receives a low level signal, and the output end of the third transistor is connected with the output end of the first transistor; and the control end of the fourth transistor is connected with the second clock signal, the input end of the fourth transistor receives a low level signal, and the output end of the fourth transistor is connected with the output end of the second transistor.
The application also discloses a display panel, which comprises a time sequence control module and the grid driving circuit, wherein the time sequence control module generates a clock signal and a frame starting signal, and the grid driving circuit generates a grid driving signal according to the clock signal and the frame starting signal and outputs the grid driving signal to a scanning line of the grid driving circuit so as to drive the display panel; the gate driving circuit comprises a reset signal generating circuit, and the input end of the reset signal generating circuit receives at least one of the clock signals and the gate driving signal output by the last stage of gate driving unit to generate a reset signal; and the output end outputs the reset signal to the reset end of the last stage of gate drive unit.
For the scheme that new signals are added to reset the last gate driving units of the gate driving circuits, the number of signals of rows does not need to be additionally increased, so that the increase of the number of signals and the increase of product cost are avoided.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the application, are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. It is obvious that the drawings in the following description are only some embodiments of the application, and that for a person skilled in the art, other drawings can be derived from them without inventive effort. In the drawings:
fig. 1 is a schematic structural diagram of a gate driving circuit according to a first embodiment of the present application;
fig. 2 is a waveform diagram of a reset signal of the first embodiment of the present application;
fig. 3 is a schematic structural diagram of a gate driving circuit according to a second embodiment of the present application;
fig. 4 is a waveform diagram of a reset signal of a second embodiment of the present application;
fig. 5 is a schematic configuration diagram of a reset signal generation circuit of a third embodiment of the present application;
fig. 6 is a schematic configuration diagram of a reset signal generation circuit of a fourth embodiment of the present application;
fig. 7 is a schematic configuration diagram of a reset signal generation circuit of a fifth embodiment of the present application;
fig. 8 is a schematic configuration diagram of a reset signal generation circuit of a sixth embodiment of the present application;
fig. 9 is a signal waveform diagram in a reset signal generating circuit of a sixth embodiment of the present application;
fig. 10 is a schematic configuration diagram of a reset signal generation circuit of a seventh embodiment of the present application;
fig. 11 is a schematic structural diagram of a gate driving circuit according to an eighth embodiment of the present application;
fig. 12 is a schematic structural diagram of a gate driving circuit according to a ninth embodiment of the present application;
fig. 13 is a schematic structural diagram of a gate driving circuit according to a tenth embodiment of the present application;
fig. 14 is a schematic configuration diagram of a reset signal generation circuit of a tenth embodiment of the present application;
FIG. 15 is a waveform diagram of a reset signal and associated timing signals of a tenth embodiment of the present application;
FIG. 16 is a waveform diagram of a reset signal and associated timing signals of a tenth embodiment of the present application;
fig. 17 is a schematic structural diagram of a display panel according to an eleventh embodiment of the present application.
100, a display panel; 110. a gate drive circuit; 120. a time sequence control module; 130. a gate driving unit; 140. a reset signal generating circuit; 141. a reset control module; 142. a reset signal output module; 143. a pull-down module; 144. a voltage maintaining module; 150. scanning lines; 160. a first clock signal line; 170. a second clock signal line; c1, a first capacitor; t1, a first transistor; t2, a second transistor; t3, a third transistor; t4, a fourth transistor; CLK, clock signal receiving end; input, input end; output, output terminal; reset, reset terminal; CLK1, a first clock signal; CLK2, a second clock signal; CLK3, third clock signal; CLK4, fourth clock signal; CLK5, fifth clock signal; CLK6, sixth clock signal; STV, frame start signal; VGH, standard high level; VSS, standard low level; GND and ground.
Detailed Description
It is to be understood that the terminology, the specific structural and functional details disclosed herein are for the purpose of describing particular embodiments only, and are representative, but that the present application may be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein.
In the description of the present application, the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating relative importance or as implicitly indicating the number of technical features indicated. Thus, unless otherwise specified, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature; "plurality" means two or more. The terms "comprises" and "comprising," and any variations thereof, are intended to cover a non-exclusive inclusion, such that one or more other features, integers, steps, operations, elements, components, and/or combinations thereof may be present or added.
Further, terms of orientation or positional relationship indicated by "center", "lateral", "upper", "lower", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, are described based on the orientation or relative positional relationship shown in the drawings, are simply for convenience of description of the present application, and do not indicate that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application.
Furthermore, unless expressly stated or limited otherwise, the terms "mounted," "connected," and "coupled" are to be construed broadly and encompass, for example, both fixed and removable coupling as well as integral coupling; can be mechanically or electrically connected; either directly or indirectly through intervening media, or through both elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
The present application is described in detail below with reference to the figures and alternative embodiments.
Fig. 1 is a schematic diagram of a gate driving circuit according to a first embodiment of the present application; fig. 2 is a waveform diagram of a reset signal of the first embodiment of the present application; as shown in fig. 1, as an embodiment of the present application, a gate driving circuit 110 is disclosed, the gate driving circuit 110 includes a plurality of rows of scan lines 150, at least two clock signal lines and a plurality of cascaded gate driving units 130, the at least two clock signal lines outputting at least two different clock signals; the plurality of cascaded gate driving units 130 correspond to the plurality of rows of scan lines 150 one to one, and each gate driving unit 130 is connected to a corresponding clock signal line to receive the corresponding clock signal, generate a gate driving signal, and output the gate driving signal to the corresponding scan line 150.
As illustrated in fig. 1, the two clock signal lines are a first clock signal line 160 and a second clock signal line 170, the odd-numbered column gate driving units are correspondingly connected to the first clock signal line 160 to receive a first clock signal CLK1, the even-numbered column gate driving units are correspondingly connected to the second clock signal line 170 to receive a second clock signal CLK2, the first clock signal CLK1 and the second clock signal CLK2 are both periodic signals, and the gate driving signal Goutn of the last stage is generated based on the second clock signal.
Each gate driving unit 130 includes a standard high level Input end for receiving a standard high level VGH, a standard low level Input end for receiving a standard low level VGL, a clock signal Input end CLK for receiving a clock signal, an Input end, an Output end and a Reset end Reset, the Input end of the first gate driving unit is connected to the frame start signal STV, the Output end outputs a scanning signal corresponding to the first scanning line G1 to the first scanning line, the Reset end Reset is connected to the Output end Output of the next-stage gate driving unit 130, and the Input ends of all the gate driving units 130 except the first-stage gate driving unit are connected to the Output end Output of the next-stage gate driving unit 130; except for the last stage of gate driving unit, the Reset terminals Reset of all the gate driving units are connected to the Output terminal Output of the next stage of gate driving unit.
The gate driving circuit 110 further includes a Reset signal generating circuit 140, an input terminal of the Reset signal generating circuit 140 receives at least one of the clock signals and the gate driving signal output by the last stage of gate driving unit, and generates a Reset signal Reset _0ut; and the output end outputs the reset signal to the reset end of the last stage of grid drive unit. Because the last stage of gate driving unit can not carry out automatic reset and no lower stage gate driving unit outputs a gate driving signal for resetting, the reset signal generating circuit generates a reset signal according to a clock signal and the gate driving signal of the last stage of gate driving unit to reset the last stage of gate driving unit.
Fig. 2 is a waveform diagram of a reset signal of the first embodiment of the present application; as shown in fig. 2, the reset time cannot be too long or too short because the normal display of the display panel needs to be considered during the reset, the start time of the reset signal generated by the reset signal generating circuit in each frame is not earlier than the end time of the gate driving signal of the last stage gate driving unit of the current frame, and the end time of the reset signal is not later than the start time of the frame start signal of the next frame.
As a preferred scheme of the present application, the start time of the Reset signal and the end time of the gate driving signal of the last stage of gate driving unit are the same time, and the Reset _0ut signal is turned on at the falling edge of Gountn, so that the normal driving of Gountn is not affected; the ending time of the Reset signal and the starting time of the frame starting signal of the next frame are the same time, the Reset _0ut signal is cut off at the STV rising edge, and the last stage of grid unit is always maintained in a Reset state before the next frame signal is output, so that the pull-down time of the last stage of grid driving unit can be prolonged, and the pull-down effect is optimal.
FIG. 3 is a schematic diagram of a gate driving circuit according to a second embodiment of the present application; as another embodiment of the present application, different from the above embodiments, the last stage of gate driving unit is a dummy gate driving unit, specifically, the display panel has N scanning lines 150, the gate driving circuit 110 has N +1 gate driving units 130, the first N gate driving units 130 correspond to the N scanning lines, the N +1 th gate driving unit is a dummy gate driving unit (dummy), and a gate driving signal output by the dummy gate driving unit is output to a reset end of the nth stage of gate driving unit; the output terminal of the reset signal generating circuit 140 outputs the reset signal to the reset terminal of the dummy gate driving unit.
The value of N is an even number, the odd-numbered column gate driving units are correspondingly connected to the first clock signal line 160 to receive the first clock signal CLK1, the even-numbered column gate driving units are correspondingly connected to the second clock signal line 170 to receive the second clock signal CLK2, and the reset signal generating circuit 140 generates a reset signal according to the gate driving signal Gontn +1 and the second clock signal CLK2 output by the dummy gate driving unit to output the reset end of the dummy gate driving unit.
Fig. 5 is a schematic configuration diagram of a reset signal generation circuit of a third embodiment of the present application; as shown in fig. 5, as a third embodiment of the present application, which is a further refinement and refinement of any of the above embodiments, the reset signal generating circuit 140 includes a reset control module 141, a reset signal output module 142, and a voltage maintaining module 144.
An output terminal Goutn +1 of the last stage gate driving unit is connected to the control terminal of the reset control module 141, and an input terminal of the reset control module 141 is connected to a standard high level VGH; the output end of the reset control module 141 is connected to the control end of the reset signal output module 142; the input terminal of the reset signal output module 142 is connected to at least one of the clock signals; the voltage maintaining module 144 is disposed between the control terminal of the reset signal output module 142 and the output terminal of the reset signal output module 142; the output end of the Reset signal output module 142 outputs the Reset signal Reset _0ut, and outputs the Reset signal to the Reset end of the last stage of gate driving unit.
The standard high-level VGH preferentially charges the voltage maintaining module 144, after the output end of the last stage of the gate driving unit outputs the gate driving signal to be disconnected, the reset control module 141 cannot continuously access the standard high-level maintaining reset signal output module 142 to be turned on, at this time, the voltage maintaining module 141 maintains the control end of the reset signal output module 142 to be turned on through discharging, so that the reset signal is completely output, and waveform deformation caused by the influence of impedance when the gate driving signal Goutn is at the last stage is avoided, the time for turning on the control end of the reset signal output module 142 is limited, and the output of the reset signal is incomplete.
The voltage maintaining module 144 mainly includes a capacitor, the reset control module 141 and the reset signal output module 142 are generally thin film transistors that are turned on at a high level, and certainly, the reset control module 141 and the reset signal output module 142 may also be other circuits that can implement the function of the module in the reset circuit, which is not described herein.
Fig. 6 is a schematic configuration diagram of a reset signal generating circuit of a fourth embodiment of the present application; as a fourth embodiment of the present application, the third embodiment is further improved, in which the clock signals include at least a first clock signal CLK1 and a second clock signal CLK2, and the first clock signal CLK1 is input to the input terminal of the reset signal output module 142;
the reset signal generating circuit 140 further includes a pull-down module 143, an input end of the pull-down module 143 receives a low voltage signal VSS, which includes but is not limited to ground, and when the clock signal is a low level signal, the low voltage signal can also be used as a receiving signal of the input end of the pull-down module 143; a control terminal of the pull-down module 143 receives the second clock signal CLK2, and an output terminal of the pull-down module 143 is connected to the output terminal of the reset signal output module 142 and the output terminal of the reset control module 141.
The waveform of one of the two clock signals is output as a reset signal, the conduction time is determined by the clock signals, the first clock signal CLK1 and the second clock signal CLK2 are both periodic signals, the last stage of gate drive signal Goutn is generated based on the second clock signal, the first clock signal CLK1 corresponds to the gate drive signal within the effective time, the two signals are combined to be used as the reset signal, and the reset signal generating circuit is simpler to implement and has high reliability.
Fig. 7 is a schematic configuration diagram of a reset signal generation circuit of a fifth embodiment of the present application; as a fifth embodiment of the present application, different from the fourth embodiment, the pull-down module uses a frame start signal STV as a signal for controlling the opening, specifically, as shown in fig. 5, an input end of the pull-down module 143 receives a low voltage signal VSS, a control end of the pull-down module 143 receives the frame start signal STV, and an output end of the pull-down module 143 is connected to an output end of the reset signal output module.
Fig. 8 is a schematic configuration diagram of a reset signal generation circuit of a sixth embodiment of the present application;
fig. 9 is a signal waveform diagram in a reset signal generating circuit of a sixth embodiment of the present application; as a sixth embodiment of the present application, which is a refinement and improvement of all the above embodiments, as shown in fig. 8 and 9, the reset control module 141 includes a first transistor T1, the reset signal output module 142 includes a second transistor T2, and the pull-down module 143 includes a third transistor T3 and a fourth transistor T4; the voltage maintaining module comprises a first capacitor C1; the clock signals include at least a first clock signal CLK1 and a second clock signal CLK2.
The output end of the last stage of gate driving unit is connected to the control end of the first transistor T1, and the input end of the first transistor T1 is connected to a standard high level VGH; the output end of the first transistor T1 is connected to the control end of the second transistor T2; an input terminal of the second transistor T2 is connected to the first clock signal CLK1; the first capacitor C1 is disposed between the control terminal of the second transistor T2 and the output terminal of the second transistor T2; the output end of the second transistor T2 outputs the reset signal, and outputs the reset signal to the reset end of the last stage of gate drive unit; a control end of the third transistor T3 receives the second clock signal CLK2, an input end receives a low level signal VSS, and an output end is connected to the output end of the first transistor; a control end of the fourth transistor T4 is connected to the second clock signal CLK2, an input end receives a low level signal, and an output end is connected to an output end of the second transistor T2.
Referring to fig. 8 and 9, time T1, during the high period of Goutn, CLK1 is low and CLK2 is high; the potential of the point Q rises from a low level to a potential of V1; time T2, goutn Low level, CLK1 high level, CLK2 Low level; the potential of the point Q rises to the potential of V2; time T3, goutn Low level, CLK1 Low level, CLK2 high level; the potential of the point Q is reduced to a low level potential, and a Reset signal Reset _ out is output in the time T2; VGH charges capacitor C1 through T1; goutn controls the conduction of T1 and the charging time of C1; CLK1 outputs a reset signal through T2; c1 maintains the conduction of T2; CLK2 controls T3 and T4 to pull down to discharge capacitor C1.
Fig. 10 is a schematic configuration diagram of a reset signal generation circuit of a seventh embodiment of the present application; as shown in fig. 10, different from the above embodiment, the reset control module 141 includes a first transistor, the input terminal of the first transistor T1 is short-circuited with the control terminal, the input terminal does not need to be connected with a standard high level signal, and the last stage of gate driving signal received by the control terminal is directly used as an input signal, so that the signal and the trace space required to be connected to the signal can be saved again.
Fig. 11 is a schematic structural diagram of a gate driving circuit according to an eighth embodiment of the present application; the reset signal generating circuit 140 is added in the present application, a reset signal is generated by using an existing signal in the timing control module, so as to reset the last stage or the last stages of gate driving units, when the gate driving units can be divided into two groups or three groups, taking two groups as an example, the last stage of gate driving unit 130 in each group needs to be reset, an output end of the reset signal generating circuit 140 is simultaneously connected to a reset end of the last stage of gate driving unit 130 in two groups so as to reset the last two stages of gate driving units, for example, the last stage in two groups is respectively the n +1 th stage and the n +2 th stage, so that a gate driving signal corresponding to the n +2 th stage and a timing control signal are received to generate a reset signal corresponding to the n +2 th stage to reset the n +1 th stage and the n +2 nd stage of gate driving unit, n is a natural number greater than or equal to 2, a reset signal generating circuit can realize the reset of the last stage or the last stages of gate driving unit, wherein the last two stages can be gate driving units or can be virtual gate driving units, the reset signal generating circuit 140 can also be used for resetting dummy for the last two stages of gate driving units.
Fig. 12 is a schematic structural diagram of a gate driving circuit according to a ninth embodiment of the present application; as shown in fig. 12, each group of gate driving units may also be correspondingly provided with a reset signal generating circuit 140, an output end of each reset signal generating circuit is connected to a reset end of a last gate driving unit in each group of gate driving units 130, an input end of each reset signal generating circuit receives the timing control signal and the gate driving signal of the last gate driving unit to generate a reset signal, so as to reset the last gate driving unit, for example, the last gate driving unit in two groups is respectively an n +1 th stage and an n +2 th stage, so that receiving the gate driving signal corresponding to the n +1 th stage and the timing control signal generates a reset signal corresponding to the n +1 th stage to reset the n +1 th gate driving unit, and receiving the gate driving signal +2 corresponding to the n +2 th stage and the timing control signal generates a reset signal corresponding to the n +2 th stage to reset the n +2 th stage, where n is a natural number greater than or equal to 2, and one reset signal generating circuit may realize the reset of the last gate driving unit.
Fig. 13 is a schematic structural diagram of a gate driving circuit according to a tenth embodiment of the present application; fig. 14 is a schematic configuration diagram of a reset signal generating circuit of a tenth embodiment of the present application; 15 is a waveform diagram of a reset signal and associated timing signals of a tenth embodiment of the present application; FIG. 16 is a waveform diagram of a reset signal and associated timing signals of a tenth embodiment of the present application; as another embodiment of the present application, referring to fig. 13 to 16, in this embodiment, the clock signals include CLK1 to CLK6 for 6 clock signals, and the gate driving signals corresponding to all the gate driving units are generated according to the 6 clock signals, and the reset signal generating circuit mainly includes 4 Thin Film Transistors (TFTs), where the four TFTs are a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4, respectively; the gate of the first transistor T1 receives the output signal Goutn of the last stage of the gate driving circuit, and the last stage of the gate driving unit is a dummy gate driving unit. As the turn-on signal of the first transistor T1, the turn-on signal may be an output signal of the last stage or a high level signal VGH; the turn-on signal of the third transistor T3 is the clock signal CLK5 of the gate driving circuit, and the output signal is another clock signal CLK2; then, the output signal of the first transistor T1 and the third transistor T3 acting together is used as the turn-on signal of the second transistor T2, and the input signal thereof is the clock signal CLK2, and it is noted that the two clock signals CLK2 and CLK5 are a pair of opposite signals; the high level of the CLK2 signal corresponds to the low level of the CLK5, the high level of the CLK5 signal corresponds to the low level of the CLK2, and the turn-on signal and the input signal of the fourth transistor T4 are the same as those of the third transistor T3.
As shown in fig. 15 and 16, according to the Q-point waveform, at the start time to the end time of the first rise in potential, i.e., at time T1, goutn high level, CK2 low level, CK5 high level; the potential of the point Q rises from a low level to a potential of V1; goutn is high level from the end time of the first rise to the end time of the second rise, namely T2 time; CK2 and CK5 are both low; the potential of the point Q rises to V2; time T3, goutn Low, CK2 high, CK5 Low; the potential of the point Q rises to the potential of the highest potential V3; t4 time, goutn low, CK2 and CK5 low; the potential of the point Q is reduced to the potential of V4; t5 time, goutn low, CK2 low, CK5 high; the potential of the point Q is reduced to a low level potential, and a reset signal is output in the time T3 to reset the last stage or the last stages of virtual grid driving units.
Fig. 17 is a schematic structural view of a display panel of the eleventh embodiment of the present application; as shown in fig. 17, the present embodiment discloses a display panel 100, which includes a timing control module 120 and the gate driving circuit 110 as described in any of the above embodiments, wherein the timing control module 120 generates a clock signal CLK and a frame start signal STV, and the gate driving circuit 110 generates a gate driving signal according to the clock signal and the frame start signal and outputs the gate driving signal to a scan line of the gate driving circuit to drive the display panel 110; the gate driving circuit 110 includes a reset signal generating circuit 140, wherein an input terminal of the reset signal generating circuit 140 receives at least one of the clock signals and the gate driving signal output by the last stage gate driving unit 130 to generate a reset signal; and the output end outputs the reset signal to the last stage or the last several stages of dummy for resetting.
It should be noted that the inventive concept of the present application can form many embodiments, but the present application has a limited space and cannot be listed one by one, so that, on the premise of no conflict, any combination between the above-described embodiments or technical features can form a new embodiment, and after the embodiments or technical features are combined, the original technical effect will be enhanced
The technical solution of the present application can be widely applied to various display panels, such as TN (Twisted Nematic) display panel, IPS (In-Plane Switching) display panel, VA (Vertical Alignment) display panel, MVA (Multi-Domain Vertical Alignment) display panel, and of course, other types of display panels, such as OLED (Organic Light-Emitting Diode) display panel, which can be applied to the above solutions.
The foregoing is a more detailed description of the present application in connection with specific alternative embodiments, and the specific implementations of the present application are not to be considered limited to these descriptions. For those skilled in the art to which the present application pertains, several simple deductions or substitutions may be made without departing from the concept of the present application, and all should be considered as belonging to the protection scope of the present application.
Claims (5)
1. A gate driving circuit for driving a display panel, the gate driving circuit comprising:
a plurality of rows of scanning lines;
at least two clock signal lines outputting at least two different clock signals;
the gate driving units are connected with the corresponding clock signal lines to receive the corresponding clock signals, generate gate driving signals and output the gate driving signals to the corresponding scanning lines;
the grid driving circuit is characterized by further comprising a reset signal generating circuit; the input end of the reset signal generating circuit receives at least one of the clock signals and the grid driving signal output by the last stage of grid driving unit to generate a reset signal; the output end outputs the reset signal to the reset end of the last stage of grid driving unit;
the starting time of the reset signal generated by the reset signal generating circuit in each frame is not earlier than the ending time of the grid driving signal of the last stage of grid driving unit of the current frame, and the ending time of the reset signal is not later than the starting time of the frame starting signal of the next frame;
the reset signal generating circuit comprises a reset control module, a reset signal output module and a voltage maintaining module;
the output end of the last stage of grid driving unit is connected to the control end of the reset control module, and the input end of the reset control module is connected to a standard high level; the output end of the reset control module is connected to the control end of the reset signal output module;
the input end of the reset signal output module is connected to at least one of the clock signals; the voltage maintaining module is arranged between the control end of the reset signal output module and the output end of the reset signal output module;
the output end of the reset signal output module outputs the reset signal and outputs the reset signal to the reset end of the last stage of gate drive unit;
the clock signals at least comprise first clock signals, and the first clock signals are input to the input end of the reset signal output module;
the reset signal generating circuit further comprises a pull-down module, wherein the input end of the pull-down module receives a low-voltage signal, the control end of the pull-down module receives a frame starting signal, and the output end of the pull-down module is connected with the output end of the reset signal output module;
the grid driving units are divided into at least two groups, the corresponding grid driving units in each group of grid driving units are sequentially cascaded, the grid driving units in different groups are connected with different clock signal lines, and the grid driving units in the same group are connected with the same clock signal line;
the reset signal generating circuit receives the grid driving signal output by the last stage of grid driving unit in all the grid driving units; the output end of the reset signal generating circuit simultaneously outputs the reset signals to the reset end of the last stage of grid driving unit in each group of grid driving units;
the reset signal generating circuit generates a reset signal according to a gate driving signal output by a last stage gate driving unit of the last group of gate driving units, and resets the last stage gate driving units of the last group and each group before the last group.
2. The gate driving circuit according to claim 1, wherein a start timing of the reset signal is the same timing as an end timing of the gate driving signal of the last stage gate driving unit.
3. The gate driving circuit of claim 1, wherein the reset control module includes a first transistor, the reset signal output module includes a second transistor, and the pull-down module includes a third transistor and a fourth transistor; the voltage maintaining module comprises a first capacitor; the clock signals comprise at least a first clock signal and a second clock signal;
the output end of the last stage of grid electrode driving unit is connected to the control end of the first transistor, and the input end of the first transistor is connected to a standard high level; the output end of the first transistor is connected to the control end of the second transistor;
an input end of the second transistor is connected to the first clock signal; the first capacitor is arranged between the control end of the second transistor and the output end of the second transistor;
the output end of the second transistor outputs the reset signal and outputs the reset signal to the reset end of the last stage of grid electrode driving unit;
the control end of the third transistor receives the second clock signal, the input end of the third transistor receives a low level signal, and the output end of the third transistor is connected with the output end of the first transistor;
and the control end of the fourth transistor is connected with the second clock signal, the input end of the fourth transistor receives a low level signal, and the output end of the fourth transistor is connected with the output end of the second transistor.
4. The gate driving circuit of claim 1, wherein the reset control module includes a first transistor, the reset signal output module includes a second transistor, and the pull-down module includes a third transistor and a fourth transistor; the voltage maintaining module comprises a first capacitor; the clock signals at least comprise 6 clock signals from a first clock signal to a sixth clock signal, and the two clock signals from the second clock signal to the fifth clock signal are a pair of opposite signals;
the output end of the last stage of grid electrode driving unit is connected to the control end of the first transistor, and the input end of the first transistor is connected to a standard high level; the output end of the first transistor is connected to the control end of the second transistor;
an input end of the second transistor is connected to the second clock signal; the first capacitor is arranged between the control end of the second transistor and the output end of the second transistor;
the output end of the second transistor outputs the reset signal and outputs the reset signal to the reset end of the last stage of grid electrode driving unit;
a control end of the third transistor receives the fifth clock signal, an input end of the third transistor receives the second clock signal, and an output end of the third transistor is connected with an output end of the first transistor;
and the control end of the fourth transistor is connected with the second clock signal, the input end of the fourth transistor receives the second clock signal, and the output end of the fourth transistor is connected with the output end of the second transistor.
5. A display panel, comprising:
a timing control module; and
a gate drive circuit as claimed in any one of claims 1 to 4;
the time sequence control module generates a clock signal and a frame starting signal, and the grid driving circuit generates a grid driving signal according to the clock signal and the frame starting signal and outputs the grid driving signal to a scanning line of the grid driving circuit to drive the display panel;
the gate driving circuit comprises a reset signal generating circuit, and the input end of the reset signal generating circuit receives at least one of the clock signals and the gate driving signal output by the last stage of gate driving unit to generate a reset signal; and the output end outputs the reset signal to the reset end of the last stage of gate drive unit.
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