CN113505094B

CN113505094B - MCU, host and method for transmitting data by multiple MCUs

Info

Publication number: CN113505094B
Application number: CN202111035283.XA
Authority: CN
Inventors: 梅汪生; 张俊
Original assignee: Shanghai Analog Semiconductor Technology Co ltd
Current assignee: Shanghai Analog Semiconductor Technology Co ltd
Priority date: 2021-09-06
Filing date: 2021-09-06
Publication date: 2022-01-25
Anticipated expiration: 2041-09-06
Also published as: CN113505094A

Abstract

The application relates to the technical field of electronics, and discloses a method, MCU of host computer and a plurality of MCU transmission data, and the host computer is connected with a plurality of MCU and is the chrysanthemum chain structure, and host computer and a plurality of MCU include unidirectional clock interface and two-way data interface respectively, and the data package of data interface transmission includes: a start code, a preamble, a payload code and a stop code arranged in sequence, the preamble defining the type of the data packet. The method comprises the following steps: when the host writes data into the MCUs, the host sends clock signals and data packets with fixed periods to the MCUs, the MCUs determine the type of the written data according to lead codes in the data packets, and the data in the effective load area in the data packets are written into a target MCU; when the host computer reads data from the MCUs, the host computer sends clock signals and data packets with fixed periods to the plurality of MCUs, and when the host computer detects that the data interface of the target MCU is enabled, the data are read out from the target MCU according to the data type defined by the lead code.

Description

MCU, host and method for transmitting data by multiple MCUs

Technical Field

The present invention relates to the field of electronic technologies, and in particular, to a method for transmitting data among an MCU, a host, and a plurality of MCUs.

Background

There are no open or universal standards/protocols for low cost mcu (microcontroller unit) like 8051, and major vendors like the core balabs are using their own internal protocols. JTAG (Joint Test Action Group) is a widely used protocol and IEEE standard, but the protocol requires at least 4 pins for testing and debugging, which is not acceptable for low cost MCUs. Moreover, JTAG also requires a typical state machine to complete the test process, which requires additional logic (cost), which is also unacceptable in low cost MCUs. The present invention introduces an innovative approach for a low cost MCU to overcome the above limitations.

Disclosure of Invention

An object of an embodiment of the present specification is to provide a method for a host and multiple MCUs to transmit data, which uses a unidirectional DCK and a bidirectional DDA to implement programming, testing, and debugging of the MCUs, and implement a low-cost MCU.

An embodiment of the present application discloses a method for transmitting data between a host and a plurality of MCUs, wherein the host and the MCUs are connected in a daisy chain structure, the host and the MCUs respectively include a unidirectional clock interface and a bidirectional data interface, and a data packet transmitted by the data interface includes: a start code, a preamble, a payload code and a stop code arranged in sequence, wherein the preamble defines the type of the data packet; the method comprises the following steps:

when the host writes data into the MCUs, the host sends clock signals and data packets with fixed periods to the MCUs, the MCUs determine the type of the written data according to the lead codes in the data packets, and the data in the effective load area in the data packets are written into a target MCU;

when the host reads data from the MCUs, the host sends clock signals and data packets with fixed periods to the MCUs, and when the host detects that the data interface of the target MCU is enabled, the data are read out from the target MCU according to the data type defined by the lead code.

In a preferred embodiment, the data packet further includes: a CRC check code or a parity check code located between the preamble and the payload region.

In a preferred embodiment, the data packet further includes: a CRC or parity code located between the payload region and the termination code.

In a preferred embodiment, when the host writes data to the MCU, the data packet further includes: a preparation code located between the payload area and the termination code.

In a preferred example, when the host reads data from the MCU, the data packet further includes: a preparation code located between the preamble and the payload area.

In a preferred embodiment, the preamble has 4 bits for defining the location and pattern of data reading or writing.

In a preferred embodiment, the data packet further includes a number of the target MCU.

An embodiment of the present application discloses an MCU, the MCU includes a unidirectional clock interface and a bidirectional data interface, and a data packet transmitted by the data interface includes: a start code, a preamble, a payload code and a stop code arranged in sequence, wherein the preamble defines the type of the data packet;

when data are written into the MCU, the MCU receives a clock signal and a data packet with a fixed period, determines the type of the written data according to a lead code in the data packet, and writes the data in a payload area in the data packet into the MCU;

and when the data interface is enabled, reading out the data from the MCU according to the data type defined by the lead code.

Compared with the prior art, the embodiment of the application has at least the following differences and effects:

the application provides a low-cost MCU which realizes programming, testing and debugging of the MCU by adopting a unidirectional DCK and a bidirectional DDA.

The present specification describes a number of technical features distributed throughout the various technical aspects, and if all possible combinations of technical features (i.e. technical aspects) of the present specification are listed, the description is made excessively long. In order to avoid this problem, the respective technical features disclosed in the above summary of the invention of the present application, the respective technical features disclosed in the following embodiments and examples, and the respective technical features disclosed in the drawings may be freely combined with each other to constitute various new technical solutions (which are considered to have been described in the present specification) unless such a combination of the technical features is technically infeasible. For example, in one example, the feature a + B + C is disclosed, in another example, the feature a + B + D + E is disclosed, and the features C and D are equivalent technical means for the same purpose, and technically only one feature is used, but not simultaneously employed, and the feature E can be technically combined with the feature C, then the solution of a + B + C + D should not be considered as being described because the technology is not feasible, and the solution of a + B + C + E should be considered as being described.

Drawings

Fig. 1 is an interface schematic diagram of 2 leads of an MCU in one embodiment of the present application.

Fig. 2 is a schematic diagram of a data format in an embodiment of the present application.

FIG. 3 is a timing diagram of a write operation performed in one embodiment of the present application.

FIG. 4 is a timing diagram illustrating the MCU non-response during a write operation in one embodiment of the present application.

FIG. 5 is a timing diagram of a read operation performed in one embodiment of the present application.

FIG. 6 is a timing diagram illustrating the unresponsiveness of the MCU in a read operation in one embodiment of the present application.

FIG. 7 is a schematic diagram of a host and multiple MCUs connected in a daisy chain according to one embodiment of the present application.

FIG. 8 is a timing diagram illustrating read and write operations performed by the daisy-chained architecture in accordance with one embodiment of the present application.

FIG. 9 is a data packet of an "address phase" of a read/write operation in one embodiment of the present application.

FIG. 10 is a data packet of a "data phase" of a write operation in one embodiment of the present application.

FIG. 11 is a data packet of a "data phase" of a read operation in one embodiment of the present application.

Detailed Description

In the following description, numerous technical details are set forth in order to provide a better understanding of the present application. However, it will be understood by those skilled in the art that the technical solutions claimed in the present application may be implemented without these technical details and with various changes and modifications based on the following embodiments.

To make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

An embodiment of the present application discloses an MCU, and fig. 1 shows a schematic structural diagram of an MCU in an embodiment. The MCU comprises a unidirectional clock interface DCK and a bidirectional data interface DDA, and is connected with a Host (Host) through the clock interface DCK and the data interface DDA to realize the communication between the Host and the MCU. In this application, the term "interface" may also be referred to as a "pin" or "pin". The data transmitted by the bidirectional data interface DDA has a fixed data format, and the transmitted data packet includes: the data analysis may be simplified by sequentially arranging a Start code (Start), a Preamble (Preamble), a Payload code (Payload), and a Stop code (Stop), wherein the Preamble is used to define the type of the data packet, for example, the location and pattern of data reading or writing.

In one embodiment, as shown in fig. 2, a data packet transmitted by the data interface DDA may include a 1-bit Start code Start [0], a 3-bit Preamble [3:0], an 8-bit Payload code Payload [7:0], and a 1-bit Stop code Stop [0 ]. It should be understood that the number of bits of each code is only an example and is not a limitation of the present application, for example, the preamble may also be 6 bits or other number of bits, and similarly, the payload code may also be 12 bits or other number of bits. In particular, the Preamble [3:0] may define the location and mode of data reading or writing, e.g., the following types, respectively:

1111-Special commands (e.g. different pattern entries)

1011-high byte (if any) write target address

1010-low byte write target address

1110-low byte auto-increment mode write target address

0000-read to SFR register included in CPU

0001-write to SFR register included in CPU

0010-read to iRAM

0011-write to iRAM

0100-read to xRAM/xSFR

0101-write to xRAM/xSFR

1000-read to program flash memory

It should be noted that the above only shows some types of preambles used in the data packet, not all of the preamble types used.

In addition, when the MCU is subjected to Write operation (Write), a Parity check code Parity [0] is also included between the preamble code and the payload code in the Write command, and a CPC check code CPC [0] and a preparation code RDY [0] are also included between the payload code and the termination code. When the MCU is Read, a Parity check code (Parity [0 ]) and a preparation code (RDY [0 ]) are also included between the preamble code and the payload code in the Read command, and a CPC check code (CPC [0 ]) is also included between the payload code and the termination code. It should be noted that the parity check code and/or the CPC check code are optional. In other embodiments, only one of the parity check code or the CPC check code may also be employed.

The host first sends a packet starting from the Most Significant Bit (MSB), and only when the ready code RDY position is high (or 1) can the host move forward to the next position.

In one embodiment, when writing data to the MCU, the MCU receives a fixed period clock signal and a data packet, determines the type of data to write according to a preamble in the data packet, and writes the data in the payload area of the data packet to the MCU.

The clock interface DCK of the MCU is typically controlled by the debugger, programmer and tester of the host, and when there are no transactions (transactions), DCK should be kept low. When the DCK is low, the debugger, programmer, and tester switch (Toggle) DDA, and a Debug and Test Module (DTM) in the MCU samples the DDA on the rising edge of the DCK.

The timing definition of the DCK/DDA interface for write operations is shown in fig. 3, where DCK represents a fixed period clock signal sent by the host, namely: the clock interface of the MCU samples the clock signal, and the Data represents the Data signal output between the host and the MCU on the Data interface DDA. The DTM transaction begins when the sampling starts to the DDA falling edge (i.e., start code 0). And then, carrying out data analysis on the lead code to acquire the type of data transmission. Preferably, the preamble is checked. Next, the payload code of the data is transmitted and, preferably, the payload code is checked. And the host stops driving the data pin and continuously monitors the data pin until the DDA pin of the MCU is pulled to be at a high level, and once the host detects that the DDA pin of the MCU is high, the host stops data frame transmission and finishes the data transmission.

The timing definition of the DCK/DDA pin to which the MCU does not respond when performing a write operation is shown in FIG. 4. At this time, the host does not receive an effective RDY signal from the MCU within a predetermined time, the host directly takes over the data pin, drives the data pin to a high level to stop data frame transmission, and ends this data transmission.

In one embodiment, the MCU receives a fixed period clock signal and data packets when reading data from the MCU, and reads data from the MCU according to the data type defined by the preamble when the data interface is enabled.

The timing definition of the DCK/DDA pin for a read operation is shown in FIG. 5. DCK represents a fixed period clock signal sent by the host, namely: the clock interface of the MCU samples the clock signal, and the Data represents the Data signal output between the host and the MCU on the Data interface DDA. The DTM transaction begins when the sampling starts to the DDA falling edge (i.e., start code 0). And then, carrying out data analysis on the lead code to acquire the type of data transmission. Preferably, the preamble is checked. And then, the host stops driving the data pin, continuously monitors the data pin until the DDA pin of the MCU is pulled to be high level, and once the host detects that the DDA pin of the MCU is high, the host starts to read data from the MCU, namely, the payload code of the transmission data is acquired. And, preferably, the payload code is checked. And after the host receives the check bit, the host directly takes over the data pin and drives the data pin to be high to stop the transmission of the data frame.

The timing definition of the DCK/DDA pin to which the MCU does not respond when performing a read operation is shown in FIG. 6. If the MCU does not return a valid ready signal within a preset time (namely the ready code is always low), the host directly takes over the data pin and drives the data pin to be high to stop the transmission of the data frame.

Fig. 7 is a schematic structural diagram of a daisy chain structure formed by connecting a host and a plurality of MCUs in an embodiment of the present application, where the host and the plurality of MCUs respectively include a unidirectional clock interface DCK and a bidirectional data interface DDA, and a data packet transmitted by the data interface includes: a start code, a preamble, a payload code and a stop code arranged in sequence, wherein the preamble defines the type of the data packet. In one embodiment, the data packet further comprises a number (ID) of the target MCU, e.g. the number of the target MCU may be transmitted together with the preamble, so that the location and mode of data reading or writing may be defined for the target MCU.

Fig. 8 is a timing diagram illustrating read and write operations performed by a daisy chain structure according to an embodiment of the present application. When the host writes data into the MCUs, the host sends clock signals and data packets with fixed periods to the MCUs, the MCUs determine the type of the written data according to the lead codes in the data packets, and the data in the effective load area in the data packets are written into the target MCU. When the host computer reads data from the MCUs, the host computer sends clock signals and data packets with fixed periods to the plurality of MCUs, and when the host computer detects that the data interface of the target MCU is enabled, the data are read out from the target MCU according to the data type defined by the lead code.

Fig. 9 is a data packet for the "address phase" of a read/write operation, with the preamble "1011" specifying the high-byte write target address (e.g., xSFR/xRAM), which is required to specify the address before reading/writing any MCU registers/memory, e.g., address [15:8] specifying the address to write to the MCU. In another embodiment of the present application, the preamble "1010" specifies the low byte write target address, which needs to be specified before reading/writing any MCU registers/memory, e.g., address [7:0] specifies the address to write to the MCU. The preamble "1110" specifies a low byte address auto-increment mode write target address, which can be automatically incremented by 1 after the last transaction, so that each next access can be used to enable access to up to 256 bytes without specifying the address again.

Fig. 10 is a data packet of the "data phase" of a write operation, which may write data to different locations of the MCU, e.g., registers, iRAM or xRAM/xSFR, depending on the preamble. The delimiter bit is not required in the packet written to the MCU, and the host needs to ensure that the RDY bit has become 1 before the host drives to the end bit.

FIG. 11 is a data packet of a "data phase" of a read operation, which may read data from different locations of the MCU, e.g., registers, iRAM or xRAM/xSFR, depending on the preamble. The slave MCU reads the switch that will direct the DDA pin driver, so there will be a separator bit (TB) and the host will be required to skip it, and the payload bit can be re-received only if the host has sampled the RDY bit to 1.

It is noted that, in the present patent application, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, the use of the verb "comprise a" to define an element does not exclude the presence of another, same element in a process, method, article, or apparatus that comprises the element. In the present patent application, if it is mentioned that a certain action is executed according to a certain element, it means that the action is executed according to at least the element, and two cases are included: performing the action based only on the element, and performing the action based on the element and other elements. The expression of a plurality of, a plurality of and the like includes 2, 2 and more than 2, more than 2 and more than 2.

The term "coupled to" and its derivatives may be used herein. "coupled" may mean that two or more elements are in direct physical or electrical contact. However, "coupled" may also mean that two or more elements are in indirect contact with each other, but yet still co-operate or interact with each other, and may mean that one or more other elements are coupled or connected between the elements that are said to be coupled to each other.

This specification includes combinations of the various embodiments described herein. Separate references to embodiments (e.g., "one embodiment" or "some embodiments" or "a preferred embodiment") do not necessarily refer to the same embodiment; however, these embodiments are not mutually exclusive, unless indicated as mutually exclusive or as would be apparent to one of ordinary skill in the art. It should be noted that the term "or" is used in this specification in a non-exclusive sense unless the context clearly dictates otherwise.

All documents mentioned in this specification are to be considered as being incorporated in their entirety into the disclosure of the present application so as to be subject to modification as necessary. It should be understood that the above description is only a preferred embodiment of the present disclosure, and is not intended to limit the scope of the present disclosure. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of one or more embodiments of the present disclosure should be included in the scope of protection of one or more embodiments of the present disclosure.

Claims

1. A method for a host and a plurality of MCUs to transmit data is characterized in that the host and the MCUs are connected in a daisy chain structure, the host and the MCUs respectively only comprise a unidirectional clock interface and a bidirectional data interface, and data packets transmitted by the data interfaces comprise: a start code, a preamble, a payload code and a stop code arranged in sequence, wherein the preamble defines the type of the data packet; the method comprises the following steps:

when the host computer reads data from the MCUs, the host computer sends clock signals and data packets with fixed periods to the MCUs, and when the host computer detects that a data interface of a target MCU is enabled, data are read out from the target MCU according to the data type defined by the lead code;

when the host writes data to the MCU, the data packet further includes: the host stops driving the data pins and continuously monitors the data pins until the data pins of the MCU are pulled to be high level, the host does not receive effective preparation code signals from the MCU within preset time, the host directly takes over the data interface, drives the data interface to be high level and finishes the data transmission;

when the host reads data from the MCU, the data packet further includes: and the host stops driving the data pin and continuously monitors the data pin until the data pin of the MCU is pulled to be at a high level, once the host detects that the data pin of the MCU is at the high level, the host starts reading data from the MCU, the host does not receive a valid preparation code signal from the MCU within preset time, directly takes over the data interface, drives the data interface to be at the high level and finishes the data transmission.

2. The method of claim 1, wherein the data packet further comprises: a CRC check code or a parity check code located between the preamble and the payload region.

3. The method of claim 1, wherein the data packet further comprises: a CRC or parity code located between the payload region and the termination code.

4. The method of claim 1, wherein the preamble has 4 bits for defining the location and mode of data reading or writing.

5. The method of claim 1, wherein the data packet further comprises a number of a target MCU.

6. An MCU, characterized in that the MCU only comprises a unidirectional clock interface and a bidirectional data interface, and the data interface transmits data packets comprising: a start code, a preamble, a payload code and a stop code arranged in sequence, wherein the preamble defines the type of the data packet;

when the data is read from the MCU, the MCU receives a clock signal and a data packet with a fixed period, and when the data interface is enabled, the data is read from the MCU according to the data type defined by the lead code;

when the host writes data to the MCU, the data packet further includes: the host stops driving the data pins and continuously monitors the data pins until the data pins of the MCU are pulled to be high level, the host does not receive effective preparation code signals from the MCU within preset time, the host directly takes over the data interface, drives the data interface to be high level and finishes the data transmission; when the host reads data from the MCU, the data packet further includes: and the host stops driving the data pin and continuously monitors the data pin until the data pin of the MCU is pulled to be at a high level, once the host detects that the data pin of the MCU is at the high level, the host starts reading data from the MCU, the host does not receive a valid preparation code signal from the MCU within preset time, directly takes over the data interface, drives the data interface to be at the high level and finishes the data transmission.