CN113498506A - Random number generation circuit, random number generation method, and electronic device - Google Patents
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Abstract
The embodiment of the disclosure provides a random number generation circuit, a random number generation method and electronic equipment, wherein the random number generation circuit comprises: a pulse generation sub-circuit configured to generate a plurality of pulses, and a frequency of the pulses varies with a variation in an environmental parameter; a frequency locked loop, the frequency locked loop comprising: a phase frequency detection sub-circuit configured to generate a phase relation indicating signal and a frequency relation indicating signal according to a phase relation between an input signal and a feedback signal, the phase relation indicating signal indicating whether a phase of the input signal is ahead of a phase of the feedback signal, the frequency relation indicating signal indicating a frequency magnitude relation between the input signal and the feedback signal; a feedback sub-circuit configured to generate the feedback signal according to a frequency relation indicating signal and a frequency of the pulse; a seed generation sub-circuit configured to generate a random number seed from the phase relationship indication signal; a random number generation sub-circuit configured to generate a random number sequence from the random number seeds.
Description
The present disclosure relates to the field of display technologies, and in particular, to a random number generation circuit, a random number generation method, and an electronic device.
Communication is one of the cornerstones of Internet of everything (Internet), and with the development of the times, communication will play an important role in future electronic systems, but Internet of everything brings network security problems at the same time. Therefore, highly secure network encryption is indispensable, and current encryption methods mainly rely on a True Random Number Generator (TRNG) in hardware for encryption using Random numbers.
Disclosure of Invention
The present disclosure is directed to at least one of the technical problems in the prior art, and provides a random number generation circuit, a random number generation method, and an electronic device.
The present disclosure provides a random number generation circuit, including:
a pulse generation sub-circuit configured to generate a plurality of pulses, and a frequency of the pulses varies with a variation in an environmental parameter;
a frequency locked loop, the frequency locked loop comprising: a phase frequency detection sub-circuit configured to generate a phase relation indicating signal and a frequency relation indicating signal according to a phase relation of an input signal and a feedback signal, wherein the phase relation indicating signal indicates whether the phase of the input signal is ahead of the phase of the feedback signal, and the frequency relation indicating signal indicates a frequency magnitude relation of the input signal and the feedback signal; a feedback sub-circuit configured to generate the feedback signal according to the frequency relation indicating signal and the frequency of the pulse;
a seed generation sub-circuit configured to generate a random number seed from the phase relationship indication signal;
a random number generation sub-circuit configured to generate a sequence of random numbers from the random number seed.
In some embodiments, the pulse generation subcircuit includes: a loop oscillator.
In some embodiments, the feedback sub-circuit comprises:
a control unit configured to generate a frequency control word according to the frequency relation indication signal;
a digital control oscillation unit configured to generate an intermediate signal having a frequency of K × F/F according to the frequency control word and the frequency of the pulses, where K is the number of the pulses generated by the pulse generation sub-circuit, F is the frequency of the pulses, and F is the frequency control word;
a first frequency dividing unit configured to frequency-divide the intermediate signal to generate the feedback signal.
In some embodiments, the frequency division coefficient of the first frequency division unit is 1.
In some embodiments, the first frequency-dividing unit is further configured to adjust a frequency-dividing coefficient of the first frequency-dividing unit according to a control parameter.
In some embodiments, the digitally controlled oscillation unit comprises: time-averaged frequency direct period synthesizer.
In some embodiments, the phase relationship indicating signal is a digital signal, and the random number seed is: a plurality of said phase relationship indicating signals are binary numbers combined from values.
In some embodiments, the random number seed is a binary number having n +1 bits, the random number generation subcircuit being specifically configured to: performing multiple right shifts on the random number seed, wherein each right shift generates a binary sequence, and the random number sequence consists of at least one binary sequence;
the first bit in the first binary sequence is generated by performing preset logic operation on the values of the last two bits of the random number seed, and the other bits in the first binary sequence are generated by right shifting the first n bits of the random number seed by one bit; the first bit in the (i + 1) th binary sequence is generated after the last two bits of the (i) th binary sequence are subjected to preset logic operation, other bits in the (i + 1) th binary sequence are generated by shifting the first n bits of the (i) th binary sequence by one bit to the right, n is an integer greater than 0, and i is an integer greater than 0 and smaller than the total number of the binary sequences.
In some embodiments, the predetermined logical operation is an exclusive or operation.
In some embodiments, the random number generation sub-circuit comprises: a pseudo-random binary sequence code generator.
In some embodiments, the phase frequency detection sub-circuit comprises:
a first input configured to receive the input signal;
a second input configured to receive the feedback signal;
a second frequency dividing unit configured to frequency-divide the input signal;
a register unit configured to acquire a plurality of signal values of an output signal of the second frequency dividing unit at a plurality of edges of the feedback signal;
a first logic unit configured to perform a logic operation on a plurality of signal values output from the register unit to output a first digital signal to a first output terminal and a second digital signal to a second output terminal when a phase of the input signal leads a phase of the feedback signal; when the phase of the input signal lags behind the phase of the feedback signal, outputting a first digital signal to the second output end and outputting a second digital signal to the first output end; the phase relation indicating signal is obtained by processing an output signal of the first output end and an output signal of the second output end according to a first logic rule;
a second logic unit configured to perform a logic operation on output signals of the first and second output terminals to output the first digital signal to a third output terminal and the second digital signal to a fourth output terminal when the frequency of the input signal is greater than the frequency of the feedback signal, and to output the second digital signal to the third output terminal and the first digital signal to the fourth output terminal when the frequency of the input signal is less than the frequency of the feedback signal; the frequency relation indicating signal is obtained by processing the output signal of the third output end and the output signal of the fourth output end according to a second logic rule.
In some embodiments, the register unit comprises: the input end of the first D trigger and the input end of the third D trigger are connected with the output end of the second frequency dividing unit, the input end of the second D trigger is connected with the output end of the first D trigger, the input end of the fourth D trigger is connected with the output end of the third D trigger, the clock end of the first D trigger, the clock end of the second D trigger and the clock end of the fourth D trigger are connected with the second input end, and the clock end of the third D trigger is connected with the second input end through a first NOT gate.
In some embodiments, the first logic unit comprises: the two input ends of the first exclusive-or gate are respectively connected with the output end of the second D trigger and the output end of the fourth D trigger, the two input ends of the second exclusive-or gate are respectively connected with the output end of the first D trigger and the output end of the fourth D trigger, the output end of the first exclusive-or gate is connected with the first output end, and the output end of the second exclusive-or gate is connected with the second output end;
the second logic unit includes: the two input ends of the first AND gate are respectively connected with the first output end and the second output end, one input end of the second AND gate is connected with the first output end through the second NOT gate, and the other output end of the second AND gate is connected with the second output end through the third NOT gate.
Correspondingly, the embodiment of the present disclosure further provides a random number generation method, including:
generating a plurality of pulses, the frequency of the pulses varying with a change in an environmental parameter;
generating a phase relation indicating signal and a frequency relation indicating signal according to the phase relation of an input signal and a feedback signal, wherein the phase relation indicating signal indicates whether the phase of the input signal leads the phase of the feedback signal, and the frequency relation indicating signal indicates the frequency magnitude relation of the input signal and the feedback signal; the feedback signal is generated according to the frequency relation indicating signal and the frequency of the pulse;
generating a random number seed according to the phase relation indication signal;
and generating a random number sequence according to the random number seed.
In some embodiments, the feedback signal is generated according to the following steps:
generating a frequency control word according to the frequency relation indication signal;
generating an intermediate signal according to the frequency control word and the frequency of the pulse, wherein the frequency of the intermediate signal is K x F/F, K is the number of the pulses generated by the pulse generation sub-circuit, F is the frequency of the pulse, and F is the frequency control word;
and dividing the frequency of the intermediate signal to generate the feedback signal.
In some embodiments, in the step of dividing the intermediate signal, the division factor is 1.
In some embodiments, the step of dividing the intermediate signal comprises: and adjusting the frequency division coefficient according to the control parameter, and dividing the frequency of the intermediate signal by using the adjusted frequency division coefficient.
In some embodiments, the phase relationship indicating signal is a digital signal, and the random number seed is: a plurality of said phase relationship indicating signals are binary numbers combined from values.
In some embodiments, the random number seed is a binary number having n +1 bits,
the step of generating a random number sequence from the random number seed comprises:
performing multiple right shifts on the random number seed, wherein each right shift generates a binary sequence, and the random number sequence consists of at least one binary sequence; the first bit in the first binary sequence is generated by performing preset logic operation on the values of the last two bits of the random number seed, and the other bits in the first binary sequence are generated by right shifting the first n bits of the random number seed by one bit; the first bit in the (i + 1) th binary sequence is generated after the last two bits of the (i) th binary sequence are subjected to preset logic operation, the other bits in the (i + 1) th binary sequence are generated by shifting the first n bits of the (i) th binary sequence by one bit to the right, n is an integer larger than 0, and i is an integer larger than 0 and smaller than the total number of the binary sequences.
Correspondingly, the embodiment of the disclosure also provides an electronic device, which includes the random number generation circuit.
The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain the disclosure without limiting the disclosure. In the drawings:
fig. 1 illustrates a schematic block diagram of a random number generation circuit, according to some embodiments of the present disclosure.
Fig. 2 illustrates a circuit diagram of a loop oscillator according to some embodiments of the present disclosure.
Fig. 3 illustrates a schematic diagram of a phase frequency detection sub-circuit in accordance with some embodiments of the present disclosure.
Fig. 4 illustrates a waveform schematic of an input signal and a feedback signal input to a phase frequency detection sub-circuit according to some embodiments of the present disclosure.
Fig. 5 illustrates a circuit diagram of a time-averaged frequency direct period synthesizer according to some embodiments of the present disclosure.
Fig. 6 illustrates a schematic diagram of time-averaged frequencies, according to some embodiments of the present disclosure.
FIG. 7 illustrates a schematic diagram of a random number generation sub-circuit, according to some embodiments of the present disclosure.
FIG. 8 illustrates a graphical effect diagram of a sequence of random numbers generated by a random number generation circuit according to some embodiments of the present disclosure.
Fig. 9 illustrates a schematic diagram of a random number generation method according to some embodiments of the present disclosure.
Fig. 10 illustrates a schematic diagram of generating a feedback signal, according to some embodiments of the present disclosure.
In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.
The terminology used herein to describe the embodiments of the disclosure is not intended to limit and/or define the scope of the disclosure. For example, unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by those of ordinary skill in the art to which this disclosure belongs. It should be understood that the use of "first," "second," and similar terms in the present disclosure are not intended to indicate any order, quantity, or importance, but rather are used to distinguish one element from another. The singular forms "a," "an," or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one, unless the context clearly dictates otherwise.
It will be further understood that the terms "comprises" or "comprising," and the like, mean that the element or item identified as preceding the term, includes the element or item identified as following the term, and equivalents thereof, without excluding other elements or items. The terms "connected" or "coupled," and the like, are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.
In a first aspect, embodiments of the present disclosure provide a random number generation circuit, fig. 1 shows a schematic block diagram of a random number generation circuit according to some embodiments of the present disclosure, and as shown in fig. 1, the random number generation circuit includes: a pulse generation sub-circuit 10, a frequency locked loop circuit, a seed generation sub-circuit 40 and a random number generation sub-circuit 50.
The pulse generating sub-circuit 10 is configured to generate a plurality of pulses, and the frequency of the pulses generated by the pulse generating sub-circuit 10 varies with the variation of the environmental parameter. For example, the pulse generating sub-circuit 10 is an oscillator, the oscillation frequency of which drifts with the change of environmental parameters (e.g., temperature).
The frequency-locked loop is a time-averaged frequency-locked loop (TAF-FLL) loop configured to lock a frequency of the input signal and a frequency of the feedback signal. The frequency locking loop comprises: a phase frequency detection sub-circuit 20 and a feedback sub-circuit 30. The phase frequency detection sub-circuit 20 is configured to generate a phase relationship indicating signal indicating whether the phase of the input signal leads the phase of the feedback signal fb and a frequency relationship indicating signal indicating the magnitude relationship between the frequency fi of the input signal and the frequency fb of the feedback signal, according to the phase relationship between the input signal (whose frequency is fi) and the feedback signal (whose frequency is fb). The feedback sub-circuit 30 is configured to generate a feedback signal fb in dependence on the frequency relation indicating signal and the frequency of the pulses.
In the disclosed embodiments, the input signal may be generated by an external Crystal Oscillator (Crystal), or by a Micro-Electro-Mechanical System (MEMS), or by an Oscillator (e.g., Ring Oscillator (RO)).
In the embodiment of the present disclosure, the input signal fi of the input phase-locked loop circuit is easy to jitter under the interference of thermal noise, and meanwhile, the frequency of the pulse generated by the pulse generating sub-circuit 10 also drifts with the change of the environmental parameter, and no matter how the input signal jitters or the pulse frequency drifts, the feedback sub-circuit 30 makes the frequency fb of the feedback signal consistent with the frequency fi of the input signal according to the magnitude relationship between the frequency of the input signal and the frequency of the feedback signal. Due to jitter of the input signal and drift of the pulse frequency, the phase of the input signal and the phase of the feedback signal received by the phase frequency and phase discriminator circuit 20 have high uncertainty, so that the phase relationship indicating signal generated according to the phase relationship has high uncertainty, thereby improving the randomness of the random number seed generated according to the phase relationship indicating signal, further improving the randomness of the generated random number, and realizing the generation of the true random number.
In some embodiments, the pulse generating sub-circuit 10 comprises a loop oscillator 11, for example an oscillator based on CROSS-cascaded NAND GATEs (CROSS NAND GATEs). Fig. 2 illustrates a circuit diagram of a loop oscillator according to some embodiments of the present disclosure, and as shown in fig. 2, the loop oscillator 11 includes a cross-cascade of 8-stage nand gate units (P0-P15), each stage including a pair of nand gates. The loop oscillator 11 generates a plurality of pulses that are evenly spaced in phase. The loop oscillator 11 is most characterized by instability, random initial oscillation conditions, and environmental sensitivity of the oscillation frequency, which shifts when the temperature changes slightly.
In some embodiments, the Phase Frequency Detector sub-circuit 20 employs a Phase Frequency Detector (PFD), fig. 3 illustrates a schematic diagram of a Phase Frequency Detector sub-circuit according to some embodiments of the present disclosure, and as shown in fig. 3, the Phase Frequency Detector sub-circuit 20 includes: a first input terminal, a second input terminal, a first output terminal out1, a second output terminal out2, a third output terminal out3, a fourth output terminal out4, a second frequency-dividing unit 21, a register unit 22, a first logic unit 23 and a second logic unit 24. The first input is configured to receive an input signal having a frequency fi. The second input terminal is configured to receive a feedback signal having a frequency fb. The second frequency dividing unit 21 is configured to divide the frequency of the input signal. For example, the second frequency dividing unit 21 employs a frequency divider.
The register unit 22 is configured to obtain a plurality of signal values of the output signal of the second frequency dividing unit 21 at a plurality of edges of the feedback signal. For example, the signal values of the second frequency-dividing unit 21 at two adjacent rising edges of the feedback signal and a falling edge between the two rising edges are obtained.
For example, the register unit 22 includes: the input end of the first D flip-flop 221 and the input end of the third D flip-flop 223 are connected to the output end of the second frequency dividing unit 21, the input end of the second D flip-flop 222 is connected to the output end of the first D flip-flop 221, the input end of the fourth D flip-flop 224 is connected to the output end of the third D flip-flop 223, the clock end of the first D flip-flop 221, the clock end of the second D flip-flop 222 and the clock end of the fourth D flip-flop 224 are connected to the second input end, and the clock end of the third D flip-flop 223 is connected to the second input end through the first not gate 25.
The first logic unit 23 is connected to the first output terminal out1 and the second output terminal out2, the first logic unit 23 is configured to perform a logic operation on a plurality of signal values output from the register unit 22, so as to output a first digital signal to the first output terminal out1 and a second digital signal to the second output terminal out2 when the phase of the input signal leads the phase of the feedback signal; and outputs the first digital signal to the second output terminal out2 and the second digital signal to the first output terminal out1 when the phase of the input signal lags the phase of the feedback signal. The phase relation indicating signal is obtained by processing the output signal of the first output terminal out1 and the output signal of the second output terminal out2 according to the first logic rule.
For example, the first logical rule is: when the first output terminal out1 outputs the first digital signal and the second output terminal out2 outputs the second digital signal, the phase relation indicating signal is set to the first digital signal; when the first output terminal out1 outputs the second digital signal and the second output terminal out2 outputs the first digital signal, the phase relation indicating signal is set to the second digital signal; when the phase relation indicating signal is a first digital signal, the phase of the indicating input signal is ahead of the phase of the feedback signal; when the phase relation indicating signal is the second digital signal, the phase relation indicating signal indicates that the phase of the input signal lags behind the phase of the feedback signal. For example, the first digital signal has a value of 1, the second digital signal has a value of 0, and when the output signal of the first output terminal out1 has a value of 1 and the output signal of the second output terminal out2 has a value of 0, the phase relationship indicating signal has a value of 1; when the value of the output signal of the first output terminal out1 is 0 and the value of the output signal of the second output terminal out2 is 1, the value of the phase relation indicating signal is 0; when both the values of the output signal of the first output terminal out1 and the output signal of the second output terminal out2 are 1 or 0, they are discarded. When the value of the phase relation indicating signal is 1, indicating that the phase of the input signal leads the phase of the feedback signal; when the phase relation indicating signal has a value of 0, it indicates that the phase of the input signal lags the phase of the feedback signal.
The second logic unit 24 is connected to the third output terminal out3 and the fourth output terminal out4, and the second logic unit 24 is configured to perform a logic operation on the output signals of the first output terminal out1 and the second output terminal out2 to output a first digital signal to the third output terminal out3 and a second digital signal to the fourth output terminal out4 when the frequency of the input signal is greater than the frequency of the feedback signal, to output the second digital signal to the third output terminal out3 and to output the first digital signal to the fourth output terminal out4 when the frequency fi of the input signal is less than the frequency fb of the feedback signal. The frequency relation indicating signal is obtained by processing the output signal of the third output terminal out3 and the output signal of the fourth output terminal out4 according to a second logic rule.
For example, the second logical rule is: when the third output terminal out3 outputs the first digital signal and the fourth output terminal out4 outputs the second digital signal, the frequency relationship indicating signal is set to the first digital signal; when the third output terminal out3 outputs the second digital signal and the fourth output terminal out4 outputs the first digital signal, the frequency indication signal is set to the second digital signal; when the frequency relation indicating signal is a first digital signal, indicating that the frequency of the input signal is greater than the frequency of the feedback signal; when the frequency relation indicating signal is the second digital signal, the frequency of the indicating input signal is smaller than the frequency of the feedback signal. For example, the first digital signal has a value of 1, the second digital signal has a value of 0, and when the output signal of the third output terminal out3 has a value of 1 and the output signal of the fourth output terminal out4 has a value of 0, the frequency relation indicator signal has a value of 1; when the value of the output signal of the third output terminal out3 is 0 and the value of the output signal of the fourth output terminal out4 is 1, the value of the frequency relationship indicating signal is 0; when both the values of the output signal of the third output terminal out3 and the output signal of the fourth output terminal out4 are 0 or 1, they are discarded. When the value of the frequency relation indicating signal is 1, indicating that the frequency fi of the input signal is greater than the frequency fb of the feedback signal; when the value of the frequency relation indicating signal is 0, it indicates that the frequency fi of the input signal is less than the frequency fb of the feedback signal.
In some embodiments, as shown in FIG. 3, register unit 22 includes: the input end of the first D flip-flop 221 and the input end of the third D flip-flop 223 are connected to the output end of the second frequency dividing unit 21, the input end of the second D flip-flop 222 is connected to the output end of the first D flip-flop 221, the input end of the fourth D flip-flop 224 is connected to the output end of the third D flip-flop 223, the clock end of the first D flip-flop 221, the clock end of the second D flip-flop 222 and the clock end of the fourth D flip-flop 224 are connected to the second input end, and the clock end of the third D flip-flop 223 is connected to the second input end through the first not gate 25.
The first logic unit 23 includes: a first xor gate 231 and a second xor gate 232, wherein two input terminals of the first xor gate 231 are respectively connected to the output terminal of the second D flip-flop 222 and the output terminal of the fourth D flip-flop 224, two input terminals of the second xor gate 232 are respectively connected to the output terminal of the first D flip-flop 221 and the output terminal of the fourth D flip-flop 224, an output terminal of the first xor gate 231 is connected to the first output terminal out1, and an output terminal of the second xor gate 232 is connected to the second output terminal 2. The second logic unit 24 includes: a second not gate 241, a third not gate 242, a first and gate 243 and a second and gate 244, wherein two input terminals of the first and gate 243 are respectively connected with a first output terminal out1 and a second output terminal out2, one input terminal of the second and gate 244 is connected with the first output terminal out1 through the second not gate 241, and the other output terminal of the second and gate 244 is connected with the second output terminal through the third not gate 242.
Fig. 4 is a schematic diagram showing waveforms of an input signal and a feedback signal of an input phase frequency detector sub-circuit according to some embodiments of the present disclosure, where, as shown in fig. 4, a solid line in an upper part indicates a waveform of an ideal input signal, a solid line in a lower part indicates a waveform of an ideal feedback signal, both the input signal and the feedback signal may be jittered by respective noise, and a dotted line indicates a boundary of a pulse edge when the input signal/feedback signal is interfered by the noise, and a probability of the pulse edge occurring at any position within the dotted line is the same. Uncertainty will arise in the phase frequency detector sub-circuit 20 when determining the phase relationship of the input signal and the output signal. For example, the phase of the input signal may lead the phase of the feedback signal, the phase of the input signal may lag the phase of the feedback signal, or the input signal may coincide with the feedback phase. In the phase frequency and phase detector circuit 20 shown in fig. 3, the feedback signal (or the inverted signal thereof) is used as the clock signal of the first D flip-flop 221 to the fourth D flip-flop 224, and the input signal of the phase frequency and phase detector circuit 20 is used as the input signal of the first D flip-flop 221 and the third D flip-flop 223, when the phases of the input signal of the D flip-flop and the clock signal are extremely close, the D flip-flop is in a metastable state, and there is a possibility that 0 or 1 is output, so that the uncertainty of the phase relation indicating signal generated by the phase frequency and phase detector circuit 20 is increased, and the randomness of the random number generated according to the phase relation indicating signal is improved.
In some embodiments, the feedback sub-circuit 30 includes: a control unit 31, a digitally controlled oscillation unit 32 and a first frequency dividing unit 33.
The control unit 31 is configured to generate a frequency control word F according to the frequency relation indication signal output by the phase frequency detection sub-circuit 20. For example, the control unit 31 reads an initial frequency control word F from the storage device, and when the frequency relationship indication signal indicates that the frequency fi of the input signal is greater than the frequency fb of the feedback signal, the control unit 31 decreases the current frequency control word by 1; when the frequency relation indicating signal indicates that the frequency of the input signal fi is less than the frequency of the feedback signal fb, the control unit 31 increases the current frequency control word by 1.
The digitally controlled oscillation unit 32 is configured to generate an intermediate signal having a frequency fo ═ K × F/F, according to the frequency control word and the frequency of the pulses generated by the pulse generating sub-circuit 10, where K is the number of pulses generated by the pulse generating sub-circuit 10, F is the frequency of said pulses, and F is the frequency control word.
The first frequency dividing unit 33 is configured to frequency-divide the intermediate signal, generating the above-mentioned feedback signal.
In some embodiments, the digitally controlled oscillation unit 32 employs a Time-averaged Frequency Direct Period synthesizer (TAF-DPS) based on a Time-averaged Frequency Direct Period Synthesis (TAF-DPS) circuit architecture. Fig. 5 illustrates a circuit diagram of a time-averaged frequency direct period synthesizer according to some embodiments of the present disclosure, as shown in fig. 5, a time-averaged frequency direct period synthesizer 320 may include a first input module, a second input module 3230, and an output module 3240.
For example, as shown in fig. 5, the first input module includes a first logic control circuit 3210 and a second logic control circuit 3220. The first logic control circuit 3210 includes a first adder 3211, a first register 3212, and a second register 3213. The second logic control circuit 3220 may include a second adder 3221, a third register 3222, and a fourth register 3223.
The second input module 3230 includes a first K → 1 multiplexer 3231, a second K → 1 multiplexer 3232, and a 2 → 1 multiplexer 3233. The first K → 1 multiplexer 3231 and the second K → 1 multiplexer 3232 each include a plurality of input terminals, control input terminals, and output terminals. A plurality of input terminals of the first K → 1 multiplexer 3231 and the second K → 1 multiplexer 3232 are respectively used for receiving K (K is an integer greater than 1) phase-uniformly spaced pulses output from the pulse generating sub-circuit. The 2 → 1 multiplexer 3233 includes a control input, an output, a first input for receiving the output of the first K → 1 multiplexer 3231, and a second input for receiving the output of the second K → 1 multiplexer 3232. For example, the time span (e.g., phase difference) between any two adjacent ones of the K uniformly phase spaced pulses may be the reference time unit Δ.
For example, as shown in fig. 5, the output module 3240 includes a flip-flop circuit. The trigger circuit is used for generating a pulse train. The flip-flop circuit includes a D flip-flop 3241, a first inverter 3242, and a second inverter 3243. The D flip-flop 3241 includes a data input, a clock input for receiving an output from the output of the 2 → 1 multiplexer 3233, and an output for outputting a first clock signal CLK 1. The first inverter 3242 includes an input for receiving a first clock signal CLK1 and an output for outputting a signal to a data input of the D flip-flop 3241. The second inverter 3243 includes an input for receiving the first clock signal CLK1 and an output for outputting the second clock signal CLK 2.
The first clock signal CLK1 is output to a control input of the 2 → 1 multiplexer 3233, and an output of the first inverter 3242 is connected to a data input of the D flip-flop 3241.
For example, the first adder 3211 may add the frequency control word F and most significant bits (e.g., 5 bits) stored in the first register 3212, and then save the addition result into the first register 3212 at the rising edge of the second clock signal CLK 2; alternatively, the first adder 3211 may add the frequency control word F and all the information stored by the first register 3212, and then save the addition result into the first register 3212 at the rising edge of the second clock signal CLK 2. On the next rising edge of the second clock signal CLK2, the most significant bit stored by the first register 3212 will be stored in the second register 3213 and serve as the select signal for the first K → 1 multiplexer 3231 for selecting one of the K pulses as the output signal of the first K → 1 multiplexer 3231.
For example, the second adder 3221 may add the frequency control word F/2 and the most significant bit stored by the first register 3212, and then save the addition result into the third register 3222 at the rising edge of the second clock signal CLK 2. At the next rising edge of the first clock signal CLK1, the information stored by the third register 3222 will be stored into the fourth register 3223 and serve as a selection signal for the second K → 1 multiplexer 3223 for selecting one pulse from the K pulses as the output signal of the second K → 1 multiplexer 3223.
The 2 → 1 multiplexer 3233 may select one of the output signal from the first K → 1 multiplexer 3231 and the output signal from the second K → 1 multiplexer 3232 as the output signal of the 2 → 1 multiplexer 3233 at the rising edge of the first clock signal CLK1 as the input clock signal of the D flip-flop 3241.
For example, one of the output of the D flip-flop 3241 and the output of the second inverter 3243 may serve as the output of the time-averaged frequency direct period synthesizer 320.
For example, the selection signal output by the second register 3213 may be used to select a falling edge of the generated synthesized clock signal of the time-averaged frequency direct period synthesizer 320, the selection signal output by the fourth register 3223 may be used to select a rising edge of the generated synthesized clock signal of the time-averaged frequency direct period synthesizer 320, and the signal fed back to the first adder 3211 by the first register 3212 may be used to control the period switching of the generated synthesized clock of the time-averaged frequency direct period synthesizer 320.
Time-averaged Frequency direct period synthesizer 320 generates an intermediate signal based on a Time-averaged Frequency (TAF), a schematic of which is shown in fig. 6 according to some embodiments of the present disclosure. Referring to FIGS. 5 and 6, the output of the time-averaged frequency direct periodic synthesizer 320 has two outputs, one of which isThe periods are respectively the first period TAAnd a second period TB. As shown in fig. 6, two time periods can be obtained for the reference time unit Δ and the frequency control word F ═ I + r: first period TAAnd a second period TB. First period TAAnd a second period TBCan be expressed by the following formula (1) and formula (2), respectively. Where I is the integer part of the frequency control word F and r is the fractional part of the frequency control word F.
T A＝I·Δ (1)
T B＝(I+1)·Δ (2)
Using a first period TAAnd a second period TBClock signals comprising two different periods (different frequencies) may be generated in an interleaved manner. The average period of the generated clock signal is TTAFAverage frequency fTAFAs shown in the following equation (3).
Where f is the frequency of the pulses, and K is the number of pulses generated by the pulse generation sub-circuit 10. The time-averaged frequency direct periodic synthesizer 320 is characterized in that: by varying the frequency of the frequency control word F, the frequency F of the generated clock signalTAFI.e. the frequency switching can be done after two cycles.
The time averaged frequency direct period synthesizer 320, based on the operation mode of the TAF, causes the frequency of the output signal to vary between two frequencies, and therefore the phase of the intermediate signal varies, and this variation of the phase causes the randomness of the output signal of the phase frequency and phase detector sub-circuit 20 to increase, thereby further increasing the randomness of generating random numbers.
In some embodiments, the first frequency-dividing unit 33 employs a frequency divider.
In order to transmit the noise of the pulse generation sub-circuit 10 into the phase frequency detection sub-circuit 20, in some embodiments, the frequency division coefficient of the first frequency division unit 33 is set to a smaller value, for example, the frequency division coefficient N is 1.
In some embodiments, in order to increase the randomness of the output signal of the phase frequency detection sub-circuit 20, the first frequency dividing unit 33 is arranged as a dither circuit, e.g. the first frequency dividing unit 33 is further configured to adjust the frequency dividing coefficient of the first frequency dividing unit 33 according to a control parameter.
For example, the control parameter is generated by a parameter generation circuit, which may be the same circuit as the random number generation sub-circuit 50, and the value of each random number in the random number sequence generated by the random number generation sub-circuit 50 is used as the control parameter. For example, when the random number generation sub-circuit 50 outputs 0, the frequency division coefficient of the first frequency dividing unit 33 is adjusted to 2; when the random number generation sub-circuit 50 outputs 1, the frequency division coefficient of the first frequency dividing unit 33 is adjusted to 1. For another example, when the random number generation sub-circuit 50 continuously outputs 0, the frequency division coefficient of the first frequency division unit 33 is adjusted to 2; when the random number generation sub-circuit 50 continuously outputs 0, 1, the frequency division coefficient of the first frequency division unit 33 is adjusted to 1; when the random number generation sub-circuit 50 continuously outputs 1, 0, the frequency division coefficient of the first frequency division unit 33 is adjusted to 3. Of course, the parameter generation circuit may be a circuit other than the random number generation sub-circuit 50.
In some embodiments, the phase relationship indicating signal is a digital signal, and the random number seed is a binary number obtained by combining values of the plurality of phase relationship indicating signals. In the embodiment of the present disclosure, a signal of 0 means that the value of the signal is 0, and a signal of 1 means that the value of the signal is 1.
For example, the value of the phase relation indicating signal is 0 or 1; when the value of the phase relation indicating signal is 0, the phase of the indicating input signal lags behind the phase of the feedback signal, and when the value of the phase relation indicating signal is 1, the phase of the indicating input signal leads the phase of the feedback signal.
For example, the phase frequency detection sub-circuit 20 performs m (for example, m is 10) phase comparisons within a predetermined time period to generate m phase relationship indicating signals, values of the m phase relationship indicating signals are 0, 1, 0, 1, and 0, respectively, and a digital signal sequence composed of values of the m phase relationship indicating signals constitutes a random number seed, that is, 0110011110. It should be understood that m is merely exemplary, and in practical applications, m may take a larger value, thereby generating a random number seed with a larger number of bits, for example, 64 is, 128 bits, 256 bits, etc., thereby increasing the complexity of the random number generated by the random number generation sub-circuit 50.
In some embodiments, the random number seed is a binary number having n +1 bits, the random number generation sub-circuit 50 is specifically configured to: and performing right shift on the random number seed for multiple times, wherein each right shift generates a binary sequence, and the random number sequence consists of at least one binary sequence. The first bit in the first binary sequence is generated by performing preset logic operation on the values of the last two bits of the random number seed, and the other bits in the first binary sequence are generated by right shifting the first n bits of the random number seed by one bit; the first bit in the (i + 1) th binary sequence is generated after the last two bits of the (i) th binary sequence are subjected to preset logic operation, the other bits in the (i + 1) th binary sequence are generated by shifting the first n bits of the (i) th binary sequence by one bit to the right, n is an integer larger than 0, and i is an integer larger than 0 and smaller than the total number of the binary sequences. It should be noted that the first bit in the binary sequence is the highest bit in the binary sequence, and the last two bits of the random number seed are the lowest bit and its adjacent bits in the plurality of bits of the random number seed.
For example, the random number generation sub-circuit 50 includes: a pseudo-random binary sequence code generator. Fig. 7 shows a schematic diagram of a random number generation sub-circuit, according to some embodiments of the present disclosure, as shown in fig. 7, the random number generation sub-circuit 51 includes: the random number seed SG comprises a logic operation unit 512, a shift register and a plurality of data selectors 513, the bit number of the bit of the random number seed SG is n +1, the shift register comprises n + 1-level D flip-flops 514, the input ends of the n + 1-level D flip-flops 514 are connected with the output ends o1 of the n + 1-level data selectors 513 in a one-to-one correspondence mode, specifically, the input end of the 1 st-level D flip-flop 514 is connected with the output end o1 of the 1 st data selector 513, the input end 514 of the 2 nd-level D flip-flop is connected with the output end o1 of the 2 nd data selector 513, and so on until the input end of the n + 1-level D flip-flop 514 is connected with the output end o1 of the n + 1-level data selector 513. The first input i1 of the 1 st data selector 513 is connected to the output of the logic operation unit 512, and the first input i1 of the jth data selector 513 is connected to the output of the j-1 th D flip-flop 514, where j is an integer and is 1< j ≦ n + 1. The n +1 bit values of the random number seed SG are respectively input to the second input terminals i2 of the n +1 data selectors 512, and two input terminals of the logic operation unit 512 are respectively connected to the output terminals of the two stages of D flip-flops 514. When the random number generation sub-circuit 51 is triggered to generate a random number, the second input terminal i2 and the output terminal o1 of each data selector 513 are controlled to be turned on, so that n + 1-bit data of the random number seed SG is input to the input terminals of the n + 1-stage D flip-flops 514, respectively, and thereafter, the first input terminal i1 and the output terminal o1 of each data selector 513 are controlled to be turned on. Each bit in the binary sequence output by the n +1 stage D flip-flop 514 is denoted as prbs [0], prbs [1] … … prbs [ n ], prbs [ n-1] and prbs [ n ] which are input to two input terminals of the logical operation unit 512.
For example, the random number generation sub-circuit 51 sequentially arranges a plurality of binary sequences generated by right-shifting a plurality of times to constitute the random number sequence, with the first bit prbs [0] of the first binary sequence being the first bit of the random number sequence, and the last bit prbs [ n ] of the last binary sequence being the last bit of the random number sequence.
For example, the random number seed is 01100010, and the binary sequence generated by the random number generation sub-circuit 51 after performing the first right shift operation is: 10110001, respectively; the binary sequence generated by performing the second right shift operation is as follows: 11011000; the binary sequence generated by performing the third right shift operation is as follows: 01101100, respectively; the binary sequence generated by performing the fourth right shift operation is: 00110110, and so on. The random number sequence is formed by sequentially arranging four binary sequences according to a generation sequence, namely the random number sequence is 10110001110110000110110000110110.
Fig. 8 is a schematic diagram illustrating the imaging effect of the random number sequence generated by the random number generation circuit according to some embodiments of the present disclosure, where the random number sequence generated by the random number generation circuit includes 65536 bits of random numbers, each bit of random number is 0 or 1, the image size of fig. 8 is 256 × 256, and includes 65536 pixels in total, each pixel corresponds to one random number, the gray level of each pixel is determined by the value of the corresponding random number, when the random number is 0, the pixel is black, and when the random number is 1, the pixel is white. It can be seen from fig. 8 that the random number distribution of the random number sequence satisfies the white noise requirement without a distinct pattern.
Most of the random number generators in the prior art include analog circuits, which have long production period and high cost, but in the embodiment of the disclosure, all parts of the random number generator are digital circuits, which have the characteristics of low power consumption and low cost, and are beneficial to being integrated in various chips, and the random number generator has high randomness for generating random numbers, and can provide higher safety and reliability in the communication process.
In a second aspect, the present disclosure also provides a random number generation method, and fig. 9 shows a schematic diagram of a random number generation method according to some embodiments of the present disclosure, which may be performed by the random number generation circuit described above. As shown in fig. 9, the random number generation method in the embodiment of the present disclosure includes the following steps S10 to S40.
And step S10, generating a plurality of pulses, wherein the frequency of the pulses changes along with the change of the environmental parameters.
Step S20, a phase relation indicating signal and a frequency relation indicating signal are generated according to the phase relation between the input signal and the feedback signal, the phase relation indicating signal indicates whether the phase of the input signal leads the phase of the feedback signal, and the frequency relation indicating signal indicates the frequency magnitude relation between the input signal and the feedback signal. The feedback signal is generated in accordance with the frequency relationship indicating signal and the frequency of the pulse.
For example, the phase relationship indicating signal is obtained by processing the output signal of the first output terminal out1 and the output signal of the second output terminal out2 of the phase frequency detection sub-circuit 20 in fig. 3 according to the first logic rule. The output signal of the first output terminal out1, the output signal of the second output terminal out2, and the phase relationship indicating signal are all digital signals. For example, the first digital signal has a value of 1, the second digital signal has a value of 0, and the first rule is: when the value of the output signal of the first output terminal out1 is 1 and the value of the output signal of the second output terminal out2 is 0, the value of the phase relation indicating signal is 1; when the value of the output signal of the first output terminal out1 is 0 and the value of the output signal of the second output terminal out2 is 1, the value of the phase relation indicating signal is 0; when both the value of the output signal of the first output terminal out1 and the value of the output signal of the second output terminal out2 are 1 or 0, they are discarded. When the value of the phase relation indicating signal is 1, indicating that the phase of the input signal leads the phase of the feedback signal; when the phase relation indicating signal has a value of 0, it indicates that the phase of the input signal lags the phase of the feedback signal.
Fig. 10 illustrates a schematic diagram of generating a feedback signal according to some embodiments of the present disclosure, as illustrated in fig. 10, the feedback signal is generated according to the following steps S21 to S23.
And step S21, generating a frequency control word according to the frequency relation indicating signal.
For example, step S21 is executed by the control unit 31 in fig. 1. Before step S21, an initial frequency control word is obtained, and in step S21, when the frequency relationship indication signal indicates that the frequency fi of the input signal is greater than the frequency fb of the feedback signal, the control unit 31 decreases the current frequency control word by 1; when the frequency relation indicating signal indicates that the frequency of the input signal fi is less than the frequency of the feedback signal fb, the current frequency control word is increased by 1.
And step S22, generating an intermediate signal according to the frequency control word and the frequency of the pulse, wherein the frequency of the intermediate signal is K x F/F, K is the number of the pulses generated by the pulse generating sub-circuit, F is the frequency of the pulses generated in the step S10, and F is the frequency control word.
Step S23 is to divide the frequency of the intermediate signal to generate a feedback signal.
For example, in step S23, the frequency division coefficient for dividing the intermediate signal is 1; for another example, step S23 includes: and adjusting the frequency division coefficient according to the control parameter, and dividing the frequency of the intermediate signal by using the adjusted frequency division coefficient.
And step S30, generating a random number seed according to the phase relation indicating signal.
In one embodiment, the phase relationship indicating signal is a digital signal, and the random number seed is: and a digital signal sequence formed by combining the plurality of phase relation indicating signals. For example, the phase relation indicating signal has a value of 0 or 1, the phase relation indicating signal has a value of 0, which indicates that the phase of the input signal lags the phase of the feedback signal, and the phase relation indicating signal has a value of 1, which indicates that the phase of the input signal leads the phase of the feedback signal.
For example, when m (for example, m is 10) phase comparisons are performed by the phase frequency detection sub-circuit within a predetermined time period to generate m phase relationship indicating signals, the values of the m phase relationship indicating signals are 0, 1, 0, 1, and 0, respectively, and a digital signal sequence composed of the m phase relationship indicating signals constitutes a random number seed, that is, 0110011110. It should be understood that m is merely exemplary, and in practical applications, m may take a larger value, thereby generating a random number seed with a larger number of bits, such as 64 bits, 128 bits, 256 bits, etc., thereby increasing the randomness of the random number generation sub-circuit.
Step S40, a random number sequence is generated from the random number seeds.
For example, the random number seed is a binary number having a plurality of bits. In some embodiments, step S40 is performed by the pseudo random binary sequence code generator, and step S40 includes: performing right shift on values of a plurality of bits of the random number seed for a plurality of times, wherein each right shift generates a binary sequence, and the random number sequence consists of at least one binary sequence; the first bit in the first binary sequence is generated by performing preset logic operation on the values of the last two bits of the random number seed, and the other bits in the first binary sequence are generated by right shifting the first n bits of the random number seed by one bit; the first bit in the (i + 1) th binary sequence is generated after the last two bits of the (i) th binary sequence are subjected to preset logic operation, the other bits in the (i + 1) th binary sequence are generated by shifting the first n bits of the (i) th binary sequence by one bit to the right, n is an integer larger than 0, and i is an integer larger than 0 and smaller than the total number of the binary sequences.
In a third aspect, an embodiment of the present disclosure further provides an electronic device, where the electronic device includes the random number generation circuit provided in the embodiment of the present disclosure.
The electronic device in the embodiments of the present disclosure may be a chip in a communication device. The random number generation circuit provided by the embodiment of the disclosure adopts digital circuits in all parts, so that the random number generation circuit can be easily integrated in various chips.
The random number generating circuit in the embodiment of the disclosure generates the random number with a high degree of randomness, thereby improving the security and reliability of the electronic device in communication.
It is to be understood that the above embodiments are merely exemplary embodiments that are employed to illustrate the principles of the present disclosure, and that the present disclosure is not limited thereto. It will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the disclosure, and these are to be considered as the scope of the disclosure.
Claims (20)
- A random number generation circuit, comprising:a pulse generation sub-circuit configured to generate a plurality of pulses, and a frequency of the pulses varies with a variation in an environmental parameter;a frequency locked loop, the frequency locked loop comprising: a phase frequency detection sub-circuit configured to generate a phase relation indicating signal and a frequency relation indicating signal according to a phase relation of an input signal and a feedback signal, wherein the phase relation indicating signal indicates whether the phase of the input signal is ahead of the phase of the feedback signal, and the frequency relation indicating signal indicates a frequency magnitude relation of the input signal and the feedback signal; a feedback sub-circuit configured to generate the feedback signal according to the frequency relation indicating signal and the frequency of the pulse;a seed generation sub-circuit configured to generate a random number seed from the phase relationship indication signal;a random number generation sub-circuit configured to generate a sequence of random numbers from the random number seed.
- The random number generation circuit of claim 1, wherein the pulse generation subcircuit comprises: a loop oscillator.
- The random number generation circuit of claim 1, wherein the feedback sub-circuit comprises:a control unit configured to generate a frequency control word according to the frequency relation indication signal;a digital control oscillation unit configured to generate an intermediate signal having a frequency of K × F/F according to the frequency control word and the frequency of the pulses, where K is the number of the pulses generated by the pulse generation sub-circuit, F is the frequency of the pulses, and F is the frequency control word;a first frequency dividing unit configured to frequency-divide the intermediate signal to generate the feedback signal.
- The random number generation circuit of claim 3, wherein a division coefficient of the first division unit is 1.
- The random number generation circuit of claim 3, wherein the first frequency-dividing unit is further configured to adjust a frequency-dividing coefficient of the first frequency-dividing unit according to a control parameter.
- The random number generation circuit of claim 3, wherein the digitally controlled oscillation unit comprises: time-averaged frequency direct period synthesizer.
- The random number generation circuit of claim 1, wherein the phase relationship indication signal is a digital signal, the random number seed being: a plurality of said phase relationship indicating signals are binary numbers combined from values.
- The random number generation circuit of claim 1, wherein the random number seed is a binary number having n +1 bits, the random number generation sub-circuit being specifically configured to: performing multiple right shifts on the random number seed, wherein each right shift generates a binary sequence, and the random number sequence consists of at least one binary sequence;the first bit in the first binary sequence is generated by performing preset logic operation on the values of the last two bits of the random number seed, and the other bits in the first binary sequence are generated by right shifting the first n bits of the random number seed by one bit; the first bit in the (i + 1) th binary sequence is generated after the last two bits of the (i) th binary sequence are subjected to preset logic operation, the other bits in the (i + 1) th binary sequence are generated by shifting the first n bits of the (i) th binary sequence by one bit to the right, n is an integer larger than 0, and i is an integer larger than 0 and smaller than the total number of the binary sequences.
- The random number generation circuit of claim 8, wherein the predetermined logical operation is an exclusive or operation.
- The random number generation circuit of claim 8, wherein the random number generation sub-circuit comprises: a pseudo-random binary sequence code generator.
- The random number generation circuit of claim 1, wherein the phase frequency detection sub-circuit comprises:a first input configured to receive the input signal;a second input configured to receive the feedback signal;a second frequency dividing unit configured to frequency-divide the input signal;a register unit configured to acquire a plurality of signal values of an output signal of the second frequency dividing unit at a plurality of edges of the feedback signal;a first logic unit configured to perform a logic operation on a plurality of signal values output from the register unit to output a first digital signal to a first output terminal and a second digital signal to a second output terminal when a phase of the input signal leads a phase of the feedback signal; when the phase of the input signal lags behind the phase of the feedback signal, outputting a first digital signal to the second output end and outputting a second digital signal to the first output end; the phase relation indicating signal is obtained by processing an output signal of the first output end and an output signal of the second output end according to a first logic rule;a second logic unit configured to perform a logic operation on output signals of the first and second output terminals to output the first digital signal to a third output terminal and the second digital signal to a fourth output terminal when the frequency of the input signal is greater than the frequency of the feedback signal, and to output the second digital signal to the third output terminal and the first digital signal to the fourth output terminal when the frequency of the input signal is less than the frequency of the feedback signal; the frequency relation indicating signal is obtained by processing the output signal of the third output end and the output signal of the fourth output end according to a second logic rule.
- The random number generation circuit of claim 11, wherein the register unit comprises: the input end of the first D trigger and the input end of the third D trigger are connected with the output end of the second frequency dividing unit, the input end of the second D trigger is connected with the output end of the first D trigger, the input end of the fourth D trigger is connected with the output end of the third D trigger, the clock end of the first D trigger, the clock end of the second D trigger and the clock end of the fourth D trigger are connected with the second input end, and the clock end of the third D trigger is connected with the second input end through a first NOT gate.
- The random number generation circuit of claim 12, wherein the first logic unit comprises: the two input ends of the first exclusive-or gate are respectively connected with the output end of the second D trigger and the output end of the fourth D trigger, the two input ends of the second exclusive-or gate are respectively connected with the output end of the first D trigger and the output end of the fourth D trigger, the output end of the first exclusive-or gate is connected with the first output end, and the output end of the second exclusive-or gate is connected with the second output end;the second logic unit includes: the two input ends of the first AND gate are respectively connected with the first output end and the second output end, one input end of the second AND gate is connected with the first output end through the second NOT gate, and the other output end of the second AND gate is connected with the second output end through the third NOT gate.
- A random number generation method, comprising:generating a plurality of pulses, the frequency of the pulses varying with a change in an environmental parameter;generating a phase relation indicating signal and a frequency relation indicating signal according to the phase relation of an input signal and a feedback signal, wherein the phase relation indicating signal indicates whether the phase of the input signal leads the phase of the feedback signal, and the frequency relation indicating signal indicates the frequency magnitude relation of the input signal and the feedback signal; the feedback signal is generated according to the frequency relation indicating signal and the frequency of the pulse;generating a random number seed according to the phase relation indication signal;and generating a random number sequence according to the random number seed.
- The method of claim 14, wherein the feedback signal is generated according to the steps of:generating a frequency control word according to the frequency relation indication signal;generating an intermediate signal according to the frequency control word and the frequency of the pulse, wherein the frequency of the intermediate signal is K x F/F, K is the number of the pulses generated by the pulse generation sub-circuit, F is the frequency of the pulse, and F is the frequency control word;and dividing the frequency of the intermediate signal to generate the feedback signal.
- The method of claim 15, wherein the step of dividing the intermediate signal has a division factor of 1.
- The method of claim 15, wherein dividing the intermediate signal comprises: and adjusting the frequency division coefficient according to the control parameter, and dividing the frequency of the intermediate signal by using the adjusted frequency division coefficient.
- The method of claim 14, wherein the phase relationship indicating signal is a digital signal, and the random number seed is: a plurality of said phase relationship indicating signals are binary numbers combined from values.
- The method of claim 14, wherein the random number seed is a binary number having n +1 bits,the step of generating a random number sequence from the random number seed comprises:performing multiple right shifts on the random number seed, wherein each right shift generates a binary sequence, and the random number sequence consists of at least one binary sequence; the first bit in the first binary sequence is generated by performing predetermined logic operation on values of the last two bits of the random number seed, and the other bits in the first binary sequence are generated by right shifting the first n bits of the random number seed by one bit; the first bit in the (i + 1) th binary sequence is generated after the last two bits of the (i) th binary sequence are subjected to preset logic operation, the other bits in the (i + 1) th binary sequence are generated by shifting the first n bits of the (i) th binary sequence by one bit to the right, n is an integer larger than 0, and i is an integer larger than 0 and smaller than the total number of the binary sequences.
- An electronic device comprising the random number generation circuit of claim 1.
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| CN113498506B (en) | 2024-03-19 |
| WO2021142830A1 (en) | 2021-07-22 |
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