CN113473052A - Information processing method and device - Google Patents

Information processing method and device Download PDF

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Publication number
CN113473052A
CN113473052A CN202110729693.8A CN202110729693A CN113473052A CN 113473052 A CN113473052 A CN 113473052A CN 202110729693 A CN202110729693 A CN 202110729693A CN 113473052 A CN113473052 A CN 113473052A
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China
Prior art keywords
configuration
register
image
period
register configuration
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CN202110729693.8A
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Chinese (zh)
Inventor
亓庆刚
王晓哲
金艳
徐继翔
关锐
王福因
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Beijing Ziguang Zhanrui Communication Technology Co Ltd
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Beijing Ziguang Zhanrui Communication Technology Co Ltd
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Priority to CN202110729693.8A priority Critical patent/CN113473052A/en
Publication of CN113473052A publication Critical patent/CN113473052A/en
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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00Details of television systems
    • H04N5/76Television signal recording

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Image Processing (AREA)

Abstract

The embodiment of the invention provides an information processing method and device, relates to the technical field of information processing, and aims to solve the problem of high performance loss. The method comprises the following steps: in each configuration synchronization period, acquiring register configuration of a plurality of frames of images to be processed in the current period; writing the register configuration to a specified storage location; reading the register configuration from the designated storage location at each image processing cycle; and processing the image in the current image processing period according to the register configuration. The embodiment of the invention is suitable for the flow of image processing.

Description

Information processing method and device
[ technical field ] A method for producing a semiconductor device
The present invention relates to the field of information processing technologies, and in particular, to a method and an apparatus for processing information.
[ background of the invention ]
With the development of communication technology, mobile terminals such as mobile phones and tablet computers have become indispensable tools in daily life of people. People have higher and higher requirements on mobile terminals, especially on the video recording function of the mobile terminals. In order to meet the requirement of the user to record the fast action of the target object by using the mobile terminal, for example: the slow-motion video recording function is gradually applied to the mobile terminal due to human jumping, frog predation or object falling, and the like, so that the video recording quality of the mobile terminal and the user experience effect are improved.
The slow motion video recording function of the mobile terminal is realized by that when the fast motion of the recording target object is usually performed, the mobile terminal outputs images at a frame rate of 240 frames or 480 frames to record video, and when the recorded video is played, the recorded video is played at a normal frame rate, such as 30fps, so that a user can clearly analyze the fast motion.
In the process of outputting high frame rate images, the signal processor ISP needs to process 240 frames or 480 frames of images within 1 second, and needs to process one frame of image within 2-4 ms on average, and if software and hardware interact directly, hardware configuration, hardware processing, hardware interrupt response and other operations must be completed within 2ms, which has high requirements on system performance.
[ summary of the invention ]
In view of this, embodiments of the present invention provide an information processing method and apparatus to solve the problem of too high performance loss.
In one aspect, an embodiment of the present invention provides an information processing method, including:
in each configuration synchronization period, acquiring register configuration of a plurality of frames of images to be processed in the current period;
writing the register configuration to a specified storage location;
reading the register configuration from the designated storage location at each image processing cycle;
and processing the image in the current image processing period according to the register configuration.
The above-described aspect and any possible implementation further provide an implementation, where the configuration synchronization period is 33ms or 66 ms.
The above-described aspect and any possible implementation further provide an implementation, and the number of frame images is 16 frame images or 32 frame images.
The above-described aspects and any possible implementations further provide an implementation in which the register configuration includes one or more of an image storage address, a hardware interaction instruction.
The above-described aspects and any possible implementations further provide an implementation, and the method further includes:
receiving a closing instruction;
in response to the close instruction, ceasing to read register configurations from the specified storage location.
In a second aspect, an embodiment of the present invention further provides an information processing apparatus, where the apparatus includes:
the configuration unit is used for acquiring register configuration of a plurality of frames of images to be processed in the current period in each configuration synchronization period; writing the register configuration to a specified storage location;
a processing unit for reading the register configuration from the designated storage location at each image processing cycle; and processing the image in the current image processing period according to the register configuration.
The above-described aspect and any possible implementation further provide an implementation, where the configuration synchronization period is 33ms or 66 ms.
The above-described aspect and any possible implementation further provide an implementation, and the number of frame images is 16 frame images or 32 frame images.
The above-described aspects and any possible implementations further provide an implementation in which the register configuration includes one or more of an image storage address, a hardware interaction instruction.
The above-described aspect and any possible implementation further provide an implementation, where the configuration unit is further configured to:
receiving a closing instruction;
in response to the close instruction, ceasing to read register configurations from the specified storage location.
According to the information processing method and device provided by the embodiment of the invention, in the high-frame-rate image data processing process, the register setting is carried out once every other period and the register setting is written into the appointed storage position, in the period, the device can directly read the instruction from the appointed storage position without intervening each frame, the mode that software and hardware interaction is required when each frame of image is processed in the signal processing flow is reduced, the times of software and hardware interaction are greatly reduced, and the requirements of image processing on the system performance are effectively reduced.
[ description of the drawings ]
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive labor.
FIG. 1 is a flow chart of a method for processing information according to an embodiment of the present invention;
fig. 2 is a block diagram of an information processing apparatus according to an embodiment of the present invention.
[ detailed description ] embodiments
For better understanding of the technical solutions of the present invention, the following detailed descriptions of the embodiments of the present invention are provided with reference to the accompanying drawings.
It should be understood that the described embodiments are only some embodiments of the invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
An embodiment of the present invention provides an information processing method, as shown in fig. 1, the method includes:
101. and in each configuration synchronization period, acquiring register configuration of a plurality of frames of images to be processed in the current period.
Wherein the register configuration comprises one or more of an image storage address and a hardware interaction instruction. For example, the image storage address includes an address for outputting a YUV image, an address for a statistics module, an address for acquiring an image, and the like, and the hardware interaction instruction includes a behavior instruction for starting hardware, waiting for a hardware interrupt, and the like.
The configuration synchronization period is generally determined according to the image resolution and the frame rate, which can be adjusted according to the device and the image output requirement, which is not limited by the present invention. Taking 720P (1280 × 720) resolution and 480 frames per second image output format as examples, all addresses of 16 frames of images which need to be stored and acquired, addresses of statistical modules which store statistical information, interrupts waiting for hardware to process one frame of image, and the like need to be written into an instruction queue at one time in a period of 33ms, and the instruction queue is used as a register configuration and written into a designated storage position. Of course, as the resolution of the image output increases or the frame rate per second decreases, the number of image frames that need to be present in the configuration synchronization period and the designated storage location will be adjusted accordingly. For example, increasing the image resolution from 720P to 1080P requires that the configuration of 32 frames of images is completed in a period of 33 ms; to reduce the frame rate to 240 frames per second, the configuration of 16 images needs to be completed within one period of 66 ms: if the image resolution is raised from 720P to 1080P and the frame rate is lowered to 240 frames per second, the configuration of 16 frames of images still needs to be completed within a period of 33 ms. Of course, the embodiment of the present invention is not limited thereto.
102. Writing the register configuration to a specified storage location.
When the register configuration is written into the designated storage location, the configuration is generally performed in the form of an instruction queue by upper application software, and the configuration is written into the designated storage location of hardware, for example, into a microprocessor (FMCU, Fake Micro Control Unit) of the image processing apparatus.
103. Reading the register configuration from the designated storage location at each image processing cycle.
104. And processing the image in the current image processing period according to the register configuration.
The register is configured with the contents of storage and indication, and the related devices only need to be operated one by one. And after the processing is finished, feeding back a processing result or indication information of the processing completion to the upper layer application software so that the upper layer application software can continuously execute the register configuration of the next period.
In addition, if the current image is processed or the corresponding image processing function does not need to be started, the upper layer application may receive a close instruction, where the close instruction is in response to whether the user uses the slow motion video recording function, and if the user closes the function or switches to the normal shooting mode, the close instruction may be such that, in response to the close instruction, the relevant device stops reading the register configuration from the specified storage location.
In the information processing method provided by the embodiment of the invention, in the high frame rate image data processing process, the register setting is performed once every other period and the register setting is written into the appointed storage position, in the period, the device can directly read the instruction from the appointed storage position without intervening each frame, the mode that software and hardware interaction is required when each frame of image is processed in the signal processing flow is reduced, the times of the software and hardware interaction are greatly reduced, and the requirement of the image processing on the system performance is effectively reduced.
An embodiment of the present invention further provides an information processing apparatus, which can implement the foregoing method flows, and the method flows are shown in fig. 2, and include:
the configuration unit 21 is configured to obtain, in each configuration synchronization period, register configurations of a plurality of frames of images to be processed in a current period; writing the register configuration to a specified storage location.
A processing unit 22 for reading the register configuration from the designated storage location at each image processing cycle; and processing the image in the current image processing period according to the register configuration.
Optionally, the configuration synchronization period is 33ms or 66 ms.
Optionally, the several frame images are 16 frame images or 32 frame images.
Optionally, the register configuration includes one or more of an image storage address and a hardware interaction instruction.
Optionally, the configuration unit 21 is further configured to: receiving a closing instruction; in response to the close instruction, ceasing to read register configurations from the specified storage location.
In the information processing device provided by the embodiment of the invention, in the high-frame-rate image data processing process, the register setting is performed once every other period and the register setting is written into the appointed storage position, in the period, the device can directly read the instruction from the appointed storage position without intervening each frame, the mode that software and hardware interaction is required when each frame of image is processed in the signal processing flow is reduced, the times of the software and hardware interaction are greatly reduced, and the requirement of the image processing on the system performance is effectively reduced.
It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In the embodiments provided in the present invention, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions in actual implementation, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, or in a form of hardware plus a software functional unit.
The integrated unit implemented in the form of a software functional unit may be stored in a computer readable storage medium. The software functional unit is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device) or a Processor (Processor) to execute some steps of the methods according to the embodiments of the present invention. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims (10)

1. A method of information processing, the method comprising:
in each configuration synchronization period, acquiring register configuration of a plurality of frames of images to be processed in the current period;
writing the register configuration to a specified storage location;
reading the register configuration from the designated storage location at each image processing cycle;
and processing the image in the current image processing period according to the register configuration.
2. The method of claim 1, wherein the configuration synchronization period is 33ms or 66 ms.
3. The method of claim 2, wherein the number of frame images is 16 frame or 32 frame images.
4. The method of claim 3, wherein the register configuration comprises one or more of an image storage address, a hardware interaction instruction.
5. The method of claim 4, further comprising:
receiving a closing instruction;
in response to the close instruction, ceasing to read register configurations from the specified storage location.
6. An apparatus for information processing, the apparatus comprising:
the configuration unit is used for acquiring register configuration of a plurality of frames of images to be processed in the current period in each configuration synchronization period; writing the register configuration to a specified storage location;
a processing unit for reading the register configuration from the designated storage location at each image processing cycle; and processing the image in the current image processing period according to the register configuration.
7. The apparatus of claim 6, wherein the configuration synchronization period is 33ms or 66 ms.
8. The apparatus of claim 7, wherein the number of frame images is 8 frame images or 16 frame images.
9. The apparatus of claim 8, wherein the register configuration comprises one or more of an image storage address, a hardware interaction instruction.
10. The apparatus of claim 9, wherein the configuration unit is further configured to:
receiving a closing instruction;
in response to the close instruction, ceasing to read register configurations from the specified storage location.
CN202110729693.8A 2021-06-29 2021-06-29 Information processing method and device Pending CN113473052A (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1632771A (en) * 2005-01-17 2005-06-29 北京中星微电子有限公司 Direct memory access control device and image processing system and transmission method
CN104952088A (en) * 2015-05-25 2015-09-30 常州北大众志网络计算机有限公司 Method for compressing and decompressing display data
CN107481692A (en) * 2017-09-05 2017-12-15 珠海格力电器股份有限公司 The display methods and equipment of a kind of section-type LCD

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1632771A (en) * 2005-01-17 2005-06-29 北京中星微电子有限公司 Direct memory access control device and image processing system and transmission method
CN104952088A (en) * 2015-05-25 2015-09-30 常州北大众志网络计算机有限公司 Method for compressing and decompressing display data
CN107481692A (en) * 2017-09-05 2017-12-15 珠海格力电器股份有限公司 The display methods and equipment of a kind of section-type LCD

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