CN113419977B - PCIE equipment management system in server and server - Google Patents
PCIE equipment management system in server and server Download PDFInfo
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- CN113419977B CN113419977B CN202110595118.3A CN202110595118A CN113419977B CN 113419977 B CN113419977 B CN 113419977B CN 202110595118 A CN202110595118 A CN 202110595118A CN 113419977 B CN113419977 B CN 113419977B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
- G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1673—Details of memory controller using buffers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0026—PCI express
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention provides a PCIE equipment management system in a server and the server, wherein the PCIE equipment management system comprises: the management device is connected to a state cache unit independently powered in the PCIE device through a first bus and is configured to acquire state information of the PCIE device from the state cache unit; and the processor is connected to the PCIE device through the second bus, configured to acquire state information of the PCIE device, and send the acquired state information to the management device through the KCS onboard interface, where the management device is configured to respond that the state information of the PCIE device cannot be acquired through the processor, and then acquire the state information of the PCIE device from the state cache unit instead. By using the scheme of the invention, the failure of the PCIE equipment of the server can be quickly positioned, a PCIE monitoring system independent of the processor can be established, the stability of the equipment is provided, and the serviceability and the reliability of the equipment are improved.
Description
Technical Field
The field relates to the field of computers, and more particularly to a PCIE device management system in a server and a server.
Background
The server is a product with extremely high requirement on reliability, and the PCIE equipment is an expansion interface of standard configuration equipment. Management of PCIE devices is very important to the stability of servers.
The traditional PCIE device management method for the server is to directly read PCIE device information by a processor of the server to manage the device. An onboard management system of the server receives information of the PCIE equipment through an interface between the processor and the bmc, but the onboard management system cannot manage the condition of the PCIE equipment when the processor fails or is not started.
Disclosure of Invention
In view of this, an embodiment of the present invention provides a PCIE device management system in a server and a server, and by using the technical solution of the present invention, a PCIE device failure of the server can be quickly located, a PCIE monitoring system independent of a processor can be established, stability of the device is provided, and serviceability and reliability of the device are improved.
Based on the foregoing object, an aspect of an embodiment of the present invention provides a PCIE device management system in a server, including:
the management device is connected to a state cache unit independently powered in the PCIE device through a first bus and is configured to acquire state information of the PCIE device from the state cache unit;
a processor connected to the PCIE device through a second bus, configured to acquire status information of the PCIE device and send the acquired status information to the management device through a KCS onboard interface,
the management device is configured to respond to the situation that the state information of the PCIE device cannot be acquired by the processor, and then switch to acquire the state information of the PCIE device from the state cache unit.
According to an embodiment of the present invention, the state cache unit in the PCIE device is an ram memory, and the state cache unit in the PCIE device is connected to an independent power supply.
According to one embodiment of the invention, the first bus is a smbus bus and the second bus is a PCIE bus.
According to one embodiment of the invention, the management device is a baseboard management controller in a server.
According to an embodiment of the present invention, further comprising:
and the power supply is connected to the processor, the management equipment and the PCIE equipment.
In another aspect of the embodiments of the present invention, a server is further provided, where the server includes a PCIE device management system, and the PCIE device management system includes:
the management device is connected to a state cache unit independently powered in the PCIE device through a first bus and is configured to acquire state information of the PCIE device from the state cache unit;
a processor connected to the PCIE device through a second bus, configured to acquire status information of the PCIE device and send the acquired status information to the management device through a KCS onboard interface,
the management device is configured to respond that the state information of the PCIE device cannot be acquired by the processor, and then switch to acquiring the state information of the PCIE device from the state cache unit.
According to an embodiment of the present invention, the state cache unit in the PCIE device is an ram memory, and the state cache unit in the PCIE device is connected to an independent power supply.
According to one embodiment of the invention, the first bus is a smbus bus and the second bus is a PCIE bus.
According to one embodiment of the invention, the management device is a baseboard management controller in a server.
According to an embodiment of the present invention, further comprising:
and the power supply is connected to the processor, the management equipment and the PCIE equipment.
The invention has the following beneficial technical effects: in the PCIE device management system in the server provided in the embodiment of the present invention, by setting the management device, the management device is connected to a state cache unit independently powered in the PCIE device through the first bus, and is configured to acquire state information of the PCIE device from the state cache unit; the management device is configured to respond to the situation that the processor cannot acquire the state information of the PCIE device, and then the management device changes to a technical scheme of acquiring the state information of the PCIE device from the state cache unit, so that the failure of the PCIE device of the server can be quickly positioned, a PCIE monitoring system independent of the processor can be established, the stability of the device is improved, and the serviceability and the reliability of the device are improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.
Fig. 1 is a schematic diagram of a PCIE device management system according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a server according to one embodiment of the invention.
Detailed Description
Embodiments of the present disclosure are described below. However, it is to be understood that the disclosed embodiments are merely examples and that other embodiments may take various and alternative forms. The figures are not necessarily to scale; certain features may be exaggerated or minimized to show details of particular components. Therefore, specific structural and functional details disclosed herein are not to be interpreted as limiting, but merely as a representative basis for teaching one skilled in the art to variously employ the present invention. As one of ordinary skill in the art will appreciate, various features illustrated and described with reference to any one of the figures may be combined with features illustrated in one or more other figures to produce embodiments that are not explicitly illustrated or described. The combination of features shown provides a representative embodiment for a typical application. However, various combinations and modifications of the features consistent with the teachings of the present disclosure may be desirable for certain specific applications or implementations.
Based on the foregoing objective, a first aspect of the embodiments of the present invention provides an embodiment of a PCIE device management system in a server. Fig. 1 is a schematic diagram of the PCIE device management system.
As shown in fig. 1, the PCIE device management system may include:
the management device is connected to the state cache unit independently powered in the PCIE device through a first bus, and is configured to acquire state information of the PCIE device from the state cache unit.
The management device may be a BMC (baseboard management controller) in a server, the first bus is a Smbus bus, the Smbus is a low-speed and low-cost bus, and is suitable for being used by a BMC low-speed platform, and an independent state cache unit is required to be set in a PCIE device, where the state cache unit is an ram memory, and the state cache unit is required to set an independent power supply, for example, the independent power supply may be a storage battery, and a system power supply cannot be used as the independent power supply, so as to prevent the state cache unit from being powered off at the same time when a system is powered off and being unable to read data in the state cache unit, when the PCIE device is in operation, the operation information and the state information of the PCIE device are sent to the state cache unit in real time for storage, and at the same time, the state cache unit is required to send the received operation information and the state information of the PCIE device to the management device for storage, and in a state where the server is in normal operation, the PCIE device can directly obtain the operation information and the cache unit of the PCIE device and can be able to obtain the cache information when the PCIE device is in an abnormal state, and when the server is in an abnormal state, the PCIE device, the server, the PCIE device can be able to obtain the cache information when the PCIE device and the server is in an abnormal state cache unit.
In another embodiment, a module of a state cache unit that supplies power independently may be provided, where the module of the state cache unit is composed of an ram memory, and the module of the state cache unit needs to be provided with an independent power supply, for example, the independent power supply may be a storage battery, and a system power supply cannot be used as the independent power supply, so as to prevent the state cache unit from being powered off simultaneously and being unable to read data in the state cache unit when the system is powered off, when a PCIE device is in operation, the operation information and the state information of each PCIE device are sent to the module of the independent state cache unit in real time to be stored, and at the same time, the module of the state cache unit needs to send the received operation information and the state information of the PCIE device to a management device to be stored, in a state where a server operates normally, the operation information and the state information of the PCIE device may be directly obtained in the management device (substrate management controller), and when the server is abnormal or is shut down, the substrate management controller may obtain the operation information and may ensure that a failure of the PCIE device may be located quickly when the server is abnormal.
In another embodiment, an independent status cache unit may be disposed in the BMC, where the status cache unit is composed of an ram memory, and the status cache unit needs to be provided with an independent power supply, for example, the independent power supply may be a storage battery, and a system power supply cannot be used as the independent power supply, so as to prevent the status cache unit from being powered off at the same time and being unable to read data in the status cache unit when the system is powered off, when the PCIE device is in operation, the operation information and the status information of each PCIE device are sent to the status cache unit in the BMC in real time to be stored, and at the same time, the status cache unit needs to send the received operation information and the received status information of the PCIE device to the management device to be stored, when the server is in a normal operation state, the operation information and the status information of the PCIE device may be directly obtained in the management device (substrate management controller), when the server is abnormal or is turned off, or when the substrate management controller is abnormal, the server may obtain the operation information and the status information and it can be ensured that the PCIE device may be failed when the server is abnormal, the server may be located quickly.
The PCIE equipment management system further comprises a processor, wherein the processor is connected to the PCIE equipment through a second bus, configured to acquire state information of the PCIE equipment, and sends the acquired state information to the management equipment through a KCS onboard interface, wherein the management equipment is configured to respond that the state information of the PCIE equipment cannot be acquired through the processor, and then the state information of the PCIE equipment is acquired from a state cache unit.
The processor is a CPU of the system, the second bus is a PCIE bus, the CPU reads the operation information and the state information of the PCIE device through the PCIE bus, and then sends the operation information and the state information to the substrate management Controller through a KCS onboard interface (Keyboard Controller mode, a transport protocol), that is, the substrate management Controller can simultaneously receive the operation information and the state information of the PCIE device sent by the CPU and the operation information and the state information of the PCIE device sent by the state cache unit, and the two pieces of information received at the same time should be the same because both are sent by the PCIE device, so that when the substrate management Controller does not receive two pieces of the same information at the same time, it indicates that one of the lines has a fault, and the substrate management Controller can generate a corresponding alarm to notify an administrator to perform an inspection. In addition, the baseboard management controller receives two pieces of same information, the two pieces of same information are not both stored, the two pieces of information are compared, if the two pieces of information are the same PCIE equipment and the time is the same, one piece of information is deleted, and the other piece of information is stored, so that the baseboard management controller is prevented from storing more repeated data.
The running information and the state information of the PCIE device in the state cache unit may be circularly stored in the form of a log, and the log that is stored first is deleted after a certain time elapses, so as to ensure that the state cache unit has a sufficient storage space to store data.
Through the technical scheme of the invention, the failure of the PCIE equipment of the server can be quickly positioned, a PCIE monitoring system independent of a processor can be established, the stability of the equipment is provided, and the serviceability and the reliability of the equipment are improved.
In a preferred embodiment of the present invention, the state cache unit in the PCIE device is an ram memory, and the state cache unit in the PCIE device is connected to an independent power supply. The memory needs to have enough storage space to be able to store the operation information and the status information of a sufficient number of PCIE devices, and the independent power supply may be a storage battery.
In a preferred embodiment of the present invention, the first bus is a smbus bus and the second bus is a PCIE bus.
In a preferred embodiment of the present invention, the management device is a baseboard management controller in a server.
In a preferred embodiment of the present invention, the method further comprises:
and the power supply is connected to the processor, the management equipment and the PCIE equipment.
Through the technical scheme of the invention, the failure of the PCIE equipment of the server can be quickly positioned, a PCIE monitoring system independent of a processor can be established, the stability of the equipment is provided, and the serviceability and the reliability of the equipment are improved.
Based on the above object, a second aspect of the embodiment of the present invention provides a server 1, as shown in fig. 2, where the server 1 includes a PCIE device management system, and the PCIE device management system includes:
the management device is connected to a state cache unit which is independently powered in the PCIE device through a first bus, and is configured to acquire state information of the PCIE device from the state cache unit.
The management device may be a BMC (baseboard management controller) in a server, the first bus is a Smbus bus, the Smbus is a low-speed and low-cost bus, and is suitable for being used by a BMC low-speed platform, and an independent state cache unit is required to be set in a PCIE device, where the state cache unit is an ram memory, and the state cache unit is required to set an independent power supply, for example, the independent power supply may be a storage battery, and a system power supply cannot be used as the independent power supply, so as to prevent the state cache unit from being powered off at the same time when a system is powered off and being unable to read data in the state cache unit, when the PCIE device is in operation, the operation information and the state information of the PCIE device are sent to the state cache unit in real time for storage, and at the same time, the state cache unit is required to send the received operation information and the state information of the PCIE device to the management device for storage, and in a state where the server is in normal operation, the PCIE device can directly obtain the operation information and the cache unit of the PCIE device and can be able to obtain the cache information when the PCIE device is in an abnormal state, and when the server is in an abnormal state, the PCIE device, the server, the PCIE device can be able to obtain the cache information when the PCIE device and the server is in an abnormal state cache unit.
In another embodiment, an independent module of a state cache unit may be provided, where the module of the state cache unit is composed of an ram memory, and the state cache unit module needs to be provided with an independent power supply, for example, the independent power supply may be a storage battery, and a system power supply cannot be used as the independent power supply, so as to prevent the state cache unit from being powered off at the same time and being unable to read data in the state cache unit when the system is powered off, when a PCIE device is in operation, the operation information and the state information of each PCIE device are sent to the module of the independent state cache unit in real time to be stored, and at the same time, the module of the state cache unit needs to send the received operation information and the state information of the PCIE device to a management device to be stored, in a state where a server operates normally, the operation information and the state information of the PCIE device may be directly obtained in the management device (substrate management controller), and when the server is abnormal or is shut down, the operation information and it may be ensured that a failure of the PCIE device can be quickly located when the server is abnormal.
In another embodiment, an independent status cache unit may be disposed in the BMC, where the status cache unit is composed of an ram memory, and the status cache unit needs to be provided with an independent power supply, for example, the independent power supply may be a storage battery, and a system power supply cannot be used as the independent power supply, so as to prevent the status cache unit from being powered off at the same time and being unable to read data in the status cache unit when the system is powered off, when the PCIE device is in operation, the operation information and the status information of each PCIE device are sent to the status cache unit in the BMC in real time to be stored, and at the same time, the status cache unit needs to send the received operation information and the received status information of the PCIE device to the management device to be stored, when the server is in a normal operation state, the operation information and the status information of the PCIE device may be directly obtained in the management device (substrate management controller), when the server is abnormal or is turned off, or when the substrate management controller is abnormal, the server may obtain the operation information and the status information and it can be ensured that the PCIE device may be failed when the server is abnormal, the server may be located quickly.
The management system of the PCIE equipment further comprises a processor, wherein the processor is connected to the PCIE equipment through a second bus, configured to acquire state information of the PCIE equipment, and sends the acquired state information to the management equipment through a KCS onboard interface, wherein the management equipment is configured to respond to the situation that the state information of the PCIE equipment cannot be acquired through the processor, and then the state information of the PCIE equipment is acquired from the state cache unit instead.
The processor is a CPU of the system, the second bus is a PCIE bus, the CPU reads the operation information and the state information of the PCIE device through the PCIE bus, and then sends the operation information and the state information to the substrate management Controller through a KCS onboard interface (Keyboard Controller mode, a transport protocol), that is, the substrate management Controller can simultaneously receive the operation information and the state information of the PCIE device sent by the CPU and the operation information and the state information of the PCIE device sent by the state cache unit, and the two pieces of information received at the same time should be the same because both are sent by the PCIE device, so that when the substrate management Controller does not receive two pieces of the same information at the same time, it indicates that one of the lines has a fault, and the substrate management Controller can generate a corresponding alarm to notify an administrator to perform an inspection. In addition, the baseboard management controller receives two pieces of same information, the two pieces of same information are not both stored, the two pieces of information are compared, if the two pieces of information are the same PCIE equipment and the time is the same, one piece of information is deleted, and the other piece of information is stored, so that the baseboard management controller is prevented from storing more repeated data.
The running information and the state information of the PCIE device in the state cache unit may be circularly stored in the form of a log, and the log that is stored first is deleted after a certain time elapses, so as to ensure that the state cache unit has a sufficient storage space to store data.
In a preferred embodiment of the present invention, the state cache unit in the PCIE device is an ram memory, and the state cache unit in the PCIE device is connected to an independent power supply.
In a preferred embodiment of the present invention, the first bus is a smbus bus and the second bus is a PCIE bus.
In a preferred embodiment of the present invention, the management device is a baseboard management controller in a server.
In a preferred embodiment of the present invention, the method further comprises:
and the power supply is connected to the processor, the management equipment and the PCIE equipment.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
The embodiments described above, particularly any "preferred" embodiments, are possible examples of implementations and are presented merely to clearly understand the principles of the invention. Many variations and modifications may be made to the above-described embodiments without departing from the spirit and principles of the technology described herein. All such modifications are intended to be included within the scope of this disclosure and protected by the following claims.
Claims (10)
1. A PCIE device management system in a server is characterized by comprising:
the management device is connected to a state cache unit independently powered in the PCIE device through a first bus and configured to acquire state information of the PCIE device from the state cache unit;
a processor connected to the PCIE device through a second bus, configured to acquire status information of the PCIE device and send the acquired status information to the management device through a KCS onboard interface,
the management device is configured to respond that the state information of the PCIE device cannot be acquired by the processor, and then switch to acquiring the state information of the PCIE device from the state cache unit.
2. The PCIE device management system of claim 1, wherein the state cache unit in the PCIE device is an ram memory, and the state cache unit in the PCIE device is connected to an independent power supply.
3. The PCIE device management system of claim 1, wherein the first bus is a smbus bus and the second bus is a PCIE bus.
4. The PCIE device management system of claim 1, wherein the management device is a baseboard management controller in a server.
5. The PCIE device management system of claim 1, further comprising:
a power supply connected to the processor, the management device, and the PCIE device.
6. A server, comprising a PCIE device management system, wherein the PCIE device management system includes:
the management device is connected to a state cache unit which is independently powered in the PCIE device through a first bus, and is configured to acquire state information of the PCIE device from the state cache unit;
a processor connected to the PCIE device through a second bus, configured to acquire status information of the PCIE device and send the acquired status information to the management device through a KCS onboard interface,
the management device is configured to respond to the situation that the state information of the PCIE device cannot be acquired by the processor, and then switch to acquire the state information of the PCIE device from the state cache unit.
7. The server according to claim 6, wherein the state cache unit in the PCIE device is an ram memory, and the state cache unit in the PCIE device is connected to an independent power supply.
8. The server of claim 6, wherein the first bus is a smbus bus and the second bus is a PCIE bus.
9. The server according to claim 6, wherein the management device is a baseboard management controller in the server.
10. The server of claim 6, further comprising:
a power supply connected to the processor, the management device, and the PCIE device.
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