CN113407463A

CN113407463A - Method of controlling memory system, computer apparatus, and storage medium

Info

Publication number: CN113407463A
Application number: CN202110733224.3A
Authority: CN
Inventors: 孙修立; 曹凯耀
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2021-06-29
Filing date: 2021-06-29
Publication date: 2021-09-17

Abstract

A method of controlling a memory system, a computer apparatus, and a storage medium are provided. The method of controlling a memory system includes: acquiring a mapping table from a memory system, compressing at least part of the mapping table and caching the compressed mapping table in a host memory; and decompressing the cached mapping table, and controlling the memory system to execute a read operation according to the decompressed mapping table. The method for controlling the memory system, the computer device and the storage medium provided by the application can reduce the occupation of the mapping table cached in the host memory on the storage space resources of the host memory, and are beneficial to the interactive operation between the host and the memory system.

Description

Method of controlling memory system, computer apparatus, and storage medium

Technical Field

The present application relates to the field of computer technologies, and more particularly, to a method of controlling a memory system, a computer apparatus, a storage medium, a storage controller, and a memory system.

Background

Non-volatile memory devices are capable of retaining data stored therein after a power failure and are widely used in computers, cellular phones, smart phones, personal digital assistants and other electronic device systems. The storage controller is used to control various operations of the nonvolatile storage device and coordinate data scheduling between the nonvolatile storage device and a Host (Host).

In addition, the storage controller is also used to perform mapping (mapping) of the logical address of the host to a physical address in the non-volatile storage device. When a host executes, for example, a program operation on a nonvolatile memory device, a memory controller writes mapping relationship (L2P) data of a logical address to a physical address corresponding to the program operation into the nonvolatile memory device, so that the host reads the program data of the program operation by using the mapping relationship data.

In some implementations, the L2P mapping table may also be stored in the storage (e.g., memory) of the host to improve the speed at which the storage controller controls the non-volatile storage device to perform random access. However, loading the L2P mapping table into the host memory for maintenance occupies a large amount of host memory space, which is a technical problem to be solved in the development of the storage controller of the non-volatile storage device.

Disclosure of Invention

One aspect of the present application provides a method of controlling a memory system. The method comprises the following steps: acquiring a mapping table from a memory system, compressing at least part of the mapping table and caching the compressed mapping table in a host memory; and decompressing the cached mapping table, and controlling the memory system to execute a read operation according to the decompressed mapping table.

In some embodiments, the step of controlling the memory system to perform a read operation comprises: and controlling the memory system to execute the read operation in a read mode of the HPB.

In some embodiments, the memory system is a UFS memory system.

In some embodiments, a memory system includes a memory controller and a non-volatile storage device, wherein the step of controlling the memory system to perform a read operation includes: and acquiring the physical address of the data to be read stored in the nonvolatile storage device according to the mapping table and the logic address after decompression processing, and sending the physical address to the storage controller.

In some embodiments, the step of obtaining the mapping table from the memory system comprises: in the case where the memory system is in an idle phase, a mapping table is obtained from the memory system.

In some embodiments, after the step of obtaining the mapping table from the memory system, the method further comprises: in response to an update request by the memory system for the partial mapping table, an updated mapping table is obtained from the memory system.

In some embodiments, the step of obtaining the updated mapping table from the memory system comprises: decompressing the mapping table to be updated cached in the host memory, and executing updating operation on the decompressed mapping table.

In some embodiments, the mapping table is divided into a plurality of logical blocks according to logical addresses of the mapping table, wherein in the step of buffering at least part of the mapping table in the host memory after compression processing, the mapping table corresponding to each logical block is compressed in units of logical blocks.

In some embodiments, the step of decompressing the cached mapping table comprises: and determining a corresponding logic block according to the logic address, and decompressing the mapping table comprising the logic block.

In some embodiments, the mapping table is divided into a plurality of logical blocks according to the logical address of the mapping table, each logical block includes a plurality of sub-logical blocks, wherein in the step of buffering at least part of the mapping table after compression processing in the host memory, the mapping table corresponding to each sub-logical block is compressed in units of sub-logical blocks.

In some embodiments, the step of decompressing the cached mapping table comprises: and determining a corresponding sub logic block according to the logic address, and decompressing the mapping table comprising the sub logic block.

In some embodiments, the step of obtaining the mapping table from the memory system and buffering at least part of the mapping table after compression processing in the host memory comprises: and according to the reference frequency for executing the reading operation by utilizing the mapping table, buffering at least part of the mapping table after compression processing in a host memory.

In some embodiments, the mapping table is compressed and/or decompressed by one of a GZIP compression algorithm, an LZO compression algorithm, and a zipper/snap compression algorithm.

Another aspect of the present application provides a computer apparatus. The computer device includes: a processor; and a memory communicatively coupled to the processor; the memory stores a driver executable by the processor, the driver being executable by the processor to enable the processor to perform the method of controlling the memory system as described in any of the embodiments above.

Another aspect of the present application also provides a non-transitory computer-readable medium storing a computer program for causing a computer to execute the method of controlling a memory system described in any of the above embodiments.

Another aspect of the present application also provides a memory controller. The memory controller is used to control the nonvolatile memory device, and the memory controller and the nonvolatile memory device are used to constitute a memory system. The storage controller is configured to: sending the mapping table stored in the memory system to a host computer so that at least part of the mapping table is cached in a host computer memory of the host computer after being compressed; and controlling the nonvolatile storage device to execute the reading operation according to the mapping table which is cached in the host memory and subjected to decompression processing.

Another aspect of the present application also provides a memory system. The memory system includes: a non-volatile storage device; and a storage controller for controlling the nonvolatile storage device, wherein the storage controller is configured to: sending the mapping table stored in the memory system to a host computer so that at least part of the mapping table is cached in a host computer memory of the host computer after being compressed; and controlling the nonvolatile storage device to execute the reading operation according to the mapping table which is cached in the host memory and subjected to decompression processing.

According to the method for controlling the memory system, the computer device, the storage medium, the storage controller and the memory system, the mapping table is compressed and cached in the host memory, so that the occupation of the mapping table cached in the host memory on the storage space resource of the host memory can be reduced, and the interactive operation between the host and the memory system is facilitated.

Drawings

Other features, objects and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:

FIG. 1 is a schematic block diagram of a host and memory system according to an embodiment of the present application;

FIG. 2 is a flow chart of a method of controlling a memory system according to an embodiment of the present application;

FIG. 3 is a schematic diagram of a method for performing a control memory system using host memory resources according to an embodiment of the present application;

FIG. 4 is a diagram illustrating a mapping relationship between logical blocks and physical blocks according to an embodiment of the present application;

FIG. 5 is a diagram illustrating a partial mapping table structure in a logic block according to an embodiment of the present application;

FIG. 6 is a diagram illustrating a method for performing an update operation using a host memory resource execution control mapping table according to an embodiment of the present application; and

fig. 7 is a schematic structural diagram of a computer device suitable for implementing the embodiments of the present application.

Detailed Description

For a better understanding of the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that the detailed description is merely illustrative of exemplary embodiments of the present application and does not limit the scope of the present application in any way.

The terminology used herein is for the purpose of describing particular example embodiments and is not intended to be limiting. The terms "comprises," "comprising," "includes" and/or "including," when used in this specification, specify the presence of stated features, integers, elements, components, and/or groups thereof, but do not preclude the presence or addition of one or more other features, integers, elements, components, and/or groups thereof.

This description is made with reference to schematic illustrations of exemplary embodiments. The exemplary embodiments disclosed herein should not be construed as limited to the particular shapes and dimensions shown, but are to include various equivalent structures capable of performing the same function, as well as deviations in shapes and dimensions that result, for example, from manufacturing. The locations shown in the drawings are schematic in nature and are not intended to limit the location of the various components.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Fig. 1 is a schematic structural diagram of a host 20 and a memory system 10 according to an embodiment of the present application. As shown in fig. 1, memory system 10 may store data that is accessible by host 20, and host 20 may include a mobile phone, MP3 player, laptop computer, desktop computer, game console, television, or in-vehicle infotainment system, among others. According to an interface protocol in which the memory system 10 is connected to the host 20, the memory system 10 may be configured as a device such as a universal flash memory storage (UFS) device, a Solid State Disk (SSD), a multimedia card in the form of MMC, eMMC, RS-MMC, and micro MMC, a secure digital card in the form of SD, mini SD, and micro SD, a Personal Computer Memory Card International Association (PCMCIA) card type memory device, a Peripheral Component Interconnect (PCI) type memory device, a PCI express (PCI-E) type memory device, a Compact Flash (CF) card, a smart media card, or a memory stick.

The host 20 controls the overall operation of the memory system 10. Host 20 may include a host processor 310 and a host memory 320.

Host processor 310 may control the operation of host 20. For example, host processor 310 may interact with memory system 10 through, for example, a storage drive, to control various operations of memory system 10. The storage drive may be, for example, a software module for controlling the memory system 10. Host 20 may control memory system 10 via the storage drive to perform data programming, reading, and erasing operations, for example. Illustratively, the storage drive also includes, for example, a Host Performance Boost (HPB) module and a Write Performance boost (WB) module. Through the host performance boosting module, the host 20 can load the mapping table in the host memory 320 to increase the speed at which the host processor 310 controls the memory system 10 to perform read operations. Specifically, a method of controlling the memory system 10 to perform a read operation using the host performance boosting module will be described in detail below.

Host memory 320 may store instructions and/or data that are executed and/or processed by processor 310. Host memory 320 may be a storage device having a relatively fast operating speed. Host memory 320 may include at least one of various volatile memories, such as DRAM.

The memory system 10 may include a non-volatile memory device 100 and a memory controller 200.

The non-volatile storage device 100 may be a storage medium used by the memory system 10 to store data. The non-volatile memory device 100 may have one or more memory die (die). Each memory die may include a memory cell array, which may include a plurality of memory cells arranged at intersections of word lines and bit lines. The memory cell array may be divided into a plurality of memory blocks, each memory block may be further divided into a plurality of sub memory blocks, and each memory block or each sub memory block may include a plurality of pages. Each memory cell in the memory cell array may be any one of a single-layer memory cell (SLC) capable of storing one bit of data, a two-layer memory cell (MLC) capable of storing two bits of data, a three-layer memory cell (TLC) capable of storing three bits of data, and a four-layer memory cell (QLC) capable of storing four bits of data. Illustratively, the non-volatile storage device 100 may be a three-dimensional NAND flash memory device, more specifically, the non-volatile storage device 100 may be, for example, a plurality of three-dimensional NAND flash memory devices arranged in parallel to achieve, for example, mass data storage of 256G or more.

The memory controller 200 may include a host interface 210, a processor 220, and a memory interface 230. The storage controller 200 may control the memory system 10 to perform operations by driving firmware or software stored in the nonvolatile storage device 100. The storage controller 200 may decode and drive instructions or algorithms of a code type, such as firmware or software. And the storage controller 200 may be implemented as hardware or a combination of hardware and software.

The host interface 210 (which may also be referred to as a "front-end interface") may connect the host 20 and the memory system 10 according to an interface protocol. The host interface 210 may communicate with the host 20 via any one of protocols such as universal flash memory (UFS) protocol, Serial Advanced Technology Attachment (SATA) protocol, Peripheral Component Interconnect (PCI) protocol and PCI express (PCI-E) protocol, Universal Serial Bus (USB) protocol, multi-media card (MMC) protocol, Parallel Advanced Technology Attachment (PATA) protocol, Small Computer System Interface (SCSI) protocol, SCSI serial (sas) protocol, and the like.

The processor 220 may be implemented by, for example, an ARM core or the like, and may drive firmware called a Flash Translation Layer (FTL) in order to control the inherent operation of the nonvolatile memory device 100 and provide device compatibility to the host 20. When driving the FTL, the host 20 may view and use the memory system 10 as a general storage device such as a hard disk. Further, the processor 220 may also implement functions such as Wear Leveling (Wear Leveling), Garbage Collection (Garbage Collection), Bad Block Management (Bad Block Management), etc. through driver firmware.

The memory interface 230 (which may also be referred to as a "back-end interface") may control the non-volatile storage device 100 according to a processor 220, such as a Flash memory controller. The memory interface 230 may provide control signals to the non-volatile memory device 100. The control signals may include commands, addresses, operation control signals, and the like for controlling the nonvolatile memory device 100. The memory interface 230 may connect the non-volatile memory device 100 according to a corresponding interface protocol. Illustratively, the memory interface 230 may communicatively interact with the non-volatile storage 100, for example, via the ONFI protocol.

FIG. 2 is a flow chart of a method 1000 of controlling a memory system according to an embodiment of the present application. FIG. 3 is a diagram illustrating a method for performing controlling a memory system using host memory resources according to an embodiment of the present application.

As shown in fig. 2 and fig. 3, in step S110, for example, after the host 20 establishes a communication connection with the memory system 10, the host processor 310 in the host 20 may send an initialization request, and the memory controller 200 in the memory system 10 receives the initialization request and sends the mapping table corresponding to the nonvolatile memory device 100 of the memory system 10 to the host 20.

In some embodiments, the mapping table of the memory system 10 corresponding to the nonvolatile storage device 100 may be sent to the host 20 with the memory system 10 in an idle phase. In other words, the host 20 may obtain the mapping table from the memory system 10 in the case where the memory system 10 is in an idle phase to avoid conflicts with other operations performed by the memory system 10. It should be understood that the case where the memory system 10 is in the idle phase may be, for example, a case where the memory system 10 does not perform a program, read, or erase operation.

The mapping table can be expressed as a mapping relationship between Logical addresses LBA To Physical addresses PBA, and therefore can be referred To as an L2P (Logical To Physical) table. In the prior art, the host 20 can access the nonvolatile memory device 100 using the logical address LBA, and the memory controller 200 in the memory system 10 can access the nonvolatile memory device 100 using the physical address PBA. It should be understood that when the host 20 reads data stored in the nonvolatile memory device 100, the memory controller 200 in the memory system 10 reads data desired to be read from the nonvolatile memory device 100 using the mapping tables and transmits the data to the host 20, thereby causing the host to acquire the data desired to be read stored in the nonvolatile memory device 100.

Fig. 4 is a schematic diagram of a mapping relationship between logical blocks and physical blocks according to an embodiment of the present application. As shown in fig. 4, the method of generating the mapping table includes block mapping according to the mapping granularity. In the block mapping, one logical block (Region) in the mapping table may be mapped to a physical block corresponding to a storage block in any nonvolatile storage device 100. It should be understood that, in the case that one memory block in the nonvolatile memory device 100 includes a plurality of sub memory blocks, in the block mapping, one sub logical block (Subregion) in the mapping table may be mapped to a sub physical block corresponding to the sub memory block in any one of the nonvolatile memory devices 100. And the physical blocks corresponding to the logical blocks, or the sub-physical blocks corresponding to the sub-logical blocks, may be the same size.

Further, in this step, the host 20 may load the mapping table acquired from the memory system 10 into its host memory 320. Host memory 320 may include, but is not limited to, DRAM and SRAM, among others. Specifically, the host processor 310 compresses at least a portion of the mapping table. The host processor 310 in the host 20 may compress at least a part of the mapping table loaded into the host memory 320 by calling a data compression handler. The data compression handler may be generated according to any one or a combination of compression algorithms such as the GZIP compression algorithm, the LZO compression algorithm, and the zipper/snap compression algorithm.

Fig. 5 is a schematic diagram of a partial mapping table structure in a logic block according to an embodiment of the present application. As shown in fig. 5, the mapping table is represented by a 16-ary number. Each row in the mapping table may represent a mapping relationship from a logical address to a physical address, and is referred to as an entry. Because the mapping table in each table entry usually adopts randomized encryption processing, but regularity exists among a plurality of table entries in the logic block/sub-logic block, according to the data compression principle, the mapping table buffered in the host memory can be subjected to data compression processing by taking the logic block or the sub-logic block as a unit, thereby improving the compression rate of at least part of the mapping table buffered in the host.

For example, the LZO compression algorithm replaces a string that has currently appeared in a history string with (repeat length L, pointing back distance D), where the repeat length refers to the length of the consecutive same portion of the later appearing string as the first appearing string. The back-pointing distance D is the distance (one byte per byte) between two consecutive identical strings. If the character is not appeared (defined as a new character), the number of the new character is firstly output, and then the new character is output. In the embodiment of the present application, the LZO algorithm is used to compress a character string (b 95 f b8 fa) having a line number of 000000d0 as a character string having a line number of 000000c8 that appears repeatedly.

Table 1 is a compression performance parameter table of the existing GZIP compression algorithm, LZO compression algorithm, and zipper/snap compression algorithm. After performing compression processing on a mapping table of 6K size cached in the host 20 using, for example, the GZIP compression algorithm, the measured compression rate may be less than or equal to 40%.

Compression algorithm	Compression ratio%	Compression rate Mb/s	Decompression rate Mb/s
				GZIP	13	20	120
LZO	20	130	420
				Zippy/Snappy	22	170	410

TABLE 1

In some embodiments, at least a portion of the mapping table may be buffered in the host memory after compression according to a reference frequency for performing a read operation using the mapping table. It should be understood that caching some mapping tables with higher reference frequency for performing read operations in the host memory in a decompressed state and some mapping tables with lower reference frequency for performing read operations in the host memory in a compressed state can ensure real-time performance of the host reading data in the nonvolatile memory device 100 using the mapping tables while reducing the memory space cached in the host memory.

In step S120, referring again to fig. 2 and 3, when the host 20 wants to control the memory system 10 to perform a read operation on data stored in the nonvolatile memory device 100, the host 20 may decompress a compression mapping table buffered in the host memory 320 corresponding to the read operation, for example, by using a decompression algorithm corresponding to any one of the GZIP compression algorithm, the LZO compression algorithm, and the zip/snap compression algorithm described above. The host 20 obtains the physical address of the data to be read according to the mapping table after the decompression processing, and sends the physical address to the memory system 10. In other words, the host 20 may access the logical address of the requested data and the decompressed mapping table, and by sending a read request (including the physical address of the data desired to be read) to the storage controller 200, cause the storage controller 200 to access the physical address of the requested data to read the requested data stored in the nonvolatile storage device 100 in response to the request. Further, the memory controller 200 in the memory system 10 may send the requested read data back to the host 20 through the memory controller 200.

In some embodiments, since the data compression process is performed in units of logical blocks/sub-logical blocks on the mapping table buffered in the host memory 320, when the host 20 controls the memory system 10 to perform a read operation, the host processor 310 may determine a corresponding logical block/sub-logical block according to a logical address of data to be read, and perform a decompression process on the mapping table including the logical block/sub-logical block, so as to enable the host 20 to perform a subsequent read operation.

FIG. 6 is a diagram illustrating a method for performing an update operation using a host memory resource execution control mapping table according to an embodiment of the present application. As shown in fig. 6, in this embodiment, after the host 20 loads the mapping table stored in the memory system 10 into the host memory 320 therein, the memory controller 200 may cause the mapping table to change by, for example, a garbage collection operation, a read collection operation, a data update operation, etc., so that the memory controller 200 may send an update data request to the host 20 to update the mapping table cached in the host memory 320. In other words, the host 20 may obtain the updated mapping table in response to an update request of the memory system 10. Specifically, since part of the mapping table is compressed and buffered in the memory of the host 20, one or a combination of the GZIP compression algorithm, the LZO compression algorithm, and the zipper/snapshot compression algorithm may be used to buffer the mapping table corresponding to the update request in the memory of the host 20 after the decompression, update, and recompression processing, so that the logical addresses and the physical addresses in the mapping table are in one-to-one correspondence after the update operation.

As described in the background art, in the existing operating method for executing a storage controller by using host memory resources, when one physical block corresponds to one logical block, assuming that one entry in each logical block occupies 8 bytes, the storage space size total size occupied by loading all mapping tables into the host memory is:

the LUN size is the storage space size of one logical unit LUN in the non-volatile storage device, and may be, for example, 128 GB. The Block size is the storage space size of a storage Block in one logical unit LUN in the non-volatile storage device, and may be, for example, 4 KB. Thus, the total size of the storage space occupied in the host memory may be 256 MB. Under the trend of gradually increasing the storage space size of the LUN of the non-volatile storage device, the storage space occupied by the mapping table cached in the host memory is also gradually increased, which may cause a burden on the host memory and is not favorable for the host and the storage controller/storage system to perform an interactive operation.

According to the method for controlling the memory system, the mapping table is compressed and cached in the host memory, so that the occupation of the mapping table cached in the host memory on the storage space resources of the host memory can be reduced, and the interactive operation between the host and the memory controller is facilitated.

Fig. 7 is a schematic structural diagram of a computer device 2000 adapted to implement an embodiment of the present application. It should be understood that the computer apparatus shown in fig. 7 is only an example, and should not bring any limitation to the function and use range of the embodiments of the present application.

As shown in fig. 7, the computer apparatus 2000 includes at least one processor 1 (e.g., CPU) that can perform various appropriate operations and processes according to a program stored in a Read Only Memory (ROM)2 or a program loaded from a storage section 6 into a Random Access Memory (RAM) 3. In the RAM 3, various programs and data necessary for the operation of the computer apparatus 2000 are also stored. The processor 1, the ROM 2 and the RAM 3 are connected to each other via a bus 4. An input/output (I/O) interface 5 is also connected to the bus 4.

The following components are connected to the I/O interface 5: a storage section 6 including a hard disk and the like; and a communication section 7 including a network interface card such as a LAN card, a modem, or the like. The communication section 7 performs communication processing via a network such as the internet. A drive 8 is also connected to the I/O interface 5 as necessary. A removable medium 9 such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, or the like is mounted on the drive 8 as necessary, so that a computer program read out therefrom is mounted into the storage section 6 as necessary.

It will be understood by those skilled in the art that all or part of the steps in the method for implementing the above embodiments may be implemented by hardware related to instructions of a program, where the program may be stored in a computer readable storage medium, and when executed, the program includes the following steps: s100, acquiring a mapping table from a memory system, compressing at least part of the mapping table, and caching the compressed mapping table in a host memory; and S120, decompressing the cached mapping table, and controlling the memory system to execute a read operation according to the decompressed mapping table.

The application also provides a memory controller and a memory system. Since any of the embodiments described above can be applied to the memory controller and the memory system provided in the present application, the present application will not be described herein.

The above description is only a preferred embodiment of the present application and is illustrative of the principles of the technology employed. It will be appreciated by a person skilled in the art that the scope of the invention as referred to in the present application is not limited to the embodiments with a specific combination of the above-mentioned features, but also covers other embodiments with any combination of the above-mentioned features or their equivalents without departing from the inventive concept. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.

Claims

1. A method of controlling a memory system, the method comprising:

acquiring a mapping table from the memory system, compressing at least part of the mapping table, and caching the compressed mapping table in a host memory; and

and decompressing the cached mapping table, and controlling the memory system to execute a reading operation according to the decompressed mapping table.

2. The method of claim 1, wherein the step of controlling the memory system to perform a read operation comprises:

and controlling the memory system to execute a read operation in a read mode of the HPB.

3. The method of claim 2, wherein the memory system is a UFS memory system.

4. The method of claim 2, wherein the memory system comprises a memory controller and a non-volatile memory device, and wherein controlling the memory system to perform a read operation comprises:

and acquiring a physical address of data to be read stored in the nonvolatile storage device according to the mapping table and the logic address after decompression processing, and sending the physical address to the storage controller.

5. The method of claim 1, wherein the step of obtaining a mapping table from the memory system comprises:

obtaining the mapping table from the memory system if the memory system is in an idle phase.

6. The method of claim 1, wherein after the step of obtaining a mapping table from the memory system, the method further comprises:

in response to an update request for a partial mapping table by the memory system, obtaining an updated mapping table from the memory system.

7. The method of claim 6, wherein the step of obtaining an updated mapping table from the memory system further comprises:

decompressing the mapping table to be updated cached in the host memory, and executing an updating operation on the decompressed mapping table.

8. The method according to claim 4, wherein the mapping table is divided into a plurality of logical blocks according to the logical addresses of the mapping table, and wherein in the step of buffering at least part of the mapping table in the host memory after compression processing, the mapping table corresponding to each logical block is compressed in units of the logical block.

9. The method of claim 8, wherein decompressing the cached mapping table comprises:

and determining a corresponding logic block according to the logic address, and decompressing a mapping table comprising the logic block.

10. The method according to claim 4, wherein the mapping table is divided into a plurality of logical blocks according to the logical addresses of the mapping table, each of the logical blocks includes a plurality of sub logical blocks, and wherein in the step of buffering at least part of the mapping table after compression processing in the host memory, the mapping table corresponding to each of the sub logical blocks is compressed in units of the sub logical blocks.

11. The method of claim 10, wherein decompressing the cached mapping table comprises:

and determining a corresponding sub logic block according to the logic address, and decompressing a mapping table comprising the sub logic block.

12. The method of claim 1, wherein the step of obtaining a mapping table from the memory system and buffering at least a portion of the mapping table in the host memory after compression comprises:

and according to the reference frequency for executing the reading operation by utilizing the mapping table, buffering at least part of the mapping table after compression processing in a host memory.

13. Method according to any of claims 1 to 12, characterized in that said mapping table is compressed and/or decompressed by one of the GZIP compression algorithm, LZO compression algorithm and zipper/snap compression algorithm.

14. A computer apparatus, comprising:

a processor; and

a memory communicatively coupled to the processor;

the memory stores a driver executable by the processor to enable the processor to perform the method of any one of claims 1 to 13.

15. A non-transitory computer readable medium storing a computer program, comprising: the computer program is for causing the computer to perform the method of any one of claims 1 to 13.

16. A storage controller for controlling a non-volatile storage device, and the storage controller and the non-volatile storage device are for constituting a memory system, characterized in that the storage controller is configured to:

sending the mapping table stored in the memory system to a host computer, so that at least part of the mapping table is cached in a host computer memory of the host computer after being compressed; and

and controlling the nonvolatile storage device to execute reading operation according to the mapping table which is cached in the host memory and subjected to decompression processing.

17. A memory system, comprising:

a non-volatile storage device; and

a storage controller to control the non-volatile storage, wherein the storage controller is configured to: