CN113396481A - Silicon carbide semiconductor device - Google Patents

Silicon carbide semiconductor device Download PDF

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Publication number
CN113396481A
CN113396481A CN202080012332.5A CN202080012332A CN113396481A CN 113396481 A CN113396481 A CN 113396481A CN 202080012332 A CN202080012332 A CN 202080012332A CN 113396481 A CN113396481 A CN 113396481A
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impurity region
silicon carbide
impurity
main surface
relative maximum
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增田健良
斋藤雄
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Sumitomo Electric Industries Ltd
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Sumitomo Electric Industries Ltd
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Abstract

The silicon carbide substrate has a first impurity region, a second impurity region, a third impurity region, a fourth impurity region, and a fifth impurity region. In a direction from the first main surface toward the second main surface through each of the first impurity region and the third impurity region, a concentration distribution of the p-type impurity has a first maximum value and a third relative maximum value that is closer to the first main surface than a position at which the first relative maximum value is present. In a direction from the first main surface toward the second main surface through each of the second impurity region and the fourth impurity region, a concentration distribution of the n-type impurity has a second relative maximum and a fourth relative maximum closer to the first main surface than a position at which the second relative maximum is present. The fourth relative maximum is greater than the third relative maximum, the third relative maximum is greater than the second relative maximum, and the second relative maximum is greater than the first relative maximum.

Description

Silicon carbide semiconductor device
Technical Field
The present disclosure relates to a silicon carbide semiconductor device. This application claims priority from japanese patent application No.2019-017745 filed on 4.2.2019, the entire contents of which are incorporated herein by reference.
Background
Japanese patent laid-open No.2014-041990(PTL 1) describes a trench Metal Oxide Semiconductor Field Effect Transistor (MOSFET).
Reference list
Patent document
Patent document 1: japanese patent laid-open No.2014-041990
Disclosure of Invention
A silicon carbide semiconductor device according to the present disclosure includes a silicon carbide substrate including a first major surface and a second major surface opposite the first major surface. The silicon carbide substrate includes: a first impurity region containing a p-type impurity; a second impurity region disposed on the first impurity region, the second impurity region including an n-type impurity; a third impurity region disposed on the second impurity region, the third impurity region including a p-type impurity; a fourth impurity region disposed on the third impurity region at a distance from the second impurity region, the fourth impurity region containing an n-type impurity; and a fifth impurity region in contact with each of the first impurity region and the second impurity region, the fifth impurity region containing an n-type impurity. In the first main surface, a gate trench is provided, the gate trench including a side surface contacting each of the second, third, and fourth impurity regions and a bottom surface continuous with the side surface and contacting the second impurity region. In a direction from the first main surface toward the second main surface through each of the first impurity region and the third impurity region, a concentration distribution of the p-type impurity has a first relative maximum value and a third relative maximum value that is closer to the first main surface than a position at which the first relative maximum value is present. In a direction from the first main surface toward the second main surface through each of the second impurity region and the fourth impurity region, a concentration distribution of the n-type impurity has a second relative maximum and is a fourth relative maximum closer to the first main surface than a position at which the second relative maximum is present. The fourth relative maximum is greater than the third relative maximum, the third relative maximum is greater than the second relative maximum, and the second relative maximum is greater than the first relative maximum.
Drawings
Fig. 1 is a schematic vertical cross-sectional view showing the structure of a silicon carbide semiconductor device according to a first embodiment.
Fig. 2 is a schematic transverse cross-sectional view along the line II-II in fig. 1.
Fig. 3 is a schematic view showing the concentration distribution of the first p-type impurity in the thickness direction of the silicon carbide substrate.
Fig. 4 is a schematic view showing the concentration distribution of the second p-type impurity in the thickness direction of the silicon carbide substrate.
Fig. 5 is a schematic view showing the concentration distribution of p-type impurities in the thickness direction of a silicon carbide substrate.
Fig. 6 is a schematic view showing the concentration distribution of the first n-type impurity in the thickness direction of the silicon carbide substrate.
Fig. 7 is a schematic view showing the concentration distribution of the second n-type impurity in the thickness direction of the silicon carbide substrate.
Fig. 8 is a schematic view showing the concentration distribution of the third n-type impurity in the thickness direction of the silicon carbide substrate.
Fig. 9 is a schematic view showing the concentration distribution of n-type impurities in the thickness direction of the silicon carbide substrate.
Fig. 10 is a schematic view showing a carrier concentration distribution in the thickness direction of the silicon carbide substrate.
Fig. 11 is a schematic vertical cross-sectional view showing a first step in the method of manufacturing the silicon carbide semiconductor device according to the first embodiment.
Fig. 12 is a schematic vertical cross-sectional view showing a second step in the method of manufacturing the silicon carbide semiconductor device according to the first embodiment.
Fig. 13 is a schematic vertical cross-sectional view showing a third step in the method of manufacturing the silicon carbide semiconductor device according to the first embodiment.
Fig. 14 is a schematic vertical cross-sectional view showing a fourth step in the method of manufacturing the silicon carbide semiconductor device according to the first embodiment.
Fig. 15 is a schematic vertical cross-sectional view showing the structure of a silicon carbide semiconductor device according to a second embodiment.
Fig. 16 is a schematic transverse sectional view taken along line XVI-XVI in fig. 15.
Fig. 17 is a schematic vertical cross-sectional view showing the structure of a silicon carbide semiconductor device according to a third embodiment.
Fig. 18 is a schematic transverse sectional view taken along line XVIII-XVIII in fig. 17.
Detailed Description
[ problem to be solved by the invention ]
An object of the present disclosure is to provide a silicon carbide semiconductor device capable of reducing variations in breakdown voltage.
[ advantageous effects of the present disclosure ]
According to the present disclosure, a silicon carbide semiconductor device capable of reducing variations in breakdown voltage can be provided.
[ summary of embodiments of the disclosure ]
An overview of embodiments of the present disclosure will first be described. With respect to crystallographic representations herein, individual orientations, population orientations, individual faces, and population faces are shown in [ ], < >, () and { }, respectively. A negative crystallographic index is usually indicated by a number with a bar "-" on it, however, here it is indicated by a negative sign before the number.
(1) A silicon carbide semiconductor device 200 according to the present disclosure includes a silicon carbide substrate 100, the silicon carbide substrate 100 including a first main surface 1 and a second main surface 2 opposite to the first main surface 1. The silicon carbide substrate 100 includes: a first impurity region 10 containing a p-type impurity; a second impurity region 20 disposed on the first impurity region 10, the second impurity region 20 containing an n-type impurity; a third impurity region 30 disposed on the second impurity region 20, the third impurity region 30 containing a p-type impurity; a fourth impurity region 40 disposed on the third impurity region 30 at a distance from the second impurity region 20, the fourth impurity region 40 containing an n-type impurity; and a fifth impurity region 50 contacting each of the first impurity region 10 and the second impurity region 20, the fifth impurity region 50 containing an n-type impurity. In first main surface 1, gate trench 7 is provided, gate trench 7 including side surface 5 contacting each of second impurity region 20, third impurity region 30, and fourth impurity region 40, and bottom surface 6 continuous with the side surface and contacting second impurity region 20. In a direction from first main surface 1 toward second main surface 2 through first impurity region 10 and third impurity region 30, the concentration distribution of the p-type impurity has first relative maximum value N1 and third relative maximum value N3 closer to the first main surface than the position where first relative maximum value N1 is present. In a direction from first main surface 1 toward second main surface 2 through each of second impurity region 10 and fourth impurity region 40, the concentration distribution of the N-type impurity has second relative maximum value N2 and fourth relative maximum value N4 closer to the first main surface than the position at which second relative maximum value N2 is present. The fourth relative maximum value N4 is greater than the third relative maximum value N3, the third relative maximum value N3 is greater than the second relative maximum value N2, and the second relative maximum value N2 is greater than the first relative maximum value N1.
(2) In the silicon carbide semiconductor device 200 according to (1), the total of the thickness of the first impurity region 10, the thickness of the second impurity region 20, the thickness of the third impurity region 30, and the thickness of the fourth impurity region 40 may be not more than 1.5 μm.
(3) In the silicon carbide semiconductor device 200 according to (1) or (2), the thickness of the first impurity region 10 may be not more than 0.5 μm.
(4) In the silicon carbide semiconductor device 200 according to any one of (1) to (3), the thickness of the second impurity region 20 may be not more than 0.5 μm.
(5) In the silicon carbide semiconductor device 200 according to any one of (1) to (4), the first relative maximum value Nl may be greater than 5 × 1016cm-3。
(6) In the silicon carbide semiconductor device 200 according to any one of (1) to (5),the second relative maximum value N2 may be greater than 1 x 1017cm-3。
(7) In the silicon carbide semiconductor device 200 according to any one of (1) to (6), the third relative maximum value N3 may be greater than 1 × 1018cm-3。
(8) In the silicon carbide semiconductor device 200 according to any one of (1) to (7), the fourth relative maximum value N4 may be greater than 1 × 1019cm-3。
(9) In the silicon carbide semiconductor device 200 according to any one of (1) to (8), at least a part of the first impurity region 10 may be arranged so as to be superimposed on the bottom surface 6 when viewed in a direction perpendicular to the second main surface 2.
(10) In the silicon carbide semiconductor device 200 according to (9), when viewed in the direction perpendicular to the second main surface 2, the first impurity region 10 may extend in the first direction 101 parallel to the second main surface 2 and the bottom surface 6 may extend in the second direction 102 parallel to the second main surface 2 and perpendicular to the first direction 101.
(11) In the silicon carbide semiconductor device 200 according to (9), the first impurity region 10 may extend in the first direction 101 parallel to the second main surface 2 and the bottom surface 6 may extend in the first direction 101 when viewed in the direction perpendicular to the second main surface 2.
(12) In the silicon carbide semiconductor device 200 according to any one of (1) to (12), the first impurity regions 10 may be arranged so as not to be superimposed on the bottom surface 6 when viewed in a direction perpendicular to the second main surface 2.
(13) In the silicon carbide semiconductor device 200 according to (12), when viewed in the direction perpendicular to the second main surface 2, the bottom surface 6 extends in the first direction 101 parallel to the second main surface 2 and the first impurity regions 10 extend in the second direction 102 parallel to the second main surface 2 and perpendicular to the first direction 101.
[ details of examples of the invention ]
Details of embodiments of the present disclosure will be described below. The same or corresponding elements in the following description have the same reference numerals assigned thereto, and the description of equivalents thereof will not be repeated.
(first embodiment)
The configuration of a MOSFET, which is the silicon carbide semiconductor device 200 according to the first embodiment, will be described first.
As shown in fig. 1, the silicon carbide semiconductor device 200 according to the present embodiment mainly includes a silicon carbide substrate 100, a gate electrode 64, a gate insulating film 71, an interlayer insulating film 72, a source electrode 60, and a drain electrode 63. The silicon carbide substrate 100 includes a first main surface 1 and a second main surface 2 opposite to the first main surface 1. The silicon carbide substrate 100 includes a silicon carbide single crystal substrate 4 and a silicon carbide epitaxial layer 3 provided on the silicon carbide single crystal substrate 4. The second main surface 2 is defined by a silicon carbide single crystal substrate 4. The first main surface 1 is defined by a silicon carbide epitaxial layer 3.
The silicon carbide single crystal substrate 4 is composed of hexagonal silicon carbide having a polytype of, for example, 4H. The maximum diameter of the first main surface 1 of the silicon carbide substrate 100 is, for example, 150mm and preferably not less than 150 mm. The first main surface 1 is, for example, a {0001} plane or a surface having an angle of 8 ° or less with respect to the {0001} plane. Specifically, the first main surface 1 is, for example, a (0001) plane or a surface at an angle of at most 8 ° to the (0001) plane. For example, first major surface 1 may be a (000-1) plane or a surface that makes an angle of up to 8 ° with the (000-1) plane. The silicon carbide single crystal substrate 4 has a thickness of, for example, 350 μm and not more than 500 μm.
The silicon carbide epitaxial layer 3 mainly includes a first impurity region 10, a second impurity region 20, a third impurity region 30, a fourth impurity region 40, a fifth impurity region 50, and a contact region 8. The first impurity region 10 is, for example, an electric field relaxation region. The second impurity region 20 is, for example, a current diffusion region. The third impurity region 30 is, for example, a channel layer (body region). The fourth impurity region 40 is, for example, a source region. The fifth impurity region 50 is, for example, a drift region.
The first impurity region 10 contains a p-type impurity (first p-type impurity). The first p-type impurity is a p-type impurity capable of providing a p-type such as aluminum (Al) or boron (B). The first impurity region 10 is a p-type region. The first impurity region 10 has a thickness (first thickness T1) of, for example, 0.35 μm. However, the first thickness T1 may be, for example, not more than 0.5 μm or not more than 0.4 μm. The lower limit of the first thickness T1 is not particularly limited, and may be, for example, not less than 0.1 μm.
The second impurity region 20 contains an n-type impurity (first n-type impurity). The second impurity region 20 is disposed on the first impurity region 10. The first N-type impurity is an N-type impurity capable of providing an N-type such as nitrogen (N) or phosphorus (P). The second impurity region 20 is an n-type region. The second impurity region 20 has a thickness (second thickness T2) of, for example, 0.3 μm. For example, the second thickness T2 may be no greater than 0.5 μm or no greater than 0.4 μm. However, the lower limit of the second thickness T2 is not particularly limited, and may be, for example, not less than 0.1 μm. The second thickness T2 may be less than the first thickness T1.
The third impurity region 30 contains a p-type impurity (second p-type impurity). The third impurity region 30 is disposed on the second impurity region 20. The second p-type impurity is a p-type impurity capable of providing a p-type such as aluminum (Al) or boron (B). The third impurity region 30 is a p-type region. The third impurity region 30 has a thickness (third thickness T3) of, for example, 0.2 μm. The third thickness T3 may be, for example, no greater than 0.3 μm or no greater than 0.25 μm. However, the lower limit of the third thickness T3 is not particularly limited, and may be, for example, not less than 0.1 μm. The third thickness T3 may be less than the second thickness T2.
The fourth impurity region 40 contains an n-type impurity (second n-type impurity). The fourth impurity region 40 is disposed on the third impurity region 30 at a distance from the second impurity region 20. The second N-type impurity is an N-type impurity capable of providing an N-type such as nitrogen (N) or phosphorus (P). The fourth impurity region 40 is an n-type region. The fourth impurity region 40 has a thickness (fourth thickness T4) of, for example, 0.25 μm. The fourth thickness T4 may be, for example, no greater than 0.35 μm or no greater than 0.3 μm. However, the lower limit of the fourth thickness T4 is not particularly limited, and may be, for example, not less than 0.1 μm. The fourth thickness T4 may be greater than the third thickness T3.
The fifth impurity region 50 contains an n-type impurity (third n-type impurity). The fifth impurity region 50 is in contact with each of the first impurity region 10 and the second impurity region 20. The third N-type impurity is an N-type impurity capable of providing an N-type such as nitrogen (N). The fifth impurity region 50 is an n-type region. The thickness of the fifth impurity region 50 (fifth thickness T5) is greater than the thickness of the first impurity region 10 (first thickness T1). The thickness of the fifth impurity region 50 (fifth thickness T5) may be greater than, for example, 0.5 μm.
The contact region 8 contains a third p-type impurity. The contact region 8 is, for example, in contact with each of the third impurity region 30 and the fourth impurity region 40. The third p-type impurity is a p-type impurity capable of providing a p-type such as aluminum (Al) or boron (B). The contact region 8 is a p-type region. The thickness of the contact region 8 may be greater than the thickness of the fourth impurity region 40 (fourth thickness T4).
The first p-type impurity may be the same as or different from the second p-type impurity. The first p-type impurity may be aluminum and the second p-type impurity may be aluminum. The first p-type impurity may be aluminum and the second p-type impurity may be boron. Similarly, the first p-type impurity may be the same as or different from the third p-type impurity. Similarly, the second p-type impurity may be the same as or different from the third p-type impurity.
The first n-type impurity may be the same as or different from the second n-type impurity. The first n-type impurity may be nitrogen and the second n-type impurity may be nitrogen. The first n-type impurity may be nitrogen and the second n-type impurity may be phosphorus. Similarly, the first n-type impurity may be the same as or different from the third n-type impurity. Similarly, the second n-type impurity may be the same as or different from the third n-type impurity.
The thickness of the first impurity region 10 (first thickness Tl), the thickness of the second impurity region 20 (second thickness T2), the thickness of the third impurity region 30 (third thickness T3), and the thickness of the fourth impurity region 40 (fourth thickness T4) may be, for example, not more than 1.5 μm. The sum of the first thickness T1, the second thickness T2, the third thickness T3, and the fourth thickness T4 may be, for example, not greater than 1.35 μm or not greater than 1.1 μm. However, the lower limit of the sum of the first thickness T1, the second thickness T2, the third thickness T3, and the fourth thickness T4 is not particularly limited, and may be, for example, not less than 0.5 μm.
The first main surface 1 is provided with gate trenches 7. The gate trench 7 includes side surfaces 5 and a bottom surface 6. The bottom surface 6 is continuous with the side surface 5. The side surface 5 is continuous with the first main surface 1. The side surface 5 extends in a direction substantially perpendicular to the first main surface 1. The bottom surface 6 is substantially parallel to the first main surface 1. The boundary between the side surface 5 and the bottom surface 6 may be formed to have a curvature. The depth of the gate trench 7 is, for example, not less than 0.5 μm and not more than 1.5 μm. The side surface 5 is in contact with each of the second impurity region 20, the third impurity region 30, and the fourth impurity region 40. The bottom surface 6 is in contact with the second impurity region 20. The bottom surface 6 is distant from the third impurity region 30. The bottom surface 6 may be distant from the first impurity region 10 or contact the first impurity region 10.
The gate insulating film 71 is made of, for example, silicon dioxide. The gate insulating film 71 is provided in contact with the side surfaces 5 and the bottom surface 6 of the gate trench 7. The gate insulating film is in contact with each of the second impurity region 20, the third impurity region 30, and the fourth impurity region 40 at the side surface 5. The gate insulating film is in contact with the second impurity region 20 at the bottom surface 6. A channel may be formed in the third impurity region 30 in contact with the gate insulating film 71. The thickness of the gate insulating film 71 is, for example, not less than 40nm and not more than 150 nm.
The gate electrode 64 is provided on the gate insulating film 71. The gate electrode 64 is arranged in contact with the gate insulating film 71. The gate electrode is provided to bury the groove defined by the gate insulating film 71. The gate electrode 64 is composed of a conductor such as polycrystalline silicon doped with impurities.
The source electrode 60 includes an electrode layer 61 and a source interconnect 62. The electrode layer 61 is made of, for example, a Ni alloy. The source electrode 60 is in contact with the fourth impurity region 40. The source electrode 60 may be in contact with the contact region 8. The electrode layer 61 is made of a material containing, for example, Ti, Al, and Si. The source interconnect 62 is made of a material containing AlSiCu, for example.
An interlayer insulating film 72 is provided to cover the gate electrode 64. The interlayer insulating film 72 is in contact with each of the gate electrode 64 and the gate insulating film 71. The interlayer insulating film 72 is made of, for example, undoped silicate, glass (NSG) film or phosphosilicate glass (PSG) film. The interlayer insulating film 72 electrically isolates the gate electrode 64 and the source electrode 60 from each other.
The drain electrode 63 is provided in contact with the second main surface 2 of the silicon carbide substrate 100. The drain electrode 63 is electrically connected to the fifth impurity region 50 on the second main surface 2 side. The drain electrode 63 is composed of a material that can establish ohmic contact with the n-type silicon carbide single crystal substrate 4 such as nickel silicide (NiSi). The drain electrode 63 is electrically connected to the silicon carbide single crystal substrate 4.
Fig. 2 is a schematic cross-sectional view along the line II-II in fig. 1. As shown in fig. 2, the gate trench 7 extends in a first direction 101 when viewed in a direction perpendicular to the second main surface 2. The first direction 101 corresponds to the longitudinal direction of the gate trench 7. The second direction 102 corresponds to a short side direction of the gate trench 7. The gate trench 7 is substantially rectangular when viewed in a direction perpendicular to the second major surface 2.
The first direction 101 is, for example, a <11-20> direction. The second direction 102 is, for example, a <1-100> direction. For example, the first direction 101 may be a direction resulting from a projection of the <11-20> direction onto the first main surface 1. The second direction 102 may be, for example, a direction resulting from a projection of the <1-100> direction onto the first main surface 1. Each of the first direction 101 and the second direction 102 is parallel to the second main surface 2.
As shown in fig. 2, at least a portion of the first impurity region 10 may be arranged to overlap on the bottom surface 6 of the gate trench 7 when viewed in a direction perpendicular to the second main surface 2. Preferably, the entire bottom surface 6 is arranged to be superimposed on the first impurity region 10 when viewed in a direction perpendicular to the second main surface 2. The first impurity regions 10 extend in the first direction 101 when viewed in a direction perpendicular to the second main surface 2. From another perspective, the longitudinal direction of the first impurity region 10 corresponds to the first direction 101, and the short side direction of the first impurity region 10 corresponds to the second direction 102. The width of the first impurity region 10 in the first direction 101 is larger than the width of the first impurity region 10 in the second direction 102 (first width W1). The first width W1 is, for example, not less than 0.5 μm and not more than 2.0 μm. The first width W1 may be greater than the first thickness T1.
As shown in fig. 2, the bottom surface 6 of the gate trench 7 extends in a first direction 101 when viewed in a direction perpendicular to the second main surface 2. From another perspective, the longitudinal direction of the bottom surface 6 corresponds to the first direction 101 and the short side direction of the bottom surface 6 corresponds to the second direction 102. The width of the bottom surface 6 in the first direction 101 is larger than the width of the bottom surface 6 in the second direction 102 (second width W2). The second width W2 is, for example, not less than 0.1 μm and not more than 1.5 μm. The second width W2 may be less than the first width W1. The gate trenches 7 may be disposed at regular intervals in the second direction 102. Similarly, the first impurity regions 10 may be disposed at regular intervals in the second direction 102. The interval W3 between two adjacent first impurity regions 10 is, for example, not less than 0.5 μm and not more than 5.0 μm.
Fig. 3 is a schematic view of the concentration distribution of the first p-type impurity in the thickness direction of the silicon carbide substrate. The abscissa in fig. 3 represents the position in the thickness direction. The ordinate in fig. 3 represents the concentration of the first p-type impurity. For example, the concentration of the first p-type impurity is measured in the direction along the arrow 103 in fig. 1.
As shown in fig. 3, the concentration distribution of the first p-type impurity (first concentration distribution 11) has a first relative maximum value Nl in the direction from first main surface 1 toward second main surface 2.
The concentration profile of the first p-type impurity exhibits a first relative maximum N1 at a first position a 1. From first position a1 toward first major surface 1, the concentration of the first p-type impurity monotonically decreases. Similarly, from the first position a1 toward the second main surface 2, the concentration of the first p-type impurity monotonically decreases. The first relative maximum value N1 is the maximum value of the concentration of the first p-type impurity in the first impurity region 10. The first relative maximum value N1 is, for example, greater than 5 × 1016cm-3. The first relative maximum value N1 may be greater than 1 × 10, for example17cm-3Or greater than 1X 1018cm-3. However, the upper limit of the first relative maximum value N1 is not particularly limited, and may be, for example, not more than 5 × 1018cm-3。
Fig. 4 is a schematic view of the concentration distribution of the second p-type impurity in the thickness direction of the silicon carbide substrate. The abscissa in fig. 4 represents the position in the thickness direction. The ordinate in fig. 4 represents the concentration of the second p-type impurity. For example, the concentration of the second p-type impurity is measured in the direction along the arrow 103 in fig. 1.
As shown in fig. 4, the concentration distribution of the second p-type impurity (third concentration distribution 13) has a third relative maximum value N3 in the direction from first main surface 1 toward second main surface 2.
The concentration profile of the second p-type impurity exhibits a third relative maximum value N3 at a third position a 3. From third position a3 toward first major surface 1, the concentration of the second p-type impurity monotonically decreases. Similarly, from the third position a3 toward the second main surface 2, the concentration of the second p-type impurity monotonically decreases. The third relative maximum value N3 is the maximum value of the concentration of the second p-type impurity in the third impurity region 30. The third relative maximum N3 is greater than the first relative maximum N1. Third phase relative maximumThe value N3 being, for example, greater than 1X 1018cm-3. The third relative maximum value N3 may be greater than 2 × 10, for example18cm-3Or greater than 5X 1018cm-3. However, the upper limit of the third relative maximum value N3 is not particularly limited, and may be, for example, not more than 1X 1019cm-3. As shown in fig. 4, the concentration distribution of the second p-type impurity can reach the first main surface 1. The concentration of the second p-type impurity at the first main surface 1 (second concentration N6) may be lower than the third relative maximum value N3.
Fig. 5 is a schematic view showing a concentration distribution of a p-type impurity in a thickness direction of a silicon carbide substrate. The abscissa in fig. 5 represents the position in the thickness direction. The ordinate in fig. 5 represents the concentration of the p-type impurity. For example, the concentration of the p-type impurity is measured in the direction along the arrow 103 in fig. 1. The density distribution shown in fig. 5 is formed such that the density distribution shown in fig. 3 and the density distribution shown in fig. 4 are superimposed on each other. As shown in fig. 5, the concentration distribution of the p-type impurity has, in the direction from the first main surface 1 toward the second main surface 2 through each of the first impurity region 10 and the third impurity region 30, a first relative maximum value N1 and a third relative maximum value N3 (third position A3) closer to the first main surface than the position (first position a1) at which the first relative maximum value N1 is present.
As shown in fig. 5, the concentration profile of the p-type impurity has a first relative minimum value N7. The concentration profile of the p-type impurity has a first relative minimum N7 at the fifth position a 5. The fifth position a5 is located between the first position a1 and the third position A3. The first relative minimum value N7 is less than the first relative maximum value N1.
Fig. 6 is a schematic view of the concentration distribution of the first n-type impurity in the thickness direction of the silicon carbide substrate. The abscissa in fig. 6 represents the position in the thickness direction. The ordinate in fig. 6 represents the concentration of the first n-type impurity. For example, the concentration of the first n-type impurity is measured in the direction of the arrow 103 in fig. 1.
As shown in fig. 6, the concentration distribution of the first N-type impurity (second concentration distribution 12) has a second relative maximum value N2 in the direction from first main surface 1 toward second main surface 2. The concentration distribution of the first n-type impurity exhibits a second relative relationship at a second position A2A maximum value N2. From second position a2 toward first main surface 1, the concentration of the first n-type impurity monotonically decreases. Similarly, from the second position a2 toward the second main surface 2, the concentration of the first n-type impurity monotonically decreases. The second relative maximum value N2 is the maximum value of the concentration of the first N-type impurity in the second impurity region 20. The second relative maximum N2 is greater than the first relative maximum N1. The second relative maximum value N2 is, for example, greater than 1 × 1017cm-3. The second relative maximum value N2 may be, for example, greater than 2 × 1017cm-3Or greater than 5X 1017cm-3. However, the upper limit of the second relative maximum value N2 is not particularly limited, and may be, for example, not more than 1X 1018cm-3。
Fig. 7 is a schematic view showing a concentration distribution of the second n-type impurity in the thickness direction of the silicon carbide substrate. The abscissa in fig. 7 represents the position in the thickness direction. The ordinate in fig. 7 represents the concentration of the second n-type impurity. For example, the concentration of the second n-type impurity is measured in the direction along the arrow 103 in fig. 1.
As shown in fig. 7, the concentration distribution of the second N-type impurity (fourth concentration distribution 14) has a fourth relative maximum value N4 in the direction from first main surface 1 toward second main surface 2.
The concentration distribution of the second N-type impurity exhibits a fourth relative maximum N4 at a fourth position a 4. From fourth position a4 toward first major surface 1, the concentration of the second n-type impurity monotonically decreases. Similarly, from the fourth position a4 toward the second main surface 2, the concentration of the second n-type impurity monotonically decreases. The fourth relative maximum value N4 is the maximum value of the concentration of the second N-type impurity in the fourth impurity region 40.
The fourth relative maximum N4 is greater than the third relative maximum N3. The third relative maximum N3 is greater than the second relative maximum N2. The fourth relative maximum value N4 is, for example, greater than 1 × 1019cm-3. The fourth relative maximum value N4 may be, for example, greater than 2 × 1019cm-3Or greater than 5X 1019cm-3. However, the upper limit of the fourth relative maximum value N4 is not particularly limited, and may be, for example, not more than 1X 1020cm-3. As shown in FIG. 7, the concentration distribution of the second n-type impurity can reach the first main tableFace 1. The concentration of the second N-type impurity at first main surface 1 (fourth concentration N8) is lower than fourth relative maximum value N4. The fourth concentration N8 is higher than the second concentration N6 (see fig. 4).
Fig. 8 is a schematic view showing a concentration distribution of the third n-type impurity in the thickness direction of the silicon carbide substrate. The abscissa in fig. 8 represents the position in the thickness direction. The ordinate in fig. 8 represents the concentration of the third n-type impurity. For example, the concentration of the third n-type impurity is measured in the direction of the arrow 103 in fig. 1.
As will be described later, the silicon carbide epitaxial layer is formed in one epitaxial growth. As shown in fig. 8, the concentration of the third N-type impurity (first concentration N5) is substantially constant in the direction from first main surface 1 toward second main surface 2. From another point of view, the concentration distribution of the third n-type impurity (fifth concentration distribution 15) is substantially flat between first main surface 1 and second main surface 2. Between the first main surface 1 and the second main surface 2, the fifth concentration profile 15 is continuous. In other words, the fifth concentration profile 15 does not include a discontinuous portion between the first major surface 1 and the second major surface 2. The first concentration N5 is lower than the first relative maximum N1. For example, the first concentration N5 is lower than 5X 1016cm-3。
Fig. 9 is a schematic view showing a concentration distribution of n-type impurities in the thickness direction of the silicon carbide substrate. The abscissa in fig. 9 represents the position in the thickness direction. The ordinate in fig. 9 represents the concentration of the n-type impurity. For example, the concentration of the n-type impurity is measured in the direction along the arrow 103 in fig. 1. The density distribution shown in fig. 9 is formed as the density distribution shown in fig. 6, and the density distribution shown in fig. 7 and the density distribution shown in fig. 8 are superimposed on each other. As shown in fig. 9, the concentration distribution of the N-type impurity has, in the direction from the first main surface 1 toward the second main surface 2 through each of the second impurity region 20 and the fourth impurity region 40, a second relative maximum value N2 and a fourth relative maximum value N4 (second position a2) closer to the first main surface than the position (fourth position a4) at which the second relative maximum value N2 is present.
As shown in fig. 9, the concentration distribution of the N-type impurity has a second relative minimum value N9. The concentration profile of the N-type impurity has a second relative minimum value N9 at the sixth position a 6. The sixth position a6 is located between the second position a2 and the fourth position a 4. The second relative minimum value N9 is less than the second relative maximum value N2. The second relative minimum value N9 may be greater than the first concentration N5.
Fig. 10 is a schematic view showing a carrier concentration distribution in the thickness direction of the silicon carbide substrate. The abscissa in fig. 10 represents the position in the thickness direction. The ordinate in fig. 10 represents the carrier concentration. The carrier concentration is expressed as an absolute value of a difference between the n-type impurity concentration and the p-type impurity concentration. For example, the carrier concentration is measured in the direction along arrow 103 in fig. 1. The carrier concentration distribution is shown by a solid line.
As shown in fig. 10, at the first position a1 in the first impurity region, the carrier concentration distribution exhibits a fifth relative maximum value n 1. Similarly, at the second position a2 in the second impurity region 20, the carrier concentration distribution exhibits a sixth relative maximum value n 2. Similarly, at the third position a3 in the third impurity region 30, the carrier concentration distribution exhibits a seventh relative maximum value n 3. Similarly, at the fourth position a4 in the fourth impurity region 40, the carrier concentration distribution exhibits an eighth relative maximum value n 4. The eighth relative maximum n4 is greater than the seventh relative maximum n 3. The seventh relative maximum n3 is greater than the sixth relative maximum n 2. The sixth relative maximum n2 is greater than the fifth relative maximum n 1. The fifth relative maximum value n1 is larger than the carrier concentration in the fifth impurity region 50 (third concentration n 5).
In a direction perpendicular to the second main surface 2, the fourth position a4 is located between the third position A3 and the first main surface 1. Similarly, the third position A3 is located between the fourth position a4 and the second position a2 in a direction perpendicular to the second major surface 2. Similarly, in a direction perpendicular to the second major surface 2, the second position a2 is located between the third position A3 and the first position a 1. Similarly, in a direction perpendicular to the second major surface 2, the first position a1 is located between the second position a2 and the second major surface 2.
At the boundary between the first impurity region 10 and the fifth impurity region 50, the carrier concentration distribution has a relative minimum. At the boundary between the first impurity region 10 and the second impurity region 20, the carrier concentration distribution has a relative minimum. At the boundary between the second impurity region 20 and the third impurity region 30, the carrier concentration distribution has a relative minimum. At the boundary between the third impurity region 30 and the fourth impurity region 40, the carrier concentration distribution has a relative minimum value.
As shown in fig. 10, in the first impurity region 10, the first concentration distribution 11, the second concentration distribution 12, and the fifth concentration distribution 15 may overlap each other. From another perspective, the first impurity region 10 may include a first n-type impurity, a first p-type impurity, and a third n-type impurity. In the second impurity region 20, the first concentration distribution 11, the second concentration distribution 12, the third concentration distribution 13, and the fifth concentration distribution 15 may overlap each other. From another perspective, the second impurity region 20 may include a first n-type impurity, a first p-type impurity, a second n-type impurity, and a third n-type impurity. In the third impurity region 30, the first concentration distribution 11, the second concentration distribution 12, the third concentration distribution 13, the fourth concentration distribution 14, and the fifth concentration distribution 15 may overlap each other. From another perspective, the third impurity region 30 may include a first n-type impurity, a first p-type impurity, a second n-type impurity, a second p-type impurity, and a third n-type impurity.
In the fourth impurity region 40, the second concentration distribution 12, the third concentration distribution 13, the fourth concentration distribution 14, and the fifth concentration distribution 15 may overlap each other. From another perspective, the fourth impurity region 40 may include a first p-type impurity, a second n-type impurity, a second p-type impurity, and a third n-type impurity. In the fifth impurity region 50, the first concentration distribution 11 and the fifth concentration distribution 15 may overlap each other. From another perspective, the fifth impurity region 50 may include the first n-type impurity and the third n-type impurity.
A method of measuring the concentration of the p-type impurity and the concentration of the n-type impurity in each impurity region will now be described.
The concentration of the p-type impurity and the concentration of the n-type impurity in each impurity region can be measured by Secondary Ion Mass Spectrometry (SIMS). For example, a secondary ion mass spectrometer manufactured by Cameca is used as the measurement device. For example, the measurement pitch is set to 0.01 μm. When nitrogen is detected as an n-type impurity, cesium (Cs) is used for the primary ion beam. The primary ion energy was set at 14.5 keV. The secondary ion polarity is negative. When detecting aluminum or boron as a p-type impurity, oxygen (O2) is used for the primary ion beam. The primary ion energy was set at 8 keV. The secondary ion polarity is positive. The concentration of the p-type impurity and the concentration of the n-type impurity were measured at the center of the silicon carbide epitaxial substrate.
A method of measuring the thickness of each impurity region will now be described.
Scanning Capacitance Microscopy (SCM) is used in a method of distinguishing p-type and n-type regions. For example, NanoScope IV manufactured by Bruker AXS was used as a measuring device. SCM is a method of visualizing the carrier concentration distribution in semiconductors. Specifically, the surface of the sample was scanned with a metal-coated silicon probe. At this time, a high-frequency voltage was applied to the sample. The majority carriers are excited to modulate the capacitance of the system. The frequency of the high-frequency voltage applied to the sample was set to 100kHz, and the voltage was set to 4.0V. The thickness of each impurity region was measured by SCM.
The operation of the MOSFET200 according to the present embodiment will now be described. In a state where a voltage applied to the gate electrode 64 is lower than a threshold voltage, that is, in an off state, even when a voltage is applied across the source electrode 60 and the drain electrode 63, the pn junction between the third impurity region 30 and the second impurity region 20 is reverse-biased and does not conduct therebetween. When a voltage equal to or higher than the threshold voltage is applied to the gate electrode 64, an inversion layer is formed in the channel region around the contact portion of the third impurity region 30 and the gate insulating film 71. Therefore, the fourth impurity region 40 and the second impurity region 20 are electrically connected to each other and current flows between the source electrode 60 and the drain electrode 63. The MOSFET200 operates as described above.
A method of manufacturing the silicon carbide semiconductor device 200 according to the present embodiment will now be described.
First, a step of preparing the silicon carbide substrate 100 is performed. The silicon carbide single crystal substrate 4 is prepared, for example, by slicing a substrate from a silicon carbide single crystal ingot grown by the modified Lely method and mirror-polishing the surface of the substrate. The silicon carbide single crystal substrate 4 is composed of hexagonal silicon carbide having a polytype of, for example, 4H. The silicon carbide single crystal substrate 4 has a diameter of, for example, 150 mm.
Then theThe step of forming the silicon carbide epitaxial layer is performed. For example, a carrier gas containing hydrogen, a raw material gas containing silane and propane, and a dopant gas containing nitrogen are supplied onto the silicon carbide single crystal substrate 4, and the silicon carbide single crystal substrate 4 is heated to, for example, about 1550 ℃ at a pressure of 100 mbar (10 kPa). Thereby forming a silicon carbide epitaxial layer 3 having an n-type on the silicon carbide single crystal substrate 4 (see fig. 11). The silicon carbide epitaxial layer 3 is doped with nitrogen as an n-type impurity. The concentration of the n-type impurity is set to, for example, 8.0X 1015cm-3. As described above, the silicon carbide substrate 100 including the silicon carbide single crystal substrate 4 and the silicon carbide epitaxial layer 3 provided on the silicon carbide single crystal substrate is prepared. The silicon carbide substrate 100 includes a first main surface 1 and a second main surface 2. The first main surface 1 is, for example, a 0001 plane or a surface at an angle of at most 8 ° to a 0001 plane.
Ions are then implanted into the silicon carbide epitaxial layer 3. First, a first ion implantation mask (not shown) is provided on the first main surface 1. Then, ions of the first p-type impurity are implanted into the silicon carbide epitaxial layer 3. Thereby forming the first impurity region 10 having a p-type. For example, aluminum is used as the first p-type impurity. The ion implantation energy is, for example, not higher than 900 keV. Then, the first ion implantation mask (not shown) is removed from the first main surface 1.
A second ion implantation mask (not shown) is provided on the first major surface 1. The second ion implantation mask covers, for example, a guard ring region (not shown). Then, ions of the first n-type impurity are implanted into the silicon carbide epitaxial layer 3. Thereby forming the second impurity region 20 having an n-type. The second impurity region 20 is formed to be in contact with the first impurity region 10. For example, nitrogen is used as the first n-type impurity. The ion implantation energy is, for example, not higher than 900 keV.
Then, ions of a second p-type impurity are implanted into the silicon carbide epitaxial layer 3. Thereby forming the third impurity region 30 having a p-type. The third impurity region 30 is formed in contact with the second impurity region 20. For example, aluminum is used as the second p-type impurity. The ion implantation energy is, for example, not higher than 900 keV.
Then, ions of a second n-type impurity are implanted into the silicon carbide epitaxial layer 3. Thereby forming the fourth impurity region 40 having an n-type. The second impurity region 40 is formed to be in contact with the third impurity region 30. For example, phosphorus is used as the second n-type impurity. The ion implantation energy is, for example, not higher than 900 keV. Then, the second ion implantation mask (not shown) is removed from the first main surface 1.
A third ion implantation mask (not shown) is then provided on the first major surface 1. Ions of the third p-type impurity are implanted into the silicon carbide epitaxial layer 3. Thereby forming a contact region 8 having a p-type. The contact region 8 is formed in contact with each of the third impurity region 30 and the fourth impurity region 40. For example, aluminum is used as the third p-type impurity. The ion implantation energy is, for example, not higher than 900 keV. Then, the third ion implantation mask (not shown) is removed from the first main surface 1. The portion of the silicon carbide epitaxial layer 3 where no ions are implanted is the fifth impurity region 50. As described above, the silicon carbide substrate 100 including the first impurity region 10, the second impurity region 20, the third impurity region 30, the fourth impurity region 40, the fifth impurity region 50, and the contact region 8 is prepared (see fig. 12).
Then, an etching mask (not shown) is formed on the first main surface 1. The etching mask is made of, for example, a material including a deposited oxide film. The etching mask has an opening provided above a region where the gate trench 7 is to be formed. The silicon carbide substrate 100 is then etched using the etch mask. For example, at SF6And O2The fourth impurity region 40, the third impurity region 30, and the second impurity region 20 are anisotropically etched. For example, Electron Cyclotron Resonance (ECR) plasma etching is employed as the anisotropic etching. A gate trench 7 is thus provided in the first main surface 1 (see fig. 13). The gate trench 7 includes side surfaces 5 and a bottom surface 6. The side surface 5 is in contact with the second impurity region 20, the third impurity region 30, and the fourth impurity region 40. The bottom surface 6 is in contact with the second impurity region 20.
Then, a gate insulating film 71 is formed. Specifically, the gate insulating film 71 is formed in contact with the first main surface 1, the side surface 5, and the bottom surface 6. The gate insulating film 71 is in contact with the fourth impurity region 40, the third impurity region 30, and the second impurity region 20 at the side surface 5. The gate insulating film 71 is in contact with the second impurity region 20 at the bottom surface 6. The gate insulating film 71 is in contact with the fourth impurity region 40 at the first main surface 1. The gate insulating film 71 has a thickness of, for example, not less than 40nm and not more than 150 nm.
Then, an NO annealing step is performed. Specifically, the silicon carbide substrate 100 on which the gate insulating film 71 has been formed is subjected to heat treatment in an atmosphere containing nitrogen at a temperature of, for example, not lower than 1100 ℃ and not higher than 1300 ℃. Examples of nitrogen-containing gases include nitric oxide diluted by 10% with nitrogen. The silicon carbide substrate 100 is annealed in a gas containing nitrogen for a period of not less than 30 minutes and not more than 360 minutes.
Then, the gate electrode 64 is formed. Specifically, the gate electrode 64 is formed on the gate insulating film 71 to bury the groove defined by the gate insulating film 71. The gate electrode 64 is made of, for example, a material including polycrystalline silicon containing impurities. Then, an interlayer insulating film 72 is formed to cover the gate electrode 64. The interlayer insulating film 72 includes, for example, at least any one of an NSG film and a PSG film.
Then, the source electrode 60 is formed. Specifically, the interlayer insulating film 72 and the gate insulating film 71 are removed from the region where the source electrode 60 is to be formed. Therefore, a part of the fourth impurity region 40 and the contact region 8 is exposed through the interlayer insulating film 72 and the gate insulating film 71 (see fig. 14). Then, an electrode layer 61 is formed on the first main surface 1 in contact with both the fourth impurity region 40 and the contact region 8. The electrode layer 61 is formed by sputtering, for example. The electrode layer 61 is made of a material containing TiAlSi, for example.
Then, the silicon carbide substrate 100 in which the electrode layer 61 has been formed is subjected to Rapid Thermal Annealing (RTA) for about two minutes, for example, at a temperature not lower than 900 ℃ and not higher than 1100 ℃. At least a portion of the electrode layer 61 is thus converted to a silicide as a result of reaction with silicon contained in the silicon carbide substrate 100. The electrode layer 61 thus establishes ohmic contact with the fourth impurity region 40. Preferably, the electrode layer 61 establishes ohmic contact with each of the fourth impurity region 40 and the contact region 8.
Then, the source interconnect 62 is formed in contact with the electrode layer 61 and covers the interlayer insulating film 72. The source interconnect 62 is preferably composed of a material containing Al, such as a material containing AlSiCu. Then, the back surface of the silicon carbide single crystal substrate 4 is polished. The thickness of the silicon carbide single crystal substrate 4 is thus reduced. Then, the drain electrode 63 is formed. Drain electrode 63 is formed in contact with second main surface 2 of silicon carbide substrate 100. The drain electrode 63 is made of a material containing NiSi, for example. The drain electrode 63 may be made of, for example, TiAlSi.
Although the drain electrode 63 is preferably formed by sputtering, it may be formed by vapor deposition. After the drain electrode 63 is formed, it is heated, for example, by laser annealing. Thus, at least a portion of the drain electrode 63 is converted into silicide. The MOSFET200 shown in fig. 1 is fabricated as described above.
(second embodiment)
The configuration of the silicon carbide semiconductor device 200 according to the second embodiment will now be described. The silicon carbide semiconductor device 200 according to the second embodiment differs from the silicon carbide semiconductor device 200 according to the first embodiment mainly in that the first impurity regions 10 are opposed to the contact regions 8, but is otherwise similar to the silicon carbide semiconductor device 200 according to the first embodiment. A description is given below in which a difference from the silicon carbide semiconductor device 200 according to the first embodiment is focused.
As shown in fig. 15, in the silicon carbide semiconductor device 200 according to the second embodiment, the first impurity region 10 is opposed to the contact region 8. Viewed from another perspective, first impurity region 10 is located between contact region 8 and second major surface 2. From another perspective, the first impurity region 10 is disposed not to oppose the bottom surface 6 of the gate trench 7. The first impurity region 10 is opposite to each of the third impurity region 30 and the fourth impurity region 40. The first impurity region 10 is opposed to the electrode layer 61.
Fig. 16 is a schematic transverse sectional view taken along line XVI-XVI in fig. 15. As shown in fig. 16, each of the first impurity regions 10 and the gate trenches 7 extends in the first direction 101 when viewed in a direction perpendicular to the second main surface 2. The first impurity regions 10 are arranged so as not to overlap the gate trenches 7 when viewed in a direction perpendicular to the second main surface 2. In the second direction 102, the gate trenches 7 and the first impurity regions 10 are alternately arranged. The gate trench 7 is located between two adjacent first impurity regions 10 when viewed in a direction perpendicular to the second main surface 2.
(third embodiment)
The configuration of the silicon carbide semiconductor device 200 according to the third embodiment will now be described. The silicon carbide semiconductor device 200 according to the third embodiment differs from the silicon carbide semiconductor device 200 according to the first embodiment mainly in that the extending direction of the first impurity regions 10 is orthogonal to the extending direction of the gate trenches 7, but is otherwise similar to the silicon carbide semiconductor device 200 according to the first embodiment. A description is given below in which a difference from the silicon carbide semiconductor device 200 according to the first embodiment is focused.
As shown in fig. 17, in the silicon carbide semiconductor device 200 according to the third embodiment, the first impurity region 10 is opposed to the bottom surface 6 of the gate trench 7, the third impurity region 30, the contact region 8, and the electrode layer 61. From another perspective, the first impurity region 10 is located between each of the bottom surface 6 of the gate trench 7, the third impurity region 30, the contact region 8, and the electrode layer 61 and the second main surface 2.
Fig. 18 is a schematic transverse cross-sectional view taken along line XVIII-XVIII in fig. 17. As shown in fig. 18, when viewed in a direction perpendicular to the second main surface 2, the bottom surface 6 of the gate trench 7 extends in a first direction 101 parallel to the second main surface 2, and the first impurity region 10 extends in a second direction 102 parallel to the second main surface 2 and perpendicular to the first direction 101. From another perspective, the extending direction of the first impurity region 10 is orthogonal to the extending direction of the gate trench 7. The longitudinal direction of the first impurity region 10 corresponds to the short side direction of the gate trench. Similarly, the short side direction of the first impurity region 10 corresponds to the longitudinal direction of the gate trench.
The first impurity regions 10 may be disposed at regular intervals along the first direction 101. The fifth impurity region 50 is disposed between two adjacent first impurity regions 10. The bottom surface 6 of the gate trench 7 includes a portion (first portion) that overlaps the first impurity region 10 and a portion (second portion) that does not overlap the first impurity region 10, when viewed in a direction perpendicular to the second main surface 2. The fifth current flows to the drain electrode 63 through the fifth impurity region 50.
Although the silicon carbide semiconductor device 200 according to the present disclosure is described above with reference to a MOSFET including the gate trench 7 by way of example, the silicon carbide semiconductor device 200 according to the present disclosure is not limited thereto. The silicon carbide semiconductor device 200 according to the present disclosure may be, for example, an Insulated Gate Bipolar Transistor (IGBT).
The function and effect of the silicon carbide semiconductor device 200 according to the embodiment will now be described.
In the silicon carbide semiconductor device 200, each of the first impurity region 10 (embedded p-type region), the second impurity region 20 (n-type current diffusion region), and the third impurity region 30 (p-type channel region) is formed by ion implantation, and the concentration distribution of the first n-type impurity in the second impurity region 20 is interposed between the concentration distribution of the first p-type impurity in the first impurity region 10 and the concentration distribution of the second p-type impurity in the third impurity region 30. Therefore, in the second impurity region 20, the first p-type impurity in the tail portion of the concentration distribution of the first p-type impurity and the second p-type impurity in the tail portion of the concentration distribution of the second p-type impurity are mixed together.
When the interval between the first impurity region 10 and the third impurity region 30 is small (in other words, the thickness of the second impurity region 20 is small), the first n-type impurity in the second impurity region 20 is neutralized by being superimposed with the tail of the concentration distribution of the first p-type impurity in the first impurity region 10 and with the tail of the concentration distribution of the second p-type impurity in the third impurity region 30. In this case, the second impurity region 20 does not have the n-type and the silicon carbide semiconductor device 200 does not operate. In order to set the second impurity region 20 to the n-type, the second impurity region 20 should have a large thickness. As the thickness of the second impurity region 20 increases, the silicon carbide epitaxial layer 3 has a greater thickness. Therefore, the silicon carbide epitaxial layer 3 is generally formed by epitaxial growth divided into two stages.
Specifically, first, a first silicon carbide layer is formed by epitaxial growth. Then, the first impurity region 10 is formed by ion implantation into the first silicon carbide layer. Then, a second silicon carbide layer is formed on the first silicon carbide layer by epitaxial growth. Then, the second impurity region 20, the third impurity region 30, and the fourth impurity region 40 are formed by ion implantation into the second silicon carbide layer. Then, a gate trench 7 is formed in the second silicon carbide layer.
The silicon carbide layer formed by the first epitaxial growth has a first thickness variation. The thickness of the first silicon carbide layer corresponds to the thickness of the drift layer (fifth impurity region 50). Since the drift layer has a larger thickness, the silicon carbide semiconductor device 200 has a higher breakdown voltage. In contrast, since the drift layer has a smaller thickness, the silicon carbide semiconductor device 200 has a lower breakdown voltage. In other words, the greater the variation in the thickness of the first silicon carbide layer, the greater the variation in the breakdown voltage of the silicon carbide semiconductor device 200.
The second silicon carbide layer formed by the second epitaxial growth has a second thickness variation. Since the thickness of the second silicon carbide layer is large, the distance between the bottom surface 6 of the gate trench 7 and the fourth impurity region 40 is long. The silicon carbide semiconductor device 200 has a lower breakdown voltage with a longer distance. In contrast, since the thickness of the second silicon carbide layer is small, the distance between the bottom surface 6 of the gate trench 7 and the fourth impurity region 40 is short. With a shorter distance, the silicon carbide semiconductor device 200 has a higher breakdown voltage. In other words, the greater the variation in the thickness of the second silicon carbide layer, the greater the variation in the breakdown voltage of the silicon carbide semiconductor device 200.
According to silicon carbide semiconductor device 200 in the present embodiment, the concentration distribution of the first p-type impurity has first relative maximum value Nl in the direction from first main surface 1 toward second main surface 2. The concentration distribution of the first N-type impurity has a second relative maximum value N2 in a direction from first main surface 1 toward second main surface 2. The concentration distribution of the second p-type impurity has a third relative maximum value N3 in the direction from first main surface 1 toward second main surface 2. The third relative maximum N3 is greater than the second relative maximum N2, and the second relative maximum N2 is greater than the first relative maximum N1.
In an example where the second relative maximum value N2 is greater than the first relative maximum value Nl, the possibility that the first N-type impurity in the second impurity region 20 is neutralized by the first p-type impurity in the first impurity region 10 is smaller than an example where the second relative maximum value N2 is smaller than the first relative maximum value N1. Therefore, in an example where the second relative maximum value N2 is greater than the first relative maximum value N1, the second impurity region 20 may have a smaller thickness than an example where the second relative maximum value N2 is smaller than the first relative maximum value N1. Thus, the silicon carbide epitaxial layer can be formed in one epitaxial growth. Therefore, the thickness variation of the silicon carbide epitaxial layer can be reduced as compared with the example in which the silicon carbide epitaxial layer is formed in two stages in the epitaxial growth. Therefore, variations in breakdown voltage of the silicon carbide semiconductor device 200 can be reduced.
The lead time for forming the silicon carbide epitaxial layer may be shorter than the example of forming the silicon carbide epitaxial layer by two-stage epitaxial growth. Therefore, the cost of the silicon carbide semiconductor device 200 can be reduced.
The silicon carbide substrate 100 after the second epitaxial growth may have been deformed as compared to the silicon carbide substrate 100 after the first epitaxial growth. When the silicon carbide epitaxial layer is formed by two-stage epitaxial growth, exposure failure may occur due to the influence of deformation of the silicon carbide substrate 100. By forming the silicon carbide epitaxial layer by one epitaxial growth, the exposure failure can be suppressed.
It is to be understood that the embodiments disclosed herein are illustrative and not restrictive in all respects. The scope of the present invention is defined by the claims, rather than the above description, and is intended to include any modifications within the scope and meaning equivalent to the scope and meaning of the claims.
List of reference numerals
1 a first major surface; 2 a second major surface; 3, silicon carbide epitaxial layer; a4 silicon carbide single crystal substrate; 5 side surfaces; 6 bottom surface; 7, a grid groove; 8 a contact zone; 10 a first impurity region; 11 a first concentration profile; 12 a second concentration profile; 13 a third concentration profile; 14 a fourth concentration profile; 15 fifth concentration profile; 20 a second impurity region; 30 a third impurity region; 40 a fourth impurity region; 50 a fifth impurity region; 60 a source electrode; 61 an electrode layer; 62 source interconnect; 63 a drain electrode; a 64 gate electrode; 71 a gate insulating film; 72 an interlayer insulating film; a 100 silicon carbide substrate; 101 a first direction; 102 a second direction; 103 arrow heads; 200 MOSFETs (silicon carbide semiconductor devices); a1 first position; a2 second position; a third position of a 3; a4 fourth position; a5 fifth position; a sixth position of a 6; n1 first relative maximum; n2 second relative maximum; n3 third relative maximum; n4 fourth relative maximum; a first concentration of N5; a second concentration of N6; n7 first relative minimum; a fourth concentration of N8; n9 second relative minimum; a first thickness T1; t2 second thickness; t3 third thickness; t4 fourth thickness; a fifth thickness T5; a first width W1; w2 second width; w3 interval; n1 fifth relative maximum; a sixth relative maximum of n 2; n3 seventh relative maximum; n4 eighth relative maximum; n5 third concentration.

Claims (13)

1. A silicon carbide semiconductor device comprising:
a silicon carbide substrate comprising a first major surface and a second major surface opposite the first major surface, wherein,
the silicon carbide substrate includes:
a first impurity region containing a p-type impurity,
a second impurity region disposed on the first impurity region, the second impurity region containing an n-type impurity,
a third impurity region disposed on the second impurity region, the third impurity region containing a p-type impurity,
a fourth impurity region disposed on the third impurity region at a distance from the second impurity region, the fourth impurity region containing an n-type impurity, an
A fifth impurity region in contact with each of the first impurity region and the second impurity region, the fifth impurity region containing an n-type impurity,
in the first main surface, a gate trench including a side surface in contact with each of the second, third, and fourth impurity regions and a bottom surface continuous with the side surface and in contact with the second impurity region is provided,
a concentration distribution of the p-type impurity has a first relative maximum and a third relative maximum located closer to the first main surface than a position where the first relative maximum is present, in a direction from the first main surface toward the second main surface through each of the first impurity region and the third impurity region,
a concentration distribution of the n-type impurity has, in a direction from the first main surface toward the second main surface through each of the second impurity region and the fourth impurity region, a second relative maximum and a fourth relative maximum located closer to the first main surface than a position at which the second relative maximum is present, and
the fourth relative maximum is greater than the third relative maximum, the third relative maximum is greater than the second relative maximum, and the second relative maximum is greater than the first relative maximum.
2. The silicon carbide semiconductor device according to claim 1,
a total of a thickness of the first impurity region, a thickness of the second impurity region, a thickness of the third impurity region, and a thickness of the fourth impurity region is not more than 1.5 μm.
3. The silicon carbide semiconductor device according to claim 1 or 2, wherein,
the thickness of the first impurity region is not more than 0.5 μm.
4. The silicon carbide semiconductor device according to any one of claims 1 to 3, wherein,
the thickness of the second impurity region is not more than 0.5 μm.
5. The silicon carbide semiconductor device according to any one of claims 1 to 4, wherein,
the first relative maximum is greater than 5 x 1016cm-3。
6. The silicon carbide semiconductor device according to any one of claims 1 to 5, wherein,
said second relative maximum being greater than 1 x 1017cm-3。
7. The silicon carbide semiconductor device according to any one of claims 1 to 6, wherein,
the third relative maximum value is greater than 1 x 1018cm-3。
8. The silicon carbide semiconductor device according to any one of claims 1 to 7, wherein,
the fourth relative maximum is greater than 1 × 1019cm-3。
9. The silicon carbide semiconductor device according to any one of claims 1 to 8, wherein,
at least a portion of the first impurity region is arranged to be superimposed on the bottom surface when viewed in a direction perpendicular to the second main surface.
10. The silicon carbide semiconductor device according to claim 9, wherein,
the bottom surface extends in a first direction parallel to the second main surface when viewed in the direction perpendicular to the second main surface, and the first impurity region extends in a second direction parallel to the second main surface and perpendicular to the first direction.
11. The silicon carbide semiconductor device according to claim 9, wherein,
when viewed in the direction perpendicular to the second main surface, the first impurity region extends in a first direction parallel to the second main surface and the bottom surface extends in the first direction.
12. The silicon carbide semiconductor device according to any one of claims 1 to 8, wherein,
the first impurity region is arranged so as not to be superimposed on the bottom surface when viewed in a direction perpendicular to the second main surface.
13. The silicon carbide semiconductor device according to claim 12, wherein,
when viewed in the direction perpendicular to the second main surface, the first impurity region extends in a first direction parallel to the second main surface and the bottom surface extends in the first direction.
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