CN113381778A - Polarization diversity signal receiving method based on FPGA - Google Patents

Polarization diversity signal receiving method based on FPGA Download PDF

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CN113381778A
CN113381778A CN202110644388.9A CN202110644388A CN113381778A CN 113381778 A CN113381778 A CN 113381778A CN 202110644388 A CN202110644388 A CN 202110644388A CN 113381778 A CN113381778 A CN 113381778A
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signal
hand
intermediate frequency
frequency
phase
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邵力强
李小峰
袁瑞
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Chengdu Xieying Technology Co ltd
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Chengdu Xieying Technology Co ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/16—Circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0079—Receiver details
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

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Abstract

The invention provides a polarization diversity signal receiving method based on an FPGA (field programmable gate array), which belongs to the technical field of telemetering signal receiving, and is characterized in that an antenna is used for receiving an input signal and carrying out radio frequency processing on the input signal to obtain an intermediate frequency left-handed signal and an intermediate frequency right-handed signal; inputting the intermediate frequency left-handed signal and the intermediate frequency right-handed signal into a differential mode ring for phase synchronization processing to obtain an in-phase signal, and outputting the in-phase signal output by the differential mode ring to a common mode ring; the common mode ring is used for eliminating frequency offset of the output signal of the differential mode ring to obtain a same-frequency same-phase signal; and combining and outputting two paths of signals with the same frequency and the same phase obtained by processing the output of the differential mode loop and the output of the common mode loop in a maximum ratio to complete the polarization diversity signal receiving based on the FPGA. The invention provides an improved polarization diversity receiver structure, and combines the advantages of an SCA modeling tool platform, so as to solve the problem of removing various frequency deviation components by utilizing the high-pass characteristic of a uniformly sampled second-order digital phase-locked loop error transfer function after frequency discrimination.

Description

Polarization diversity signal receiving method based on FPGA
Technical Field
The invention belongs to the technical field of telemetering signal receiving, and particularly relates to a polarization diversity signal receiving method based on an FPGA.
Background
Diversity signal reception techniques are commonly used in telemetry signal reception. Because the distance between the remote measurement target and the ground measurement and control station is long, and the power of the transmitter of the aircraft such as a satellite, a missile and the like cannot be compared with that of the transmitter of ground equipment due to the size limitation. Therefore, the signals received by the ground measurement and control equipment are very weak, and useful signals are submerged in strong interference and various noises. Meanwhile, due to the relative motion between the aircraft and the ground measurement and control station, the carrier frequency of the received signal changes along with time, namely the Doppler frequency is contained. When severe bursty interference, selective interference, multipath interference, deep zero fading and other high-rate and high-dynamic fast fading conditions exist, even if the transmission power can be increased, the expected effect cannot be obtained. In a complex and severe electromagnetic environment, under the condition of fast fading, in order to utilize the received signal power to the maximum extent, reduce the loss of the obtained data, reduce the influence of the variation factor of the transmission characteristic of the electric wave, compress the fluctuation of the signal level, improve the distribution rate of the signal amplitude, reduce the probability of the signal level fading below a set threshold value, and improve the signal-to-noise ratio, thereby improving the effectiveness and reliability of signal transmission, a diversity reception method can be adopted, and the diversity reception is an effective measure against the fast fading.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides the polarization diversity signal receiving method based on the FPGA, which solves the problem that various frequency deviation components are removed by utilizing the high-pass characteristic of a uniformly sampled second-order digital phase-locked loop error transfer function after frequency discrimination.
In order to achieve the above purpose, the invention adopts the technical scheme that:
the scheme provides a polarization diversity signal receiving method based on an FPGA, which comprises the following steps:
s1, receiving an input signal by using an antenna and carrying out radio frequency processing on the input signal to obtain an intermediate frequency left-handed signal and an intermediate frequency right-handed signal;
s2, inputting the intermediate frequency left-handed signal and the intermediate frequency right-handed signal into a differential mode ring for phase synchronization processing to obtain an in-phase signal, and inputting the in-phase signal output by the differential mode ring into a common mode ring;
s3, eliminating frequency offset of the differential mode ring output signal by using the common mode ring to obtain a same-frequency same-phase signal;
and S4, combining and outputting two paths of signals with the same frequency and the same phase obtained by processing the output of the differential mode loop and the output of the common mode loop in the maximum ratio, and completing the polarization diversity signal receiving based on the FPGA.
Further, the intermediate frequency left-hand signal S of the step S1L(t) and a medium frequency right-hand signal SRThe expressions of (t) are as follows:
SL(t)＝Acos(wLt+φ+θL)+nL
SR(t)＝Acos(wRt+φ+θR)+nR
where A denotes the amplitude of the signal, wLAnd wRRespectively representing the intermediate frequency left-hand signal SL(t) and a medium frequency right-hand signal SR(t) center frequency, θLAnd thetaRRespectively representing the intermediate frequency left-hand signal SL(t) and a medium frequency right-hand signal SR(t) initial phase, phi denotes modulation data information, nLAnd nRRespectively representing the intermediate frequency left-hand signal SL(t) and a medium frequency right-hand signal SR(t) noise.
Further, the intermediate frequency left-handed signal SL(t) and a medium frequency right-hand signal SR(t) local signal diplex signal INAnd quadrature branch signal QNThe expressions are respectively as follows:
IN＝2cos(wt)
QN＝2sin(wt)
wherein w represents the local carrier frequency, t represents time, and the local signal is the same-direction branch signal INAnd quadrature branch signal QNIs 0.
Further, the method for performing phase synchronization processing in step S2 includes the following steps:
s21, respectively carrying out orthogonal down-conversion on the intermediate frequency left-hand signal and the intermediate frequency right-hand signal to obtain a left-hand signal homodromous component ILQuadrature component Q of the left-hand signalLD-signal homodromous component IRAnd quadrature component Q of the right-hand signalR；
S22, filtering the homodromous component I of the left-handed signal by using a low-pass filterLQuadrature component Q of the left-hand signalLD-signal homodromous component IRAnd quadrature component Q of the right-hand signalRTo obtain a low-pass filtered signal I'L、Q'L、I'RAnd Q'R；
S23, mixing signal I'L、Q'L、I'RAnd Q'RPerforming cross-correlation operation to obtain an in-phase signal I and an orthogonal signal Q, and performing arc tangent operation on the in-phase signal I and the orthogonal signal Q to obtain a phase difference of the in-phase signal I and the orthogonal signal Q;
and S24, inputting the phase difference into a loop filter, and respectively inputting output signals of the filter into a corresponding first digital oscillator NCO and a corresponding second digital oscillator NCO in opposite polarities to realize phase synchronization of the intermediate-frequency left-hand signal and the intermediate-frequency right-hand signal and obtain an in-phase signal.
Further, the cocurrent branch signal I 'in the step S22'LAnd quadrature shunt signal Q'LAre respectively:
I'L＝Acos((wL-w)t+φ+θL)+n'LI
Q'L＝Asin((w-wL)t-φ-θL)+n'LQ
where A denotes the amplitude of the signal, wLRepresenting the intermediate frequency left-hand signal SL(t) center frequency, θLRepresenting the intermediate frequency left-hand signal SL(t) initial phase, phi, represents modulated data information, n'LIAnd n'LQRespectively represent the intermediate frequency left-hand signal SL(t) Co-directional branch signal I'LAnd quadrature shunt signal Q'LLow-pass filtered noise of thetaLRepresenting the intermediate frequency left-hand signal SL(t) initial phase.
Further, the cocurrent branch signal I 'in the step S22'RAnd quadrature shunt signal Q'RAre respectively:
I'R＝Acos((wR-w)t+φ+θR)+n'RI
Q'R＝Asin((w-wR)t-φ-θR)+n'RQ
where A denotes the amplitude of the signal, wRRepresenting the intermediate frequency right-hand signal SR(t) center frequency, θRRepresenting the intermediate frequency right-hand signal SR(t) initial phase, phi, represents modulated data information, n'RIAnd n'RQRespectively represent the intermediate frequency right-hand signals SR(t) Co-directional branch signal I'RAnd quadrature shunt signal Q'RLow-pass filtered noise of thetaRRepresenting the intermediate frequency right-hand signal SR(t) initial phase.
Further, the expressions of the equidirectional signal I and the orthogonal signal Q in step S23 are respectively:
I＝I'R·Q'L+Q'R·I'L＝A2sin((wR-wL)t+θR-θL)+nR
Q＝I'R·I'L+Q'R·Q'L＝A2cos((wR-wL)t+θR-θL)+nL
wherein A is2Representing the amplitude, w, of the co-directional signal I and the quadrature signal QRRepresenting the intermediate frequency right-hand signal SR(t) center frequency, wLRepresenting the intermediate frequency left-hand signal SL(t) center frequency, θRRepresenting the intermediate frequency right-hand signal SRInitial phase of (t), θLRepresenting the intermediate frequency left-hand signal SLInitial phase of (t), nRAnd nLRespectively representing intermediate frequency right-hand signals SR(t) and a medium frequency left hand signal SL(t) noise.
Further, the expression of the arctangent operation performed on the homodyne signal I and the quadrature signal Q in step S23 is as follows:
((wR-wL)t+θR-θL)＝Arctan(Q/I)
wherein, wRRepresenting the intermediate frequency right-hand signal SR(t) center frequency, wLRepresenting the intermediate frequency left-hand signal SL(t) center frequency, θRRepresenting the intermediate frequency right-hand signal SRInitial phase of (t), θLRepresenting the intermediate frequency left-hand signal SL(t) initial phase, t time, Arctan (Q/I) arctangent of the in-phase signal I and the quadrature signal Q, ((w)R-wL)t+θR-θL) And (4) containing the error component of the signal to obtain an arc tangent result.
Further, the step S3 includes the following steps:
s31, reserving a frequency offset signal in a differential mode loop output signal by utilizing the low-pass characteristic of the common mode loop second-order phase-locked loop, and inputting the frequency offset signal into a digital oscillator NCO as a phase error signal;
and S32, utilizing the digital oscillator NCO to track and lock the phase error signal to eliminate the frequency offset component, and inputting the processing result of the digital oscillator NCO into the mixer to realize closed loop.
The working principle of the invention is as follows:
receiving a left-handed signal and a right-handed signal from a radio frequency antenna, filtering out signals except zero intermediate frequency by a low-pass filter after orthogonal down-conversion, then performing cross-correlation operation on four signals, performing arc tangent on the calculated I, Q signal to obtain a phase difference of two paths, sending the obtained phase difference into a loop filter, sending the output of the filter to NCO of each channel in opposite polarity, enabling the phases of the two paths of signals to be close to the middle, realizing phase synchronization, and entering a common mode loop after the two paths of signals are subjected to same frequency and same phase of the differential mode loop and are added; the common mode loop reserves a slowly-changed frequency deviation signal in two paths of signals output by the differential mode loop by utilizing the low-pass characteristic of a second-order phase-locked loop, the slowly-changed frequency deviation signal is sent to a frequency mixer NCO as a phase error signal, and the frequency mixer NCO tracks the frequency of a locking error signal and sends the frequency deviation component to a closed loop of the frequency mixer after eliminating the frequency deviation component; and combining the processing results of the differential mode loop and the common mode loop to output at the maximum ratio.
The invention has the beneficial effects that:
(1) according to the invention, after frequency discrimination, various frequency deviation components are removed by utilizing the high-pass characteristic of the uniformly sampled second-order digital phase-locked loop error transfer function, the advantages of an SCA modeling tool platform are fully combined, and the invalid and heavy code re-development time is reduced.
(2) Compared with the traditional polarization diversity receiving method, the invention has simple control and easy realization, and can utilize the frequency of the received signal to the maximum extent in a complex and severe electromagnetic environment, reduce the data loss and reduce the influence of the change factor of the electric wave transmission characteristic.
(3) The invention can compress the signal level deception, improve the distribution rate of the signal amplitude, reduce the probability that the signal level declines to be below the set threshold value, and improve the signal-to-noise ratio, thereby improving the effectiveness and reliability of signal transmission and effectively removing the signal fast fading.
Drawings
Fig. 1 is a flowchart of a polarization diversity signal receiving method based on an FPGA in the embodiment of the present invention.
Fig. 2 is a schematic diagram of a polarization diversity signal receiving method based on an FPGA in the embodiment of the present invention.
Fig. 3 is a schematic diagram of the differential ring according to the embodiment of the present invention.
Fig. 4 is a schematic diagram of cross-correlation operation in an embodiment of the present invention.
Fig. 5 is an overall frame diagram of digital down-conversion and differential mode loop in the implementation process based on the System Generator model in the embodiment of the present invention.
Fig. 6 is a frame diagram of digital down conversion in the implementation process based on the System Generator model in the embodiment of the present invention.
FIG. 7 is a frame diagram of a differential mode ring in the implementation process based on the System Generator model in the embodiment of the present invention.
FIG. 8 is a waveform diagram of the System Generator based down-conversion simulation in the embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention is provided to facilitate the understanding of the present invention by those skilled in the art, but it should be understood that the present invention is not limited to the scope of the embodiments, and it will be apparent to those skilled in the art that various changes may be made without departing from the spirit and scope of the invention as defined and defined in the appended claims, and all matters produced by the invention using the inventive concept are protected.
Example 1
As shown in fig. 1, the present invention provides a polarization diversity signal receiving method based on FPGA, which includes the following steps:
s1, receiving an input signal by using an antenna and carrying out radio frequency processing on the input signal to obtain an intermediate frequency left-handed signal and an intermediate frequency right-handed signal;
s2, inputting the intermediate frequency left-handed signal and the intermediate frequency right-handed signal into a differential mode ring for phase synchronization processing to obtain an in-phase signal, and inputting the in-phase signal output by the differential mode ring into a common mode ring;
s3, eliminating frequency offset of the differential mode ring output signal by using the common mode ring to obtain a same-frequency same-phase signal;
and S4, combining and outputting two paths of signals with the same frequency and the same phase obtained by processing the output of the differential mode loop and the output of the common mode loop in the maximum ratio, and completing the polarization diversity signal receiving based on the FPGA.
As shown in fig. 2 and 3, the intermediate frequency left-hand signal S of step S1L(t) and a medium frequency right-hand signal SRThe expressions of (t) are as follows:
SL(t)＝Acos(wLt+φ+θL)+nL
SR(t)＝Acos(wRt+φ+θR)+nR
where A denotes the amplitude of the signal, wLAnd wRRespectively representing the intermediate frequency left-hand signal SL(t) and a medium frequency right-hand signal SR(t) center frequency, θLAnd thetaRRespectively representing the intermediate frequency left-hand signal SL(t) and a medium frequency right-hand signal SR(t) initial phase, phi denotes modulation data information, nLAnd nRRespectively representing the intermediate frequency left-hand signal SL(t) and a medium frequency right-hand signal SR(t) noise.
The intermediate frequency leftRotation signal SL(t) and a medium frequency right-hand signal SR(t) local signal diplex signal INAnd quadrature branch signal QNThe expressions are respectively as follows:
IN＝2cos(wt)
QN＝2sin(wt)
wherein w represents the local carrier frequency, t represents time, and the local signal is the same-direction branch signal INAnd quadrature branch signal QNIs 0.
The method for performing phase synchronization processing in step S2 includes the following steps:
s21, respectively carrying out orthogonal down-conversion on the intermediate frequency left-hand signal and the intermediate frequency right-hand signal to obtain a left-hand signal homodromous component ILQuadrature component Q of the left-hand signalLD-signal homodromous component IRAnd quadrature component Q of the right-hand signalR；
S22, filtering the homodromous component I of the left-handed signal by using a low-pass filterLQuadrature component Q of the left-hand signalLD-signal homodromous component IRAnd quadrature component Q of the right-hand signalRTo obtain a low-pass filtered signal I'L、Q'L、I'RAnd Q'R；
S23, mixing signal I'L、Q'L、I'RAnd Q'RPerforming cross-correlation operation to obtain an in-phase signal I and an orthogonal signal Q, and performing arc tangent operation on the in-phase signal I and the orthogonal signal Q to obtain a phase difference of the in-phase signal I and the orthogonal signal Q;
and S24, inputting the phase difference into a loop filter, and respectively inputting output signals of the filter into a corresponding first digital oscillator NCO and a corresponding second digital oscillator NCO in opposite polarities to realize phase synchronization of the intermediate-frequency left-hand signal and the intermediate-frequency right-hand signal and obtain an in-phase signal.
The homodromous branch signal I 'in the step S22'LAnd quadrature shunt signal Q'LAre respectively:
I'L＝Acos((wL-w)t+φ+θL)+n'LI
Q'L＝Asin((w-wL)t-φ-θL)+n'LQ
where A denotes the amplitude of the signal, wLRepresenting the intermediate frequency left-hand signal SL(t) center frequency, θLRepresenting the intermediate frequency left-hand signal SL(t) initial phase, phi, represents modulated data information, n'LIAnd n'LQRespectively represent the intermediate frequency left-hand signal SL(t) Co-directional branch signal I'LAnd quadrature shunt signal Q'LLow-pass filtered noise of thetaLRepresenting the intermediate frequency left-hand signal SL(t) initial phase.
The homodromous branch signal I 'in the step S22'RAnd quadrature shunt signal Q'RAre respectively:
I'R＝Acos((wR-w)t+φ+θR)+n'RI
Q'R＝Asin((w-wR)t-φ-θR)+n'RQ
where A denotes the amplitude of the signal, wRRepresenting the intermediate frequency right-hand signal SR(t) center frequency, θRRepresenting the intermediate frequency right-hand signal SR(t) initial phase, phi, represents modulated data information, n'RIAnd n'RQRespectively represent the intermediate frequency right-hand signals SR(t) Co-directional branch signal I'RAnd quadrature shunt signal Q'RLow-pass filtered noise of thetaRRepresenting the intermediate frequency right-hand signal SR(t) initial phase.
As shown in fig. 4, the expressions of the equidirectional signal I and the orthogonal signal Q in step S23 are respectively:
I＝I'R·Q'L+Q'R·I'L＝A2sin((wR-wL)t+θR-θL)+nR
Q＝I'R·I'L+Q'R·Q'L＝A2cos((wR-wL)t+θR-θL)+nL
wherein A is2Representing the amplitude, w, of the co-directional signal I and the quadrature signal QRRepresenting the intermediate frequency right-hand signal SR(t) center frequency, wLRepresenting the intermediate frequency left-hand signal SL(t) center frequency, θRRepresenting the intermediate frequency right-hand signal SRInitial phase of (t), θLRepresenting the intermediate frequency left-hand signal SLInitial phase of (t), nRAnd nLRespectively representing intermediate frequency right-hand signals SR(t) and a medium frequency left hand signal SL(t) noise.
The expression for performing the arc tangent operation on the homodyne signal I and the quadrature signal Q in step S23 is as follows:
((wR-wL)t+θR-θL)＝Arctan(Q/I)
wherein, wRRepresenting the intermediate frequency right-hand signal SR(t) center frequency, wLRepresenting the intermediate frequency left-hand signal SL(t) center frequency, θRRepresenting the intermediate frequency right-hand signal SRInitial phase of (t), θLRepresenting the intermediate frequency left-hand signal SL(t) initial phase, t time, Arctan (Q/I) arctangent of the in-phase signal I and the quadrature signal Q, ((w)R-wL)t+θR-θL) And (4) containing the error component of the signal to obtain an arc tangent result.
The step S3 includes the following steps:
s31, reserving a frequency offset signal in a differential mode loop output signal by utilizing the low-pass characteristic of the common mode loop second-order phase-locked loop, and inputting the frequency offset signal into a digital oscillator NCO as a phase error signal;
and S32, utilizing the digital oscillator NCO to track and lock the phase error signal to eliminate the frequency offset component, and inputting the processing result of the digital oscillator NCO into the mixer to realize closed loop.
As shown in fig. 5, in an embodiment of the present invention, the polarization diversity signal receiving method is realized by simulating an FPGA implementation method of digital down-conversion and differential-mode loop designed by System Generator modeling, and the simulation implementation process is as follows:
a data file containing left-handed signal information is input through a left-handed signal input interface left _ rx _ in, and the output end of the left-handed signal input interface left _ rx _ in is connected with an SI pin of the digital down-conversion module; a data file containing right-handed signal information is input through a left-handed signal input interface right _ rx _ in, and the output end of the right-handed signal input interface right _ rx _ in is connected with an SQ pin of the digital down-conversion module; pins SI _ I, SI _ Q, SQ _ I and SQ _ Q at the output end of the digital down-conversion module are respectively connected with pins SI _ I, SI _ Q, SQ _ I and SQ _ Q of the differential mode ring module in a one-to-one correspondence manner; the fcw _ I and fcw _ Q pins of the differential mode loop module are respectively connected with the fcw _ I and fcw _ Q pins of the digital down-conversion module in a one-to-one correspondence manner to form a mixer loop; and the pin out _ I of the differential mode ring outputs a combined equidirectional signal I, and the pin out _ Q of the differential mode ring outputs a combined orthogonal signal Q.
As shown in fig. 6, the left-handed signal is input to the digital down-conversion module through the SI pin, the mixer output is input to the digital down-conversion module from the fcw _ I pin and forms a carrier signal with the same frequency and phase as the left-handed signal through a digital frequency synthesizer (DDS), the left-handed signal and the carrier signal are multiplied by a multiplier Mult and then pass through a low-pass filter FIR to obtain a carrier-removed signal, and the carrier-removed signal is output through the SI _ I and SI _ Q interfaces respectively; because the phase difference between the left-handed signal and the right-handed signal is 180 degrees, the right-handed signal is inverted through an SQ pin and then input into the digital down-conversion module, the output of the mixer is input into the digital down-conversion module from an fcw _ Q pin and forms a carrier signal with the same frequency and phase as the right-handed signal through a digital frequency synthesizer (DDS), the right-handed signal and the carrier signal are multiplied through a multiplier Mult and then pass through a low-pass filter FIR to obtain a de-carrier signal, and the de-carrier signal is output through SQ _ I and SQ _ Q interfaces respectively.
As shown in fig. 7, the differential-mode loop module includes a differential-mode loop, a common-mode loop, and a module in which a differential-mode output and a common-mode output work together.
The output signals of the digital down-conversion module are respectively input to SI _ I, SI _ Q, SQ _ I and SQ _ Q pins in the differential mode loop module in a one-to-one correspondence mode and are subjected to cross-correlation operation, an operation result is obtained, a combined homodromous signal I is output from an out _ I pin and is output to a gain _ I pin of the common mode loop, an operation result is obtained, a combined orthogonal signal Q is output from an out _ Q pin and is output to a gain _ Q pin of the common mode loop, and a common mode loop processing result is output to a module with the combined action of differential mode output and common mode output; the output signals of the digital down-conversion module are respectively and correspondingly input into a register1, a register2 and a register3, the output ends of the register1, the register2 and the register3 are correspondingly connected with pins In1, In2, In3 and In4 of a differential mode loop, and the processing result of the differential mode loop is output to a module with the combined action of differential mode output and common mode output; the module with the combined action of the differential mode output and the common mode output processes output signals of a differential mode ring and the common mode ring, and then the output signals enter a slice unit and a slice1 unit respectively after performing cross-correlation operation with a common-frequency carrier, the slice unit and the slice1 unit are correspondingly connected with a register4 and a register5 one by one, and output results of the register4 and the register5 are output to a digital down-conversion module from an fcw _1 pin and an fcw _2 pin respectively to form a mixer circuit.
As shown in fig. 8, signals in the figure are a left-hand signal input from the left _ rx _ in interface, a right-hand signal input from the right _ rx _ in interface, and a baseband signal and a clock signal output from the SI _ I, SI _ Q, SQ _ I and SQ _ Q pins, which are obtained by performing mixer and low-pass filtering on the left-hand signal and the right-hand signal, respectively.
In the traditional polarization diversity receiving method, two paths of signals are combined together through the common action of a differential mode ring and a common mode ring, and the effect of removing Doppler frequency offset to enable the two paths of signals to reach the same frequency and the same direction is achieved. The control of the structure is relatively complex, and the requirement of an actual project is difficult to meet in practical application. On the basis of researching the key technology of traditional polarization diversity reception, the invention structurally improves the traditional method, removes frequency offset components by utilizing the high-pass characteristic of a uniformly sampled second-order phase-locked loop after the frequency discrimination of signals, and proves the effectiveness of the method by performing FPGA bottom layer logic simulation on the method based on a System Generator.

Claims (9)

1. A polarization diversity signal receiving method based on FPGA is characterized by comprising the following steps:
s1, receiving an input signal by using an antenna and carrying out radio frequency processing on the input signal to obtain an intermediate frequency left-handed signal and an intermediate frequency right-handed signal;
s2, inputting the intermediate frequency left-handed signal and the intermediate frequency right-handed signal into a differential mode ring for phase synchronization processing to obtain an in-phase signal, and inputting the in-phase signal output by the differential mode ring into a common mode ring;
s3, eliminating frequency offset of the differential mode ring output signal by using the common mode ring to obtain a same-frequency same-phase signal;
and S4, combining and outputting two paths of signals with the same frequency and the same phase obtained by processing the output of the differential mode loop and the output of the common mode loop in the maximum ratio, and completing the polarization diversity signal receiving based on the FPGA.
2. The FPGA-based polarization diversity signal receiving method according to claim 1, wherein said step S1 is implemented by using an intermediate frequency left-handed signal SL(t) and a medium frequency right-hand signal SRThe expressions of (t) are as follows:
SL(t)＝Acos(wLt+φ+θL)+nL
SR(t)＝Acos(wRt+φ+θR)+nR
where A denotes the amplitude of the signal, wLAnd wRRespectively representing the intermediate frequency left-hand signal SL(t) and a medium frequency right-hand signal SR(t) center frequency, θLAnd thetaRRespectively representing the intermediate frequency left-hand signal SL(t) and a medium frequency right-hand signal SR(t) initial phase, phi denotes modulation data information, nLAnd nRRespectively representing the intermediate frequency left-hand signal SL(t) and a medium frequency right-hand signal SR(t) noise.
3. The FPGA-based polarization diversity signal receiving method of claim 2, wherein the intermediate frequency left-handed signal SL(t) and a medium frequency right-hand signal SR(t) local signal diplex signal INAnd quadrature branch signal QNThe expressions are respectively as follows:
IN＝2cos(wt)
QN＝2sin(wt)
wherein w represents the local carrier frequency, t represents time, and the local signal is the same-direction branch signal INAnd quadrature branch signal QNIs 0.
4. The FPGA-based polarization diversity signal receiving method according to claim 1, wherein the method for performing the phase synchronization process in step S2 comprises the steps of:
s21, respectively carrying out orthogonal down-conversion on the intermediate frequency left-hand signal and the intermediate frequency right-hand signal to obtain a left-hand signal homodromous component ILQuadrature component Q of the left-hand signalLD-signal homodromous component IRAnd quadrature component Q of the right-hand signalR；
S22, filtering the homodromous component I of the left-handed signal by using a low-pass filterLQuadrature component Q of the left-hand signalLD-signal homodromous component IRAnd quadrature component Q of the right-hand signalRTo obtain a low-pass filtered signal I'L、Q'L、I'RAnd Q'R；
S23, mixing signal I'L、Q'L、I'RAnd Q'RPerforming cross-correlation operation to obtain an in-phase signal I and an orthogonal signal Q, and performing arc tangent operation on the in-phase signal I and the orthogonal signal Q to obtain a phase difference of the in-phase signal I and the orthogonal signal Q;
and S24, inputting the phase difference into a loop filter, and respectively inputting output signals of the filter into a corresponding first digital oscillator NCO and a corresponding second digital oscillator NCO in opposite polarities to realize phase synchronization of the intermediate-frequency left-hand signal and the intermediate-frequency right-hand signal and obtain an in-phase signal.
5. The FPGA-based polarization diversity signal receiving method according to claim 4, wherein the homodromous branch signal I 'in the step S22'LAnd quadrature shunt signal Q'LIs divided intoRespectively, the following steps:
I'L＝Acos((wL-w)t+φ+θL)+n'LI
Q'L＝Asin((w-wL)t-φ-θL)+n'LQ
where A denotes the amplitude of the signal, wLRepresenting the intermediate frequency left-hand signal SL(t) center frequency, θLRepresenting the intermediate frequency left-hand signal SL(t) initial phase, phi, represents modulated data information, n'LIAnd n'LQRespectively represent the intermediate frequency left-hand signal SL(t) Co-directional branch signal I'LAnd quadrature shunt signal Q'LLow-pass filtered noise of thetaLRepresenting the intermediate frequency left-hand signal SL(t) initial phase.
6. The FPGA-based polarization diversity signal receiving method according to claim 4, wherein the homodromous branch signal I 'in the step S22'RAnd quadrature shunt signal Q'RAre respectively:
I'R＝Acos((wR-w)t+φ+θR)+n'RI
Q'R＝Asin((w-wR)t-φ-θR)+n'RQ
where A denotes the amplitude of the signal, wRRepresenting the intermediate frequency right-hand signal SR(t) center frequency, θRRepresenting the intermediate frequency right-hand signal SR(t) initial phase, phi, represents modulated data information, n'RIAnd n'RQRespectively represent the intermediate frequency right-hand signals SR(t) Co-directional branch signal I'RAnd quadrature shunt signal Q'RLow-pass filtered noise of thetaRRepresenting the intermediate frequency right-hand signal SR(t) initial phase.
7. The FPGA-based polarization diversity signal receiving method according to claim 4, wherein the expressions of the in-phase signal I and the quadrature signal Q in step S23 are respectively:
I＝I'R·Q'L+Q'R·I'L＝A2 sin((wR-wL)t+θR-θL)+nR
Q＝I'R·I'L+Q'R·Q'L＝A2cos((wR-wL)t+θR-θL)+nL
wherein A is2Representing the amplitude, w, of the co-directional signal I and the quadrature signal QRRepresenting a right-hand signal SR(t) center frequency, wLRepresenting the intermediate frequency left-hand signal SL(t) center frequency, θRRepresenting the intermediate frequency right-hand signal SRInitial phase of (t), θLRepresenting the intermediate frequency left-hand signal SLInitial phase of (t), nRAnd nLRespectively representing intermediate frequency right-hand signals SR(t) and a medium frequency left hand signal SL(t) noise.
8. The FPGA-based polarization diversity signal receiving method according to claim 4, wherein the expression of the arctangent operation performed on the homodyne signal I and the quadrature signal Q in step S23 is as follows:
((wR-wL)t+θR-θL)＝Arctan(Q/I)
wherein, wRRepresenting the intermediate frequency right-hand signal SR(t) center frequency, wLRepresenting the intermediate frequency left-hand signal SL(t) center frequency, θRRepresenting the intermediate frequency right-hand signal SRInitial phase of (t), θLRepresenting the intermediate frequency left-hand signal SL(t) initial phase, t time, Arctan (Q/I) arctangent of the in-phase signal I and the quadrature signal Q, ((w)R-wL)t+θR-θL) And (4) containing the error component of the signal to obtain an arc tangent result.
9. The FPGA-based polarization diversity signal receiving method according to claim 1, wherein said step S3 comprises the steps of:
s31, reserving a frequency offset signal in a differential mode loop output signal by utilizing the low-pass characteristic of the common mode loop second-order phase-locked loop, and inputting the frequency offset signal into a digital oscillator NCO as a phase error signal;
and S32, utilizing the digital oscillator NCO to track and lock the phase error signal to eliminate the frequency offset component, and inputting the processing result of the digital oscillator NCO into the mixer to realize closed loop.
CN202110644388.9A 2021-06-09 2021-06-09 Polarization diversity signal receiving method based on FPGA Pending CN113381778A (en)

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