CN113381745A

CN113381745A - Power supply delay circuit and hot plug device

Info

Publication number: CN113381745A
Application number: CN202110708878.0A
Authority: CN
Inventors: 张荥; 李绍健; 罗岚; 杨昆; 宋宪磊; 王浩良
Original assignee: Gree Electric Appliances Inc of Zhuhai
Current assignee: Gree Electric Appliances Inc of Zhuhai
Priority date: 2021-06-25
Filing date: 2021-06-25
Publication date: 2021-09-10

Abstract

The application relates to a power supply delay circuit and a hot plug device, wherein the power supply delay circuit comprises a delay circuit, a first connecting end and a second connecting end, the delay circuit is connected with the first connecting end and the second connecting end, the first connecting end is used for connecting a power supply, and the second connecting end is used for connecting the power supply or a grounding end; the delay circuit is used for conducting delay on the power supplies so that the two power supplies are not conducted at the same time or the power supplies are conducted earlier than the grounding end, mutual interference between the power supplies is avoided, and use reliability is improved.

Description

Power supply delay circuit and hot plug device

Technical Field

The present application relates to the field of electronic circuit technology, and more particularly, to a power delay circuit and a hot plug device.

Background

With the development of science and technology and the continuous progress of society, more and more kinds of electronic devices appear in people's daily work and life, and the required power supply amplitude often will be different between different parts in the electronic device, and between different electronic devices.

The multi-power supply circuit can provide power supplies with different amplitudes, and the power supply requirements of different loads are met. However, in the multi-power circuit, the hot plug may cause mutual interference between power supplies, and there is a disadvantage that the reliability of use is low.

Disclosure of Invention

Therefore, it is necessary to provide a power delay circuit and a hot plug device to effectively improve the reliability of use, aiming at the problem that the hot plug causes mutual interference between power supplies and has low reliability of use.

A power supply delay circuit comprises a delay circuit, a first connecting end and a second connecting end, wherein the delay circuit is connected with the first connecting end and the second connecting end, the first connecting end is used for connecting a power supply, and the second connecting end is used for connecting a power supply or a grounding end; the delay circuit is used for conducting delay on the power supplies so as to enable the two power supplies to be conducted at different times or enable the power supplies to be conducted earlier than the grounding end.

In one embodiment, the delay circuit includes a switching tube, a first resistor assembly, a second resistor assembly and a capacitor assembly, a first end of the switching tube is connected to the first connection end, a second end of the switching tube is connected to the second connection end through a power load, a control end of the switching tube is connected to one end of the first resistor assembly and one end of the second resistor assembly, the other end of the first resistor assembly is connected to the first end of the switching tube, the other end of the second resistor assembly is connected to the second connection end, and the capacitor assembly is connected to the second resistor assembly in parallel.

In one embodiment, the switching tube is a MOS tube.

In one embodiment, the switch tube is a triode.

A hot plug device comprises a daughter board, wherein the daughter board comprises a power supply load and the power supply delay circuit.

In one embodiment, the hot plug device further comprises a motherboard and an inter-board connecting wire, and the motherboard is connected with the daughter board through the inter-board connecting wire.

In one embodiment, the inter-board connecting line includes a daughter board line, a daughter terminal, a mother terminal, and a mother board line, the daughter terminal is connected to the daughter board through the daughter board line, and the mother terminal is matched with the daughter terminal and connected to the mother board through the mother board line.

In one embodiment, the motherboard is provided with a power supply and a grounding terminal, and the power supply and the grounding terminal are connected with the daughter board through the inter-board connecting line.

In one embodiment, the number of the power sources is more than two.

In one embodiment, the output voltages of the power supplies are different from each other.

The power supply delay circuit and the hot plug device are provided with the delay circuit between the power supply and the power supply or between the power supply and the grounding terminal, so that the two power supplies are not conducted at the same time, or the power supply is conducted earlier than the grounding terminal, mutual interference between the power supplies is avoided, and the use reliability is improved.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments or the conventional technologies of the present application, the drawings used in the descriptions of the embodiments or the conventional technologies will be briefly introduced below, it is obvious that the drawings in the following descriptions are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a schematic diagram of an embodiment of a power delay circuit;

FIG. 2 is a diagram illustrating an embodiment of a power delay circuit;

FIG. 3 is a schematic diagram illustrating a hot swap apparatus according to an embodiment;

FIG. 4 is a schematic diagram of a hot plug device according to an embodiment.

Description of reference numerals: 110-a delay circuit; a V1-24V DC power supply; V2-5V DC power supply; a GND-ground network; r4-motherboard 5V power supply load; c3-filtering capacitor at 5V power supply output end of motherboard; r3-filtering resistor of 5V power supply transmitting end of motherboard; k1-power connector for mother board and daughter board 24V; k2-a 5V power supply connector for the motherboard and the daughter board; k3-a connector for connecting the motherboard with the daughter board GND; d1-daughter board chip internal parasitic body diode; c4-daughter board 5V power supply entrance end filter capacitor; r5-daughter board 24V power supply entrance end filter resistor; c2-daughter board 24V power supply entrance end filter capacitor; MOS-MOS tube; r1-resistance; r2-same resistance as R1; c1 is a-patch capacitor.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

It will be understood that spatial relationship terms, such as "under", "below", "beneath", "below", "over", "above", and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.

It will be understood that when an element is referred to as being "connected" to another element, it can be directly connected to the other element or be connected to the other element through intervening elements. The "connection" in the following embodiments is understood as "electrical connection", "communication connection", or the like if the connected circuits, modules, units, or the like have electrical signals or data transmission therebetween.

As used herein, the singular forms "a", "an" and "the" may include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises/comprising," "includes" or "including," etc., specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, the terminology used in this specification includes any and all combinations of the associated listed items.

In one embodiment, a power delay circuit is provided, which can be applied to a sensitive circuit to guarantee the conducting sequence of power supply during hot plug. As shown in fig. 1, the power delay circuit includes a delay circuit 110, a first connection end and a second connection end, the delay circuit 110 is connected to the first connection end and the second connection end, the first connection end is used for connecting a power supply, and the second connection end is used for connecting a power supply or a ground end; the delay circuit 110 is used to delay the power supplies to be turned on, so that the two power supplies are not turned on at the same time, or the power supplies are turned on earlier than the ground. It can be understood that, when the first connection end and the second connection end are both connected to the power supply, the first connection end and the second connection end are respectively connected to different power supplies.

Specifically, the delay circuit 110 may be disposed on a power load side, where the power load is connected to the power side through a hot plug interface, and the hot plug interface includes a power interface and a ground interface. According to actual requirements, a first connecting end of the power supply delay circuit is connected with a power supply interface, and a second interface of the power supply delay circuit is connected with a grounding interface or another power supply interface. In the hot plug process, the delay circuit 110 delays the conduction of the power supplies to avoid the simultaneous conduction of the two power supplies or make the power supplies conducted earlier than the grounding end, thereby preventing the mutual interference among multiple power supplies, ensuring the conduction sequence of the power supplies during the hot plug, and protecting the circuit. When the two power supplies are prevented from being turned on at the same time, the delay circuit 110 may delay one of the power supplies, for example, perform turn-on delay control on the power supply with high output voltage; the delay circuit 110 may also delay both power supplies, and prevent the two power supplies from being turned on simultaneously by controlling the delay time to be different.

In addition, the number of the delay circuits 110 and the number of the first and second connection terminals may be different according to the number of the power supplies. As shown in fig. 2, the delay circuit 110 may be located between the ground GND and the power supply, or between two power supplies. The preferred turn-on sequence is that the ground GND is turned on before the power supply 3, the power supply 3 is turned on before the power supply 2, and the power supply 2 is turned on before the power supply 1. The delay circuits 110 may be disposed between the power source 1, the power source 2, the power source 3 and the ground GND, and each delay circuit 110 is connected to the power source or the ground GND through the corresponding first connection end and the second connection end. Specifically, in a system with 3 power supplies and the ground, the delay circuit 110 is located between the power supplies, and ensures that after the ground terminal GND is connected, the power supply 3 is connected after a period of delay time, the power supply 2 is connected after the power supply 3, and the power supply 1 is connected after the power supply 2, so that interference among the power supplies is effectively avoided, and the power supply connection sequence can be controlled.

It should be noted that the conduction sequence between each power supply and the ground GND is not fixed, and the conduction sequence can be selected by itself according to different circuit path conditions, for example, a delay circuit is added to the path between the power supply 3 and the power supply 2 before the power supply 2 is turned on, so as to ensure that the power supply 3 is turned on again after the power supply 2 is turned on in advance. Or, the ground terminal GND needs to be turned on before the power supply 1, and the delay circuit is added to the path between the power supply 1 and the ground terminal GND to ensure that the power supply 1 is turned on again after the ground terminal GND is turned on.

It is understood that the specific structure of the delay circuit 110 is not exclusive, and in one embodiment, as shown in fig. 1, the delay circuit 110 includes a switch tube, a first resistor component, a second resistor component and a capacitor component, a first end of the switch tube is connected to the first connection end, a second end of the switch tube is connected to the second connection end through a power load, a control end of the switch tube is connected to one end of the first resistor component and one end of the second resistor component, another end of the first resistor component is connected to the first end of the switch tube, another end of the second resistor component is connected to the second connection end, and the capacitor component is connected to the second resistor component in parallel. Specifically, the switching tube may be a selective MOS tube or a triode, in this embodiment, the switching tube is an N-channel MOS tube, the gate is used as the control end, the drain is used as the first end, and the source is used as the second end. The first resistance component and the second resistance component can adopt a single resistance, and can also adopt a plurality of resistances to carry out series connection, parallel connection or series-parallel connection. In this embodiment, the first resistor element is a resistor R1, and the second resistor element is a resistor R2. The capacitor assembly plays a charging delay role, and the switch tube is switched on after the capacitor is charged to reach a switching-on voltage. The capacitor assembly can adopt a single capacitor, and can also adopt a plurality of capacitors connected in series or in parallel. In this embodiment, the capacitor assembly is a chip capacitor C1, and the chip capacitor C1 is connected in parallel with the resistor R2.

The delay circuit 110 is arranged between the power supply and the power supply or between the power supply and the grounding terminal, so that the two power supplies are not conducted at the same time or the power supplies are conducted earlier than the grounding terminal, mutual interference between the power supplies is avoided, and the use reliability is improved.

In one embodiment, a hot plug device is further provided, which comprises a daughter board, wherein the daughter board comprises a power supply load and the power supply delay circuit. The power load and the power delay circuit form a control loop which is connected with the power supply and the grounding terminal of the motherboard in a pluggable way. Specifically, the power supply delay circuit includes a delay circuit 110, a first connection end and a second connection end, the delay circuit 110 is connected to the first connection end and the second connection end, the first connection end is used for connecting a power supply, and the second connection end is used for connecting a power supply or a ground end; the delay circuit 110 is used to delay the power supplies to be turned on, so that the two power supplies are not turned on at the same time, or the power supplies are turned on earlier than the ground. The delay circuit 110 is disposed on a power load side, and the power load is connected to the power load side through a hot plug interface, where the hot plug interface includes a power interface and a ground interface. According to actual requirements, a first connecting end of the power supply delay circuit is connected with a power supply interface, and a second interface of the power supply delay circuit is connected with a grounding interface or another power supply interface. In the hot plug process, the delay circuit 110 delays the conduction of the power supplies to avoid the simultaneous conduction of the two power supplies or make the power supplies conducted earlier than the grounding end, thereby preventing the mutual interference among multiple power supplies, ensuring the conduction sequence of the power supplies during the hot plug, and protecting the circuit. When the two power supplies are prevented from being turned on at the same time, the delay circuit 110 may delay one of the power supplies, for example, perform turn-on delay control on the power supply with high output voltage; the delay circuit 110 may also delay both power supplies, and prevent the two power supplies from being turned on simultaneously by controlling the delay time to be different.

As shown in fig. 1, the delay circuit 110 includes a switch tube, a first resistor assembly, a second resistor assembly and a capacitor assembly, wherein a first end of the switch tube is connected to the first connection end, a second end of the switch tube is connected to the second connection end through a power load, a control end of the switch tube is connected to one end of the first resistor assembly and one end of the second resistor assembly, the other end of the first resistor assembly is connected to the first end of the switch tube, the other end of the second resistor assembly is connected to the second connection end, and the capacitor assembly is connected to the second resistor assembly in parallel. The switch tube is an N-channel MOS tube, the first resistance element is a resistor R1, and the second resistance element is a resistor R2. The capacitor assembly plays a charging delay role, and the switch tube is switched on after the capacitor is charged to reach a switching-on voltage. Specifically, the capacitor assembly is a chip capacitor C1, and the chip capacitor C1 is connected in parallel with a resistor R2.

Further, as shown in fig. 2, the delay circuit 110 may be located between the ground GND and the power supply, or between two power supplies. The preferred turn-on sequence is that the ground GND is turned on before the power supply 3, the power supply 3 is turned on before the power supply 2, and the power supply 2 is turned on before the power supply 1. The delay circuits 110 can be arranged among the power supplies 1, the power supplies 2, the power supplies 3 and the ground end GND, in a system of 3 power supplies and the ground, the delay circuits 110 are positioned among the power supplies, the power supplies 3 are conducted after a period of delay time after the ground end GND is conducted, the power supplies 2 are conducted after the power supplies 3, the power supplies 1 are conducted after the power supplies 2, interference among a plurality of power supplies is effectively avoided, and the conduction sequence of the power supplies can be controlled.

In one embodiment, as shown in fig. 3, the hot plug device further includes a motherboard and an inter-board connection line, and the motherboard is connected to the daughter board through the inter-board connection line. The inter-board connecting line comprises a daughter board line W2, a daughter end, a mother end and a mother board line W1, wherein the daughter end is connected with the daughter board through the daughter board line W2, and the mother end is matched with the daughter end and is connected with the mother board through the mother board line W1. Furthermore, the motherboard is provided with a power supply and a grounding terminal, and the power supply and the grounding terminal are connected with the daughter board through an inter-board connecting wire.

Only one power supply or a plurality of power supplies can be arranged on the motherboard, and a corresponding number of delay circuits 110 are arranged on the daughter board according to actual requirements and are used for delaying the power supply conduction. In one embodiment, the number of the power supplies is more than two, and power can be supplied through the power loads of the plurality of power supply daughter boards on the mother board. The output voltages of the power supplies may be the same, different, or partially the same. In this embodiment, the output voltages of the power supplies are different from each other. The power supplies with different output voltages are arranged so as to meet different power supply requirements of the power supply loads.

Specifically, the female terminal and the sub terminal support a hot plug function, a power supply and a grounding terminal are arranged on the mother board, and after the female terminal and the sub terminal are connected, a power supply load on the daughter board forms a passage with the power supply and the grounding terminal on the mother board through an inter-board connecting line. The interfaces between the female and the male terminals may vary depending on the number and type of power supplies on the motherboard. Taking the case that the power supply on the motherboard includes a +24V power supply and a +5V power supply, the female terminal and the male terminal are provided with a +24V interface, a +5V interface and a GND interface.

The hot plug device is provided with the delay circuit 110 between the power supply and the power supply or between the power supply and the grounding terminal, so that the two power supplies are not conducted at the same time, or the power supplies are conducted earlier than the grounding terminal, mutual interference between the power supplies is avoided, and the use reliability is improved.

In order to better understand the power delay circuit and the hot plug device, the following detailed description is provided with reference to specific embodiments.

In a multi-power circuit, hot plugging can cause mutual interference among power supplies, and the delay circuit provided by the application can solve the problem, has a delay effect on the conduction of the power supplies by using fewer devices, can be applied to a sensitive circuit, and ensures the conduction sequence of the power supplies during hot plugging, thereby playing a role in protecting the circuit.

Description of the system principle: the delay circuit is used in a multi-power circuit, as shown in fig. 2, a system of 3 power supplies and the ground is enumerated, the delay circuit is positioned between the power supplies, the power supply 3 is conducted after a period of delay time after the grounding end GND is conducted, the power supply 2 is conducted after the power supply 3, the power supply 1 is conducted after the power supply 2, interference among the power supplies is effectively avoided, and the conduction sequence of the power supplies can be controlled.

The delay circuit can be located between the ground GND and the power supply, or between two power supplies. The preferred turn-on sequence is that the ground GND is turned on before the power supply 3, the power supply 3 is turned on before the power supply 2, and the power supply 2 is turned on before the power supply 1. The conduction sequence is automatically selected according to different circuit path conditions, for example, a time delay circuit is added on the paths of the power supply 3 and the power supply 2 when the power supply 2 is required to be conducted before the power supply 3, and the power supply 3 is ensured to be conducted again after the power supply 2 is conducted in a leading mode. Or, the ground terminal GND needs to be turned on before the power supply 1, and the delay circuit is added to the path between the power supply 1 and the ground terminal GND to ensure that the power supply 1 is turned on again after the ground terminal GND is turned on.

As shown in fig. 1, the delay circuit 110 includes an MOS transistor, two resistors, and a capacitor, where the MOS transistor is a common N-channel MOS transistor and is used as a switch and is turned on when a start voltage is reached; r1 and R2 are the same resistor, and voltage is divided at the resistor, so that the voltage is guaranteed to reach the starting voltage of the MOS tube; the capacitor C1 plays a role in charge delay, and when the capacitor charge voltage reaches the MOS tube starting voltage, the MOS tube is conducted. It is understood that in other embodiments, the MOS transistor may be replaced by one or two transistors, and the function of the delay circuit 110 can also be realized.

The system is described in detail below by referring to a control loop of a 24V dc power supply, a 5V dc power supply and a ground terminal GND in a sensitive circuit:

as shown in fig. 4, the whole system is divided into a daughter board, a mother board, and an inter-board connection line, the mother board provides a 24V/5V power supply and a ground, the daughter board is connected through the inter-board connection line, the delay circuit 110 is located in the daughter board, and when the mother board power supply 24V is connected to the daughter board, the delay circuit 110 is needed.

Specifically, the motherboard portion: v1 is the 24V DC power supply that the daughter board was provided to the mother board, V2 is the 5V DC power supply that is provided to the daughter board by the mother board, GND provides ground network for the circuit, R4 is mother board 5V power load, C3 is mother board 5V power transmission end filter capacitance, R3 is mother board 5V power transmission end filter resistance.

Connecting the plates: k1 is here equally a female and a male terminal 24V connection in the inter-board connection, K2 is here equally a female and a male terminal 5V connection in the inter-board connection, and K3 is here equally a female and a male terminal GND connection in the inter-board connection.

A daughter board: d1 is a daughter board chip internal parasitic body diode that conducts when the 24V power supply is turned on. C4 is a filter capacitor at the inlet end of a daughter board 5V power supply, R5 is a filter resistor at the inlet end of a daughter board 24V power supply, and C2 is a filter capacitor at the inlet end of a daughter board 24V power supply.

The delay circuit 110: the MOS is an MOS tube and a voltage-controlled device, and the MOS tube is conducted when the voltage reaches a starting voltage to play a role of switching. R1 is a common resistor to make the MOS tube reach the turn-on voltage, R2 is a resistor the same as R1 to make the MOS tube reach the turn-on voltage, C1 is a common patch capacitor to play a role of charging delay, and the capacitor is charged to reach the MOS turn-on voltage.

The circuit operation principle is as follows: the delay circuit 110 is added to a port of the daughter board, when the 24V power supply reaches the daughter board through a terminal, the 24V power supply firstly passes through the delay circuit 110, the delay circuit 110 comprises an MOS (metal oxide semiconductor) transistor, two resistors R1 and R2 with the same resistance value and a capacitor C1, when the 24V power supply passes through the MOS transistor, the 24V power supply is conducted after the capacitor C1 charging time, the delay time is t, and the time t required by the selected MOS transistor to reach the starting voltage is calculated according to the following capacitor charging formula.

Wherein, U is the charging voltage at two ends of the capacitor C1, U₀The voltage of the power supply is 24V, e is a constant e, R is the parallel resistance of a resistor R1 and a resistor R2, C is the capacitance of a capacitor C1, and t is the charging time t. The time t is larger than the difference of the conduction time of K1, K2 and K3 during hot plug (proved by experiments, the conduction time of K1, K2 and K3 is less than 40 ms).

When the delay circuit 110 is not used, the hot plug causes sequential problems of the conduction time of the K1, the K2 and the K3, if the 24V power supply is conducted before the 5V power supply and the 5V power supply is conducted before the ground GND (after the K1 is closed, the K2 is closed and the K3 is closed finally), the current path of the 24V power supply is V1 → K1 → R5 → D1 → K2 → R3 → GND, and at this time, the diode D1 is subjected to high voltage impact instantaneously and is damaged.

In this example, the delay circuit 110 is added, so that the ground and the 5V power supply can be guaranteed to be conducted before the 24V power supply (the K2 and the K3 are closed first, and the 24V power supply is conducted again), and under this condition, the high-voltage 24V power supply cannot pass through the diode D1 anyway. The following analysis shows different ground conduction sequences during hot plug:

at the moment of connection, if the ground terminal GND is not turned on and the 24V power supply is turned on before the 5V power supply (K1, K2 are closed, and K3 is opened), after the current passes through the MOS transistor for a time delay t (the on time of the MOS transistor is equal to the charging time of the capacitor C1), the hot plug operation is completed during the time t, the ground terminal GND is turned on (K3 is closed) or the 5V power supply is turned on (K2 is closed), and the 24V power supply high voltage does not affect the circuit.

The power supply delay circuit has a delay function on power supply conduction, prevents mutual interference among multiple power supplies, can be widely applied to the multiple power supply circuit, and protects the power supply and sensitive circuits under the condition of low cost. The power supply delay circuit solves the problem of influence of live-line plugging on a power supply and also solves the problem of influence of live-line plugging on a sensitive circuit.

In the description herein, references to the description of "some embodiments," "other embodiments," "desired embodiments," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, a schematic description of the above terminology may not necessarily refer to the same embodiment or example.

The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims

1. A power supply delay circuit is characterized by comprising a delay circuit, a first connecting end and a second connecting end, wherein the delay circuit is connected with the first connecting end and the second connecting end, the first connecting end is used for connecting a power supply, and the second connecting end is used for connecting a power supply or a grounding end; the delay circuit is used for conducting delay on the power supplies so as to enable the two power supplies to be conducted at different times or enable the power supplies to be conducted earlier than the grounding end.

2. The power delay circuit according to claim 1, wherein the delay circuit comprises a switching tube, a first resistor assembly, a second resistor assembly and a capacitor assembly, a first end of the switching tube is connected to the first connection end, a second end of the switching tube is connected to the second connection end through a power load, a control end of the switching tube is connected to one end of the first resistor assembly and one end of the second resistor assembly, the other end of the first resistor assembly is connected to the first end of the switching tube, the other end of the second resistor assembly is connected to the second connection end, and the capacitor assembly is connected to the second resistor assembly in parallel.

3. The power delay circuit of claim 2, wherein the switching transistor is a MOS transistor.

4. The power delay circuit of claim 2, wherein the switching transistor is a triode.

5. A hot swap apparatus comprising a daughter board, the daughter board comprising a power load and the power delay circuit of any of claims 1-4.

6. The hot plug device according to claim 5, further comprising a motherboard and an inter-board connection line, wherein the motherboard is connected to the daughter board via the inter-board connection line.

7. The hot plug device according to claim 6, wherein the inter-board connection lines comprise daughter board lines, daughter terminals, mother terminals and mother board lines, the daughter terminals are connected to the daughter boards through the daughter board lines, and the mother terminals are matched with the daughter terminals and connected to the mother boards through the mother board lines.

8. The hot-plug device according to claim 6, wherein the motherboard is provided with a power supply and a ground terminal, and the power supply and the ground terminal are connected with the daughter board through the inter-board connection wires.

9. The hot-plug device according to claim 8, wherein the number of the power sources is two or more.

10. A hot plug device according to claim 9, wherein the output voltages of the power supplies are different from each other.