CN113345916A - Display panel and preparation method thereof - Google Patents
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- CN113345916A CN113345916A CN202110547924.3A CN202110547924A CN113345916A CN 113345916 A CN113345916 A CN 113345916A CN 202110547924 A CN202110547924 A CN 202110547924A CN 113345916 A CN113345916 A CN 113345916A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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Abstract
The embodiment of the application provides a display panel and a preparation method thereof. The display panel comprises a plurality of light emitting units and a plurality of driving units, each driving unit is electrically connected with one light emitting unit, each driving unit comprises at least three thin film transistors, and orthographic projections of two thin film transistors in at least one driving unit on a plane where the light emitting units are located are at least partially overlapped. Through setting up two thin film transistors in the drive unit to the structure of partial coincidence, can be so that the occupation space of a plurality of thin film transistors reduces to reduce drive unit's occupation space, correspondingly, the number of drive unit in the unit area increases, and the size setting that the luminescence unit corresponds drive unit, consequently can improve display panel's resolution ratio.
Description
Technical Field
The application belongs to the technical field of display devices, and particularly relates to a display panel and a preparation method thereof.
Background
With the development of display technology, Thin Film Transistors (TFTs) are widely used in display panels. The display panel includes a plurality of light emitting units and a plurality of driving units for driving the light emitting units, the driving units correspond to the pixels one to one, and each driving unit generally includes a plurality of thin film transistors.
However, in the related art display panel design, the occupation space of the plurality of thin film transistors in the driving unit is large.
Disclosure of Invention
The embodiment of the application provides a display panel and a preparation method thereof, so as to reduce the occupied space of a plurality of thin film transistors in a driving unit.
In a first aspect, an embodiment of the present application provides a display panel, including:
a plurality of light emitting units;
each driving unit is electrically connected with one light emitting unit and comprises at least three thin film transistors, and orthographic projections of two thin film transistors in at least one driving unit on a plane where the light emitting units are located are at least partially overlapped.
Optionally, the driving unit includes:
the driving thin film transistor is used for driving the light emitting unit to work;
the switch thin film transistor is used for controlling the drive thin film transistor to be switched on or switched off, and the switch thin film transistor and the drive thin film transistor are arranged at intervals; and
and the compensation thin film transistor is used for compensating the driving thin film transistor to drive the light-emitting unit to work, and the compensation thin film transistor and the switch thin film transistor are nested.
Optionally, the switching thin film transistor includes a first gate, and the compensation thin film transistor and the switching thin film transistor share the first gate.
Optionally, the display panel further includes a substrate, and the switching thin film transistor includes:
a first active portion disposed on the substrate;
a first insulating portion provided to the first active portion;
the first grid is arranged on the first insulating part;
a second insulating portion disposed on the first gate and covering the first active portion, the first insulating portion, and the first gate; and
the first source electrode and the first drain electrode are arranged on one side, away from the first grid electrode, of the second insulating part, and the first source electrode and the first drain electrode are electrically connected with the first active part respectively;
the compensation thin film transistor includes:
a second active portion disposed between the second insulating portion and the first source electrode;
a third insulating portion disposed on the second active portion and covering the second active portion; and
and the second source electrode and the second drain electrode are arranged on one side of the third insulating part, which is deviated from the first grid electrode, and are positioned on the same layer as the first source electrode, and the second source electrode and the second drain electrode are respectively and electrically connected with the second active part.
Optionally, a length direction of the first active portion is perpendicular to a length direction of the second active portion.
Optionally, the driving thin film transistor is disposed on the substrate, and the display panel further includes:
a light shielding portion disposed on the substrate and disposed opposite to the driving thin film transistor, the driving thin film transistor being electrically connected to the light shielding portion;
and a buffer part arranged between the light shielding part and the driving thin film transistor.
Optionally, the driving unit includes:
the driving thin film transistor is used for driving the light emitting unit to work;
the driving thin film transistor is used for driving the driving thin film transistor to be in a state of being connected with the driving thin film transistor;
or the drive unit includes:
the driving thin film transistor is used for driving the light emitting unit to work;
the compensation thin film transistor and the driving thin film transistor are arranged at intervals, and the two compensation thin film transistors are arranged in a nested manner.
In a second aspect, an embodiment of the present application further provides a method for manufacturing a display panel, including:
providing a substrate;
preparing a plurality of thin film transistors on the substrate, dividing the thin film transistors into a plurality of driving units, wherein each driving unit comprises at least three thin film transistors, and orthographic projections of two thin film transistors in at least one driving unit on a plane where the light-emitting units are located are at least partially overlapped;
and forming a light-emitting unit corresponding to each driving unit, and electrically connecting the light-emitting unit with the driving units.
Optionally, the preparing a plurality of thin film transistors on the substrate includes:
manufacturing a driving thin film transistor, wherein the driving thin film transistor is used for driving the light-emitting unit to work;
manufacturing a switch thin film transistor, wherein the switch thin film transistor and the driving thin film transistor are arranged at intervals, and the switch thin film transistor is used for controlling the driving thin film transistor to be switched on or switched off;
and manufacturing a compensation thin film transistor, wherein the compensation thin film transistor is nested with the switch thin film transistor, and the compensation thin film transistor is used for compensating the driving thin film transistor to drive the light-emitting unit to work.
Optionally, the nesting arrangement of the compensation thin film transistor and the switch thin film transistor includes:
forming a first active portion on the substrate;
forming a first insulating portion and a first gate electrode on the first active portion, respectively, the first insulating portion being located between the first active portion and the first gate electrode;
forming a second insulating portion on the first gate electrode, the second insulating portion covering the first active portion, the first insulating portion, and the first gate electrode;
forming a second active portion on the second insulating portion;
forming a third insulating portion on the second active portion and covering the second active portion;
and forming a first source electrode and a first drain electrode and a second source electrode and a second drain electrode on the same layer on the third insulating part respectively, wherein the first source electrode and the first drain electrode are electrically connected with the first active part respectively to form the switch thin film transistor, and the second source electrode and the second drain electrode are electrically connected with the second active part respectively to form the compensation thin film transistor.
The display panel of the embodiment of the application comprises a plurality of light emitting units and a plurality of driving units, wherein each driving unit is electrically connected with one light emitting unit, each driving unit comprises at least three thin film transistors, and orthographic projections of two thin film transistors in at least one driving unit on a plane where the light emitting units are located are at least partially overlapped. Through setting up two thin film transistors in the drive unit to the structure of partial coincidence, can be so that the occupation space of a plurality of thin film transistors reduces to reduce drive unit's occupation space, correspondingly, the number of drive unit in the unit area increases, and the size setting that the luminescence unit corresponds drive unit, consequently can improve display panel's resolution ratio.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings used in the description of the embodiments will be briefly described below. It is obvious that the drawings in the following description are only some embodiments of the application, and that other drawings can be derived from these drawings by a person skilled in the art without inventive effort.
For a more complete understanding of the present application and its advantages, reference is now made to the following descriptions taken in conjunction with the accompanying drawings. Wherein like reference numerals refer to like parts in the following description.
Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present application.
Fig. 2 is a schematic structural diagram of a driving circuit of the display panel shown in fig. 1.
Fig. 3 is a schematic structural diagram of a driving unit in the display panel shown in fig. 1.
Fig. 4 is a schematic structural diagram of a part of the structure of the driving unit shown in fig. 3.
Fig. 5 is a schematic flow chart of a manufacturing method of a display panel provided in an embodiment of the present application.
Fig. 6 is a schematic flow chart of a method for manufacturing a plurality of thin film transistors according to an embodiment of the present disclosure.
Fig. 7 is a schematic view of a manufacturing process of a plurality of thin film transistors according to an embodiment of the present disclosure.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The display panel may include a plurality of light emitting units and a plurality of driving units, each of the light emitting units is electrically connected to one of the driving units, and the driving units are used to drive the light emitting units to operate, and the light emitting units are generally designed according to the size of the driving units. The driving units are in one-to-one correspondence with the pixels, each driving unit generally comprises a plurality of thin film transistors, and the space occupied by the thin film transistors is the space occupied by one driving unit.
In order to solve the above problems, embodiments of the present application provide a display panel and a method for manufacturing the same. Hereinafter, the display panel and the method for manufacturing the display panel will be described in detail with reference to the accompanying drawings.
For example, please refer to fig. 1, and fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure. The embodiment of the present application provides a display panel 1, and the display panel 1 includes a plurality of light emitting units 10 and a plurality of driving units 20. Each driving unit 20 is electrically connected to one of the light emitting units 10. Each driving unit 20 comprises at least three thin film transistors, and orthogonal projections of two thin film transistors in at least one driving unit 20 on a plane where the light emitting unit 10 is located are at least partially overlapped. By arranging two tfts in the driving unit 20 to partially overlap, the occupied space of the tfts can be reduced, and thus the occupied space of the driving unit 20 is reduced, accordingly, the number of the driving units 20 per unit area is increased, and the light emitting unit 10 is arranged corresponding to the size of the driving unit 20, so that the resolution of the display panel 1 can be improved.
Wherein, each driving unit 20 may include a driving thin film transistor 22, a switching thin film transistor 24 and a compensation thin film transistor 26, the driving thin film transistor 22 is used for driving the light emitting unit 10 to operate; the switching thin film transistor 24 is used for controlling the on/off of the driving thin film transistor 22, and the switching thin film transistor 24 and the driving thin film transistor 22 are arranged at intervals; the compensation thin film transistor 26 is used for compensating the operation of the light emitting unit 10 driven by the driving thin film transistor 22, and the compensation thin film transistor 26 is nested with the switching thin film transistor 24. A nested arrangement is understood to mean that the switching tft 24 and the compensation tft 26 are arranged in a stack with an interconnection therebetween, and unlike a single arrangement, two tfts of a nested arrangement may share a portion of the components. For example, switching thin film transistor 24 may include a first gate, which is shared by compensation thin film transistor 26 and switching thin film transistor 24. The two thin film transistors are nested, so that the occupied space of a single driving unit 20 is reduced, the number of the driving units 20 in a unit area is increased, and the driving units 20 correspond to the pixels one by one, thereby being greatly helpful for manufacturing the display panel 1 with high resolution.
It should be noted that the composition of each driving unit 20 is not limited to the above-described structure. For example, each of the driving units 20 may include a driving thin film transistor 22 and two switching thin film transistors 24, and other types of thin film transistors, the two switching thin film transistors 24 being disposed in a nested arrangement and spaced apart from the driving thin film transistor 22. As another example, each driving unit 20 may include a driving tft 22 and two compensating tfts 26, and other types of tfts, wherein the two compensating tfts 26 are disposed in a nested manner and spaced apart from the driving tft 22. Each drive unit 20 may also be formed in other ways, which are not illustrated here.
In addition, please refer to fig. 2 in conjunction with fig. 1, and fig. 2 is a schematic structural diagram of a driving circuit of the display panel shown in fig. 1. The driving circuit of the display panel 1 generally has a 3T1C structure, that is, a driving circuit composed of three thin film transistors and 1 capacitor. The three thin film transistors may correspond to the driving thin film transistor 22, the switching thin film transistor 24, and the compensation thin film transistor 26 described above. As shown in fig. 2, T1, T2, and T3 represent thin film transistors having different functions, respectively. Wherein, T1 represents the switching tft 24, T2 represents the driving tft 24, and T3 represents the compensation tft 26, and the gate of T1 is applied with an oscillating voltage to control the conduction of T2, so as to provide a driving current to the diode to make the diode emit light. T3 is used to compensate for T2 when the operating state of T2 is poor or when it is necessary to increase the brightness of the diode. Cst is the storage capacitor, WR is the port of the write signal, and RD is the port of the read signal. VDD is the power supply voltage, VSS is ground. VCM being a reference voltage, VDataIs the data signal access port. Wherein the write signal WR, the read signal RD and the data signal VDataAre all provided by an external driving chip. Of course, the driving circuit of the display panel 1 may also have other structures, such as 5T1C, 7T1C, and the like, corresponding to different circuit structures of the display panel 1, and the nested arrangement of the embodiment of the present application may correspond to the nested arrangement of different thin film transistors, and may also correspond to the arrangement of the same thin film transistor. It is to be understood that the switching thin film transistor 24 and the compensation thin film transistor 26 in the driving circuit may be disposed in a nested structure, that two switching thin film transistors 24 may be disposed in a nested structure, and that two compensation thin film transistors 26 may be disposed in a nested structure. It is required to be noted thatThe structure and function of the driving tft 22 are different from those of the switching tft 24 and those of the compensating tft 26, and therefore the driving tft 22 is not selected to be nested with other tfts. The switching thin film transistor 24 and the compensation thin film transistor 26 have generally the same structure, so that the thin film transistors with the same structure can be nested to reduce the occupied space of the driving unit 20.
In order to more clearly explain the structure of the plurality of thin film transistors in the driving unit 20, the driving unit 20 will be explained below.
For example, referring to fig. 3, fig. 3 is a schematic structural diagram of a driving unit in the display panel shown in fig. 1. The display panel 1 further comprises a substrate 30. The switching thin film transistor 24 includes a first active portion 241, a first insulating portion 242, a first gate 243, a second insulating portion 244, a first source electrode 245, and a first drain electrode 246. The first active portion 241 is disposed on the substrate 30, the first insulating portion 242 is disposed on the first active portion 241, the first gate 243 is disposed on the first insulating portion 242, and the second insulating portion 244 is disposed on the first gate 243 and covers the first active portion 241, the first insulating portion 242, and the first gate 243. The first source 245 and the first drain 246 are disposed on a side of the second insulating portion 244 facing away from the first gate 243, and the first source 245 and the first drain 246 are electrically connected to the first active portion 241, respectively.
The first active portion 241 may be referred to as a semiconductor portion or a semiconductor active portion, and may be made of an oxide semiconductor material. The shape of the substrate 30 may be a direction, the first active portion 241 may be a rectangular island-shaped structure, and the first active layer 241 may be located in a partial region of the substrate 30.
The first insulating portion 242 is also referred to as a gate insulating portion, and is used to insulate the first active portion 241 from the first gate 243. The first insulating portion 242 may have an island-shaped structure with a rectangular shape, and the first insulating portion 242 may be disposed to overlap the first active portion 241, and it is understood that a partial region of the first insulating portion 242 overlaps a partial region of the first active portion 241.
The first gate 243 may be a rectangular island structure, and the pattern of the first gate 243 is similar to that of the first insulating portion 242. The material of the first gate 243 is typically a metal material.
The second insulating portion 244 is used to insulate the first source 245 and the first drain 246 from the first active portion 241, the first insulating portion 242, and the first gate 243 covered by the second insulating portion 244. The first source 245 may be electrically connected to the first active portion 241 through a via, and the first drain 246 may also be electrically connected to the first active portion 241 through a via.
The projection of the first gate 243 on the first active portion 241 may be a channel region of the first active portion 241, the projection of the first source 245 on the first active portion 241 may be a conductor region of the first active portion 241, and the projection of the first drain 246 on the first active portion 241 may also be a conductor region of the first active portion 241. The conductivity of the channel region is less than the conductivity of the conductor region, which is achieved by a conductimetric process to control the conductivity of the various portions. The first gate 243 is used for controlling the conduction of the channel region, and the first gate 243 can be understood as a switch, when a voltage is applied to the first gate 243, the first gate 243 attracts charges in the channel region to generate a current to the first source electrode 245 and the first drain electrode 246, so that the switching thin film transistor 24 enters an operating state. When the voltage is removed, the first gate 243 does not attract the charges in the channel region, and thus the first source 245 and the first drain 246 are not turned on, so that the switching thin film transistor 24 enters the non-operating state.
The compensation thin film transistor 26 includes a second active portion 261, a third insulating portion 262, a second source electrode 263, and a second drain electrode 264. The second active portion 261 is disposed between the second insulating portion 244 and the first source 245. The third insulating portion 262 is disposed on the second active portion 261 and covers the second active portion 261. The second source 263 and the second drain 264 are disposed on a side of the third insulating portion 262 away from the first gate 243 and located at the same layer as the first source 245, and the second source 263 and the second drain 264 are respectively electrically connected to the second active portion 261.
The second active portion 261, the third insulating portion 262, the second source 263 and the second drain 264 of the compensation tft 26 may refer to the description of the corresponding components of the switching tft 24, and are not described herein again. For example, referring to fig. 4, fig. 4 is a schematic structural diagram of a part of the driving unit shown in fig. 3. The length direction of the first active portion 241 may be perpendicular to the length direction of the second active portion 261 such that the first source electrode 245 does not overlap with the positions of the second source electrode 263 and the second drain electrode 264 and the first drain electrode 246 does not overlap with the positions of the second source electrode 263 and the second drain electrode 264. This arrangement also prevents interference between the first source electrode 245 and the first drain electrode 246 and the second source electrode 263 and the second drain electrode 264.
It should be noted that the compensation tft 26 and the switching tft 24 share the first gate 243, that is, the first gate 243 can control the charges in the channel region of the first active portion 241 to turn on the first source electrode 245 and the first drain electrode 246, and the first gate 243 can also control the charges in the channel region of the second active portion 261 to turn on the second source electrode 263 and the second drain electrode 264.
The driving thin film transistor 22 is disposed on the substrate 30. The display panel 1 further includes a light shielding portion 40 and a buffer portion 50, the light shielding portion 40 is disposed on the substrate 30 and is disposed opposite to the driving thin film transistor 22, and the driving thin film transistor 22 is electrically connected to the light shielding portion 40. The buffer portion 50 is disposed between the light shielding portion 40 and the driving thin film transistor 22. Here, the driving thin film transistor 22 is designed similarly to the switching thin film transistor 24, for example, the driving thin film transistor 22 may include a third active portion 221, a fourth insulating portion 222, a second gate electrode 223, a third source electrode 224, and a third drain electrode 225, and unlike the switching thin film transistor 24, the third source electrode 224 is electrically connected to the third active portion 221, and the third source electrode 224 is electrically connected to the light shielding portion 40.
Referring to fig. 5, fig. 5 is a schematic flow chart illustrating a manufacturing method of a display panel according to an embodiment of the present disclosure. The embodiment of the present application further provides a method for manufacturing a display panel, and the structure of the display panel 1 can refer to the structures shown in fig. 1 to 4 and the above description. The preparation method comprises the following steps:
101. a substrate is provided.
102. The method comprises the steps of preparing a plurality of thin film transistors on a substrate, dividing the thin film transistors into a plurality of driving units, wherein each driving unit comprises at least three thin film transistors, and orthographic projections of two thin film transistors in at least one driving unit on a plane where a light emitting unit is located are at least partially overlapped.
103. And forming a light-emitting unit corresponding to each driving unit, and electrically connecting the light-emitting unit with the driving units.
By arranging two tfts in the driving unit 20 to partially overlap, the occupied space of the tfts can be reduced, and thus the occupied space of the driving unit 20 is reduced, accordingly, the number of the driving units 20 per unit area is increased, and the light emitting unit 10 is arranged corresponding to the size of the driving unit 20, so that the resolution of the display panel 1 can be improved.
Referring to fig. 6 and 7, fig. 6 is a schematic flow chart of a method for manufacturing a plurality of thin film transistors according to an embodiment of the present disclosure, and fig. 7 is a schematic view of a process for manufacturing a plurality of thin film transistors according to an embodiment of the present disclosure. For the method of manufacturing the plurality of thin film transistors in step 102, the following steps may be referred to. That is, the preparation method of the embodiment of the present application further includes:
201. a substrate is provided.
The material of the substrate 30 may be a glass material, and a substrate 30 is provided and cleaned to facilitate subsequent manufacturing processes.
After the substrate 30 is cleaned, a layer of metal with a thickness of 500-2000A may be deposited as the light shielding portion 40 material, and the light shielding portion 40 material may be a metal such as Mo, Al, Cu, Ti, or an alloy material. The pattern of the light shielding portions 40 is defined to form the light shielding portions 40.
A layer of buffer 50 material may also be deposited on the light shielding portion 40, and the buffer 50 material may be a single layer of Si3N4, a single layer of SiO2, or a single layer of SiON, and may also be a double-layer film of Si3N4, SiO2, and SiON materials. The buffer portion 50 is deposited to have a thickness ranging from 1000A to 5000A to reduce the influence of the substrate 30 on the active portion.
202. A first active portion is formed on a substrate.
An active layer material, such as an oxide semiconductor material, is deposited and covers the buffer 50. The active layer material may be IGZO, IZTO, IGZTO, etc., and the thickness of the active layer material ranges from 100A to 1000A. The active layer material is patterned to form spaced first and third active portions 241 and 221. The first active portion 241 may include a channel region and a conductor region, and the first active portion 241 is defined to form the channel region and the conductor region. The third active portion 221 is provided in the same manner as the first active portion 241. It should be noted that, the same process is used for preparing the plurality of thin film transistors, so that the layer-by-layer preparation is used during the preparation to form the plurality of thin film transistors which are arranged in parallel and spaced, and the embodiment of the present application takes the preparation of the driving thin film transistor 22, the switching thin film transistor 24 and the compensation thin film transistor 26 as an example, which should not be construed as a limitation to the preparation method of the display panel.
203. A first insulating portion and a first gate electrode are respectively formed on the first active portion, the first insulating portion being located between the first active portion and the first gate electrode.
And depositing an insulating layer, wherein the insulating layer can be made of SiOx, SiNx or a multilayer structure film and covers the whole active layer pattern, and the material deposition thickness of the insulating layer ranges from 1000A to 3000A.
And depositing a grid layer material and covering the insulating layer material. The gate layer material may be a transition metal material, such as Mo, Al, Cu, Ti, and alloys thereof. The thickness of the gate layer material ranges from 2000A to 8000A.
The first gate 243 is etched by a yellow light, and the first insulating portion 242 is etched by the first gate 243 by self-aligned etching. Only under the first gate 243 is the first insulating portion 242 present, and the remaining portion of the insulating layer material is etched away. Accordingly, the pattern of the second gate 223 is etched, and then the fourth insulating portion 222 is etched by using the pattern of the second gate 223 as a self-aligned etching.
Depositing a layer of metal Al with the thickness of 50-100A, and annealing, wherein the Al is combined with O in the active layer covered by the Al to form a conductor layer, and the rest part of the active layer is not processed to maintain the semiconductor characteristics.
204. A second insulating portion is formed on the first gate electrode, covering the first active portion, the first insulating portion and the first gate electrode.
A second insulating layer 244 is deposited, which may comprise SiOx, SiNx, or an organic material, wherein the thickness of the second insulating layer 244 is 2000A-10000A. The second insulating portion 244 covers the first active portion 241, the first insulating portion 242, and the first gate 243, and the second insulating portion 244 covers the third active portion 221, the fourth insulating portion 222, and the second gate 223.
205. A second active portion is formed on the second insulating portion.
A second active portion 261 is formed on the second insulating portion 244 corresponding to the first gate 243, i.e., a layer of metal oxide material is deposited first, and then the pattern of the second active portion 261 is defined.
206. A third insulating portion is formed on the second insulating portion and covers the second active portion.
An insulating layer of material, such as SiOx or SiNx or an organic material, is deposited as the third insulating portion 262. The thickness of the third insulating portion 262 may be set as needed, and is not limited herein.
207. And forming a first source electrode and a first drain electrode and a second source electrode and a second drain electrode which are in the same layer on the third insulating part respectively, wherein the first source electrode and the first drain electrode are electrically connected with the first active part respectively to form a switch thin film transistor, and the second source electrode and the second drain electrode are electrically connected with the second active part respectively to form a compensation thin film transistor.
A layer of transparent metal, which may be ITO, IZO, or a multi-layer film, or an alloy, is deposited as the source and drain metal layers, with a thickness of 2000-. The first source electrode 245 and the first drain electrode 246 are electrically connected to the first active portion 241, respectively, to form the switching thin film transistor 24. The second source electrode 263 and the second drain electrode 264 are electrically connected to the second active portion 261, respectively, to form the compensation thin film transistor 26. The third source electrode 224 and the third drain electrode 225 are electrically connected to the third active portion 221, respectively, to form the driving thin film transistor 22.
And finally, a PV layer can be deposited to protect the thin film transistor from being invaded by external air and water vapor.
The above process is a process for manufacturing a plurality of thin film transistors.
According to the display panel and the manufacturing method thereof provided by the embodiment of the application, the display panel 1 comprises a plurality of light emitting units 10 and a plurality of driving units 20, each driving unit 20 is electrically connected with one light emitting unit 10, each driving unit 20 comprises at least three thin film transistors, and orthographic projections of two thin film transistors in at least one driving unit 20 on a plane where the light emitting units 10 are located are at least partially overlapped. By arranging two tfts in the driving unit 20 to partially overlap, the occupied space of the tfts can be reduced, and thus the occupied space of the driving unit 20 is reduced, accordingly, the number of the driving units 20 per unit area is increased, and the light emitting unit 10 is arranged corresponding to the size of the driving unit 20, so that the resolution of the display panel 1 can be improved.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
In the description of the present application, the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more features.
The display panel and the manufacturing method thereof provided by the embodiments of the present application are described in detail above, and the principle and the embodiment of the present application are explained by applying specific examples herein, and the description of the embodiments above is only used to help understanding the method and the core idea of the present application; meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (10)
1. A display panel, comprising:
a plurality of light emitting units;
each driving unit is electrically connected with one light emitting unit and comprises at least three thin film transistors, and orthographic projections of two thin film transistors in at least one driving unit on a plane where the light emitting units are located are at least partially overlapped.
2. The display panel according to claim 1, wherein the driving unit comprises:
the driving thin film transistor is used for driving the light emitting unit to work;
the switch thin film transistor is used for controlling the drive thin film transistor to be switched on or switched off, and the switch thin film transistor and the drive thin film transistor are arranged at intervals; and
and the compensation thin film transistor is used for compensating the driving thin film transistor to drive the light-emitting unit to work, and the compensation thin film transistor and the switch thin film transistor are nested.
3. The display panel according to claim 2, wherein the switching thin film transistor includes a first gate electrode, and the compensation thin film transistor and the switching thin film transistor share the first gate electrode.
4. The display panel according to claim 3, wherein the display panel further comprises a substrate, and the switching thin film transistor comprises:
a first active portion disposed on the substrate;
a first insulating portion provided to the first active portion;
the first grid is arranged on the first insulating part;
a second insulating portion disposed on the first gate and covering the first active portion, the first insulating portion, and the first gate; and
the first source electrode and the first drain electrode are arranged on one side, away from the first grid electrode, of the second insulating part, and the first source electrode and the first drain electrode are electrically connected with the first active part respectively;
the compensation thin film transistor includes:
a second active portion disposed between the second insulating portion and the first source electrode;
a third insulating portion disposed on the second active portion and covering the second active portion; and
and the second source electrode and the second drain electrode are arranged on one side of the third insulating part, which is deviated from the first grid electrode, and are positioned on the same layer as the first source electrode, and the second source electrode and the second drain electrode are respectively and electrically connected with the second active part.
5. The display panel according to claim 4, wherein a longitudinal direction of the first active portion is perpendicular to a longitudinal direction of the second active portion.
6. The display panel according to claim 4, wherein the driving thin film transistor is disposed on the substrate, the display panel further comprising:
a light shielding portion disposed on the substrate and disposed opposite to the driving thin film transistor, the driving thin film transistor being electrically connected to the light shielding portion;
and a buffer part arranged between the light shielding part and the driving thin film transistor.
7. The display panel according to claim 1, wherein the driving unit comprises:
the driving thin film transistor is used for driving the light emitting unit to work;
the driving thin film transistor is used for driving the driving thin film transistor to be in a state of being connected with the driving thin film transistor;
or the drive unit includes:
the driving thin film transistor is used for driving the light emitting unit to work;
the compensation thin film transistor and the driving thin film transistor are arranged at intervals, and the two compensation thin film transistors are arranged in a nested manner.
8. A method for manufacturing a display panel, comprising:
providing a substrate;
preparing a plurality of thin film transistors on the substrate, dividing the thin film transistors into a plurality of driving units, wherein each driving unit comprises at least three thin film transistors, and orthographic projections of two thin film transistors in at least one driving unit on a plane where the light-emitting units are located are at least partially overlapped;
and forming a light-emitting unit corresponding to each driving unit, and electrically connecting the light-emitting unit with the driving units.
9. The method according to claim 8, wherein the manufacturing a plurality of thin film transistors on the substrate comprises:
manufacturing a driving thin film transistor, wherein the driving thin film transistor is used for driving the light-emitting unit to work;
manufacturing a switch thin film transistor, wherein the switch thin film transistor and the driving thin film transistor are arranged at intervals, and the switch thin film transistor is used for controlling the driving thin film transistor to be switched on or switched off;
and manufacturing a compensation thin film transistor, wherein the compensation thin film transistor is nested with the switch thin film transistor, and the compensation thin film transistor is used for compensating the driving thin film transistor to drive the light-emitting unit to work.
10. The method of manufacturing according to claim 9, wherein the nested arrangement of the compensation thin film transistor and the switching thin film transistor comprises:
forming a first active portion on the substrate;
forming a first insulating portion and a first gate electrode on the first active portion, respectively, the first insulating portion being located between the first active portion and the first gate electrode;
forming a second insulating portion on the first gate electrode, the second insulating portion covering the first active portion, the first insulating portion, and the first gate electrode;
forming a second active portion on the second insulating portion;
forming a third insulating portion on the second active portion and covering the second active portion;
and forming a first source electrode and a first drain electrode and a second source electrode and a second drain electrode on the same layer on the third insulating part respectively, wherein the first source electrode and the first drain electrode are electrically connected with the first active part respectively to form the switch thin film transistor, and the second source electrode and the second drain electrode are electrically connected with the second active part respectively to form the compensation thin film transistor.
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