CN113312896A - Hardware description language VHDL standard inspection tool - Google Patents
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Abstract
The invention belongs to the technical field of hardware description language specification checking tool design, and particularly relates to a hardware description language VHDL specification checking tool. Aiming at reducing the requirement of code specification violation errors generated in the VHDL code development stage, the invention designs a hardware description language VHDL specification inspection tool by taking a Debian system as the use environment of the specification inspection tool. The VHDL code detection system comprises a file batch processing module, a lexical analysis module, a syntax analysis module, a semantic analysis module and a problem positioning module, can realize automatic detection of VHDL coding rule convention, has the characteristics of displaying violation rule code line number and file name, supporting command line operation, supporting multi-file batch processing, having low requirement on hardware performance, supporting a mainstream Linux system and the like, and improves the efficiency and flexibility of VHDL code detection by a standard detection tool.
Description
Technical Field
The invention belongs to the technical field of hardware description language specification checking tool design, and particularly relates to a hardware description language VHDL specification checking tool.
Background
The VHDL language is a high-level language for circuit design. It appeared in the late 80 s. Originally developed by the U.S. department of defense, a less versatile hardware design language for the united states forces to improve the reliability and reduce the development cycle of a design. The VHDL is translated into Chinese, namely a hardware description language of the ultra-high-speed integrated circuit, and is mainly applied to the design of a digital circuit. VHDL is used primarily to describe the structure, behavior, functionality, and interfaces of digital systems. Except for the fact that it contains many statements with hardware features, the linguistic form, description style, and syntax of VHDL are very similar to a general computer high-level language. After an external interface is defined for a design entity, once its internal development is complete, other designs can invoke the entity directly. This concept of dividing the design entity into inner and outer parts is the fundamental point of VHDL system design. VHDL has, compared to other hardware descriptions: the system has the characteristics of strong function, flexible design, wide support, easy modification, strong system hardware description capacity, independence from the design of devices, process independence, strong portability, easy sharing and reuse and the like.
The basic task of lexical analysis is to scan a source program from left to right character by character to generate individual word symbols, and to transform the source program in the form of a character string into an intermediate program in the form of a string of word symbols. The program that performs lexical analysis is called a lexical analysis program, also called a lexical analyzer or scanner. The lexical analyzer functions as an input source program and outputs word symbols.
The basic task of syntactic analysis is to analyze and judge whether the syntactic structure of a program conforms to syntactic rules on the basis that lexical analysis identifies word strings. The grammatical structure of a language is described in Context Free Grammar (CFG). The task of the parser is therefore essentially to determine whether the entire word string constitutes a syntactically correct procedure, in terms of the production of a context-free grammar.
The primary role of semantic analysis is to examine the semantics of each grammar component. Semantic checks are also inevitably performed during semantic analysis, as lexical analyses and grammar analyses are performed simultaneously with lexical checks and grammar checks. Dynamic semantic checking requires the generation of corresponding object code, which is performed at runtime, while static semantic checking is performed immediately after parsing to generate a syntax tree. The semantic analysis comprises the following steps: type checking, control flow checking, consistency checking, etc. Semantics are context-dependent, so formalized description of semantics is very difficult, and at present, it is common to use attribute grammar as a tool for describing program language semantics and use a grammar-guided translation method to complete the translation work of grammar components.
The Huangzi is the aerospace model FPGA hardware description language code inspection software design [ D ]. Harbin industry university, 2017 discloses a code specification inspection tool for a hardware description language Verilog, a developed hardware inspection tool takes a Windows system as a use environment, performs lexical analysis and syntactic analysis according to a grammatical specification of the Verilog language, takes Q/WE1117-2014 courtyard FPGA hardware description language programming criterion as a code detection specification, and realizes graphical interface display based on MFC development Notepad + + extension plug-in. The difference between the developed hardware language specification checking tool and the invention is that: the use environment of the scheme is a Windows operating system, and the use environment of the invention is a Linux operating system; the language checked by the scheme is Verilog language, and the language detected by the invention is VHDL language; the scheme only carries out lexical analysis and syntactic analysis actually, and is difficult to detect more complex parts in syntactic specifications, and the lexical analysis, the syntactic analysis and the semantic analysis are carried out during code detection, so that deeper semantics in codes can be analyzed, and the aim of detecting more syntactic specifications is fulfilled.
Disclosure of Invention
The invention aims to provide a hardware description language VHDL specification checking tool.
The purpose of the invention is realized by the following technical scheme: the system comprises a file batch processing module, a lexical analysis module, a syntax analysis module, a semantic analysis module and a problem positioning module; the file batch processing module is used for preprocessing the detected VHDL file and calling a lexical analysis module to perform lexical analysis; the lexical analysis module scans the VHDL file from left to right and divides the character stream into token streams; the token is a string of characters which can not be further divided in the source file; the lexical analysis module compares an input character stream with lexical rules, if characters violating the lexical rules exist in the character stream, the line number of the characters appearing in a source file and the type information of the violating rules are recorded, and the information is transmitted to the problem positioning module to be used for displaying error information in a command line; the grammar analysis module receives a token stream generated by the lexical analysis module and converts the token stream into a grammar tree; if a certain token stream can not be identified, recording the number of lines of the token stream appearing in the source file and the type information of the violated rule, transmitting the information to a problem locating module for displaying error information in a command line, and for the token stream which can be identified, generating a grammar tree corresponding to a corresponding grammar structure and recording the attribute of the grammar tree at each node of the grammar tree; the semantic analysis module receives the syntax tree generated by the syntax analysis module, compares the attributes of the nodes in the syntax tree with semantic rules built in the semantic analysis module, and performs semantic analysis; if the semantic specification is not met, recording the number of lines of the source file and the type information of the violated rules, and transmitting the information to a problem positioning module for displaying error information in the command line; the attributes comprise inheritance attributes and comprehensive attributes; the inheritance attribute is obtained by calculating the root node attribute of the node in the syntax tree and is used for transmitting information downwards from the root node to the branch node of the syntax tree; the comprehensive attribute is obtained by calculating the branch node attribute of the node in the syntax tree and is used for transmitting information upwards from the branch node to the root node of the syntax tree.
The invention has the beneficial effects that:
aiming at reducing the requirement of code specification violation errors generated in the VHDL code development stage, the invention designs a hardware description language VHDL specification inspection tool by taking a Debian system as the use environment of the specification inspection tool. The VHDL code detection system comprises a file batch processing module, a lexical analysis module, a syntax analysis module, a semantic analysis module and a problem positioning module, can realize automatic detection of VHDL coding rule convention, has the characteristics of displaying violation rule code line number and file name, supporting command line operation, supporting multi-file batch processing, having low requirement on hardware performance, supporting a mainstream Linux system and the like, and improves the efficiency and flexibility of VHDL code detection by a standard detection tool.
Drawings
FIG. 1 is a block diagram of the flow of VHDL code checking according to the present invention.
Fig. 2(a) is a schematic diagram of the operation of the lexical analysis module of the present invention.
FIG. 2(b) is a diagram illustrating the operation of the parsing module of the present invention.
FIG. 2(c) is a schematic diagram of the semantic analysis module according to the present invention.
Fig. 3 is a block diagram of the present invention.
Detailed Description
The invention is further described below with reference to the accompanying drawings.
The invention belongs to the technical field of hardware description language specification checking tool design in the field of computers. Aiming at reducing the requirement of code specification violation errors generated in the VHDL code development stage, the invention designs a hardware description language VHDL specification inspection tool by taking a Debian system as the use environment of the specification inspection tool. The VHDL code detection system comprises a file batch processing module, a lexical analysis module, a syntax analysis module, a semantic analysis module and a problem positioning module, can realize automatic detection of VHDL coding rule convention, has the characteristics of displaying violation rule code line number and file name, supporting command line operation, supporting multi-file batch processing, having low requirement on hardware performance, supporting a mainstream Linux system and the like, and improves the efficiency and flexibility of VHDL code detection by a standard detection tool.
The invention overcomes the technical bottleneck that the traditional hardware description language development tool is difficult to detect the error in the VHDL code according to the coding specification, and solves the VHDL code detection problem. The invention is divided into five parts: the system comprises a file batch processing module, a lexical analysis module, a syntax analysis module, a semantic analysis module and a problem positioning module. The specification inspection tool constructed in the way can realize batch accurate inspection on a large number of VHDL files.
When the VHDL file is detected by using the method, the file batch processing module firstly preprocesses the detected file and calls the lexical analysis module to carry out lexical analysis. The lexical analysis module scans the VHDL file from left to right and divides the character stream into words (tokens), wherein the tokens are a string of characters which can not be further divided in the source file. The method comprises the steps of setting a series of lexical rules in a lexical analysis module, wherein the lexical rules generally correspond to some basic naming specifications in VHDL, comparing an input character stream with the lexical rules, recording the number of lines of characters appearing in a source file and type information of violated rules if the characters violating the lexical rules exist in the character stream, and transmitting the information to a problem positioning module for displaying error information in a command line.
And the grammar analysis module receives the token stream generated by the lexical analysis module, and the token stream is converted into a grammar tree to prepare for a subsequent semantic analysis module. The syntactic analysis is intended to determine not only whether a given sentence conforms to the syntactic structure, but also to analyze which structures the sentence conforms to, i.e., how the sentence is generated from the starting symbol, and to generate a syntactic tree according to the generation process. A series of grammar specifications are built in the grammar analysis module, and the grammars are used for judging whether the grammars conform to the standard grammar of the VHDL. If a token stream cannot be identified, the number of lines it appears in the source file and the type information of the violated rule are recorded, and the information is passed to the problem locator module for displaying error information in the command line. If a token stream can be identified, it is necessary to generate a syntax tree corresponding to the corresponding syntax structure and to record its attributes at each node of the syntax tree, for example: type, value, range, etc., for use in lexical analysis.
The semantic analysis module is a core module of the tool, receives the syntax tree generated by the syntax analysis module, and performs semantic analysis according to the attributes of the nodes in the syntax tree. Attributes can be divided into two categories, inherited and integrated, where inherited attributes are used to pass information "from top to bottom". The inheritance attribute is calculated by the father node attribute of the node in the corresponding syntax tree, namely, the inheritance attribute is transmitted downwards along the syntax tree from the root node to the branch (child) node, and the inheritance attribute reflects the characteristic of context dependence. Inheritance properties can be conveniently used to represent structural relationships of program language contexts. The composite attribute is used to pass information "bottom-up". The composite attribute is calculated from the branch node (i.e., child node) attributes of the nodes in the corresponding parse tree, and the transmission direction of the composite attribute is opposite to the inheritance attribute, i.e., the composite attribute is transmitted upwards along the parse tree from the branch node to the root node. The semantic information is obtained in the mode, the semantic information is compared with the semantic rules built in the semantic analysis module, if the semantic rules do not accord with the semantic specification, the line number of the semantic information appearing in the source file and the type information of the violated rules are recorded, and the information is transmitted to the problem positioning module to be used for displaying error information in the command line.
Example 1:
aiming at reducing the requirement of code specification violation errors generated in the VHDL code development stage, a Debian system is used as the use environment of a specification detection tool, lexical analysis, syntactic analysis and semantic analysis technical research is carried out according to the grammatical specification of a VHDL language, the technical bottleneck that the traditional hardware description language development tool is difficult to accurately detect errors in the VHDL code according to the code specification is broken through, and the VHDL code detection problem is solved. The file batch processing module, the lexical analysis module, the syntax analysis module, the semantic analysis module and the problem positioning module are formed, and the efficiency and the flexibility of the VHDL code detection of the standard inspection tool are improved.
And researching and sorting out a VHDL standard syntax specification, a common uncompoundable code writing mode and a general VHDL code writing style, and taking the three types as the detection specifications of the tool. In which the case of non-compliance with the VHDL standard syntax specification and non-synthesizable code writing style is classified as error (error) and the case of non-compliance with the general VHDL code writing style is classified as warning (warning). The tool takes the expanded specification as a detection standard, so that the VHDL code has higher availability, robustness and universality. The expanded specification is refined and divided into 16 rules, which are respectively: naming rules, basic cell design rules, reset signal usage rules, clock signal usage rules, asynchronous circuit processing rules, RTL descriptive syntax constraint rules, combinational logic design rules, sequential logic design rules, tristate buffer design rules, process usage rules, IF statement syntax rules, CASE statement syntax rules, FOR statement description rules, operator usage rules, finite state machine development rules, testable design rules. Each rule is further refined into a plurality of specific descriptions, and when a code violation is detected, the tool can specifically indicate the description of the violation.
As shown in fig. 1, the hardware description language VHDL specification checking tool can be divided into five modules, which are: the system comprises a file batch processing module, a lexical analysis module, a syntax analysis module, a semantic analysis module and a problem positioning module. When code detection is needed for batch VHDL files, a file batch processing module firstly preprocesses the files, one VHDL file is sent to a lexical analysis module at a time for lexical analysis, as shown in FIG. 2(a), the lexical analysis module processes an input character stream, divides the character stream into token streams and performs lexical analysis according to a lexical rule table, and if a lexical error occurs, error information is transmitted to a problem positioning module. As shown in fig. 2(b), the parsing module receives the token stream generated by the lexical analysis module, converts it into a syntax tree and parses it against the grammar rule table, and if a syntax error occurs, passes the error information to the problem location module. As shown in fig. 2(c), the semantic analysis module receives the syntax tree generated by the syntax analysis module and performs semantic analysis against the semantic rule table, and if a semantic error occurs, transmits error information to the problem location module. As shown in FIG. 3, the problem location module can accurately display the rule violated by the code and the location of the error code according to the error information flowing into the module.
The invention is composed of a lexical analysis module, a syntactic analysis module and a semantic analysis module. The lexical analysis module is used for scanning an input VHDL file from left to right, dividing a character stream into character strings which can not be further divided, and reporting lexical errors in the file. The grammar analysis module is used for converting the character stream generated by the lexical analysis module into a grammar tree and reporting grammar errors of the sentence, and setting corresponding attributes for each node in the grammar tree. The semantic analysis module is used for scanning a syntax tree generated in the syntax analysis stage and investigating the attribute of each node so as to judge whether the syntax tree conforms to the semantics, and if the syntax tree does not conform to the semantic standard, a semantic error is reported.
The lexical rules of the hardware description language may be constantly changed, and the lexical analysis module is the most basic module of the tool, and once modification occurs, the upper syntactic analysis module and the semantic analysis module may be changed accordingly. The tool uses a flexible extension model, and only needs to compile the newly added lexical specification according to a specified format and place the newly compiled lexical rule file into a corresponding folder. By adopting the structure, the expandability of the tool can be improved to a great extent, and the service cycle of the tool is prolonged.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (1)
1. A hardware description language VHDL specification inspection tool, characterized by: the system comprises a file batch processing module, a lexical analysis module, a syntax analysis module, a semantic analysis module and a problem positioning module; the file batch processing module is used for preprocessing the detected VHDL file and calling a lexical analysis module to perform lexical analysis; the lexical analysis module scans the VHDL file from left to right and divides the character stream into token streams; the token is a string of characters which can not be further divided in the source file; the lexical analysis module compares an input character stream with lexical rules, if characters violating the lexical rules exist in the character stream, the line number of the characters appearing in a source file and the type information of the violating rules are recorded, and the information is transmitted to the problem positioning module to be used for displaying error information in a command line; the grammar analysis module receives a token stream generated by the lexical analysis module and converts the token stream into a grammar tree; if a certain token stream can not be identified, recording the number of lines of the token stream appearing in the source file and the type information of the violated rule, transmitting the information to a problem locating module for displaying error information in a command line, and for the token stream which can be identified, generating a grammar tree corresponding to a corresponding grammar structure and recording the attribute of the grammar tree at each node of the grammar tree; the semantic analysis module receives the syntax tree generated by the syntax analysis module, compares the attributes of the nodes in the syntax tree with semantic rules built in the semantic analysis module, and performs semantic analysis; if the semantic specification is not met, recording the number of lines of the source file and the type information of the violated rules, and transmitting the information to a problem positioning module for displaying error information in the command line; the attributes comprise inheritance attributes and comprehensive attributes; the inheritance attribute is obtained by calculating the root node attribute of the node in the syntax tree and is used for transmitting information downwards from the root node to the branch node of the syntax tree; the comprehensive attribute is obtained by calculating the branch node attribute of the node in the syntax tree and is used for transmitting information upwards from the branch node to the root node of the syntax tree.
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