CN113312284A - Data transmission method, device, system, storage medium and electronic device - Google Patents
Data transmission method, device, system, storage medium and electronic device Download PDFInfo
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
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Abstract
The embodiment of the invention provides a data transmission method, a data transmission device, a data transmission system, a data transmission storage medium and an electronic device; wherein, the method comprises the following steps: under the condition that first data to be transmitted to a host computer exist in a slave computer, acquiring a data receiving state of a first Direct Memory Access (DMA) arranged in the slave computer; determining the potential of a target pin preset between the host and the slave; and under the condition that the data receiving state is determined to be a data unreceiving state and the potential of the target pin is determined to be a second potential, adjusting the potential of the target pin to be a first potential so as to instruct the host to read the first data in the slave. The invention solves the problems that processor resources are wasted and only fixed-length data can be transmitted because the slave machine sends data to the host machine in the data transmission process in the related technology, and achieves the effects of saving the processor resources and transmitting the data with indefinite length.
Description
Technical Field
The embodiment of the invention relates to the field of communication, in particular to a data transmission method, a data transmission device, a data transmission system, a data transmission storage medium and an electronic device.
Background
In the related art, during data transmission of the SPI master and the SPI slave, the slave may actively transmit data to the master through the SPI (Serial Peripheral Interface) by causing the master to periodically generate a clock signal, but the processor resource is wasted by causing the master to periodically generate the clock signal to transmit the data.
SPI, a serial peripheral interface, is a high-speed, full-duplex, synchronous communications bus. Such a bus is typically used for data transmission between the embedded processor and the peripheral chip. SPI is a full-duplex synchronous communication bus, i.e., the host is also receiving data when sending data and vice versa. For example, when the master sends data, the slave must return some data, which may be the data the slave wants to send, but may also be null data sent by the slave in order to reply to the master. This means that the master cannot determine whether or not the received data is null data transmitted from the slave at the time of transmission. Generally, to increase the communication rate of SPI communication, hardware DMA (Direct Memory Access) is used, and when DMA is used, the length of transmission data needs to be specified. In short, when SPI transmission and reception is performed using a DMA in the full duplex mode, data size setting of the DMA is a troublesome problem.
Therefore, in the related art, the problems that processor resources are wasted and only fixed-length data can be transmitted due to the fact that data are sent from the slave to the host in the data transmission process exist.
In view of the above problems in the related art, no effective solution has been proposed.
Disclosure of Invention
The embodiment of the invention provides a data transmission method, a data transmission device, a data transmission system, a storage medium and an electronic device, which are used for at least solving the problems that processor resources are wasted and only fixed-length data can be transmitted due to the fact that data are sent from a slave computer to a host computer in the data transmission process in the related technology.
According to an embodiment of the present invention, there is provided a data transmission method including: under the condition that first data to be transmitted to a host computer exist in a slave computer, acquiring a data receiving state of a first Direct Memory Access (DMA) arranged in the slave computer; under the condition that the data receiving state is determined to be a data unreceiving state, determining the current potential of a target pin preset between the host and the slave, wherein the current potential of the target pin is used for indicating the data transmission direction between the host and the slave, when the potential is a first potential, the data transmission direction is that the host reads data in the slave, and when the potential is a second potential, the data transmission direction is that the host sends data to the slave; and under the condition that the current potential of the target pin is determined to be a second potential, adjusting the potential of the target pin to be a first potential so as to instruct the host to read the first data in the slave.
According to an embodiment of the present invention, there is also provided a data transmission method, including: detecting the current potential of a target pin preset between a host and a slave, wherein the current potential of the target pin is used for indicating the data transmission direction between the host and the slave, when the potential is a first potential, the data transmission direction is that the host reads data in the slave, and when the potential is a second potential, the data transmission direction is that the host sends data to the slave; under the condition that the current potential of the target pin is determined to be a first potential, reading first data stored in the slave machine and to be transmitted to a host machine; and sending second data stored in the host machine and to be transmitted to the slave machine under the condition that the current potential of the target pin is determined to be a second potential.
According to another embodiment of the present invention, there is provided a data transmission apparatus including: the device comprises an acquisition module, a processing module and a processing module, wherein the acquisition module is used for acquiring a data receiving state of a first Direct Memory Access (DMA) arranged in a slave under the condition that first data to be transmitted to a host exist in the slave; the determining module is configured to determine a current potential of a target pin preset between the host and the slave when the data receiving state is determined to be a data unreceived state, where the current potential of the target pin is used to indicate a data transmission direction between the host and the slave, the data transmission direction is that the host reads data in the slave when the potential is a first potential, and the data transmission direction is that the host sends data to the slave when the potential is a second potential; and the adjusting module is used for adjusting the potential of the target pin to be a first potential under the condition that the current potential of the target pin is determined to be a second potential so as to instruct the host to read the first data in the slave.
According to another embodiment of the present invention, there is also provided a data transmission apparatus including: the detection module is used for detecting the current potential of a target pin preset between a host and a slave, wherein the current potential of the target pin is used for indicating the data transmission direction between the host and the slave, the data transmission direction is that the host reads data in the slave when the potential is a first potential, and the data transmission direction is that the host sends data to the slave when the potential is a second potential; the reading module is used for reading first data stored in the slave machine and to be transmitted to the host machine under the condition that the current potential of the target pin is determined to be a first potential; and the sending module is used for sending second data stored in the host machine and to be transmitted to the slave machine under the condition that the current potential of the target pin is determined to be a second potential.
According to another embodiment of the present invention, a data transmission system is provided, which includes the host, the slave and the target pin in any of the above embodiments, wherein the host and the slave are connected through the target pin.
According to a further embodiment of the present invention, there is also provided a computer-readable storage medium having a computer program stored thereon, wherein the computer program is arranged to perform the steps of any of the above method embodiments when executed.
According to yet another embodiment of the present invention, there is also provided an electronic device, including a memory in which a computer program is stored and a processor configured to execute the computer program to perform the steps in any of the above method embodiments.
According to the invention, under the condition that first data to be sent to a host computer exists in the slave computer, the data receiving state of a first direct memory access DMA arranged in the slave computer is obtained, under the condition that the data receiving state is determined to be a data unreceiving state, the current potential of a target pin preset between the host computer and the slave computer is determined, under the condition that the current potential of the target pin is determined to be a second potential, the current potential of the target pin is adjusted to be the first potential, and at the moment, the host computer can read the first data in the slave computer. When the current potential of the target pin is the second potential, the host can send data to the slave. When the first direct memory access DMA is in a data unreceived state and the current potential of the target pin is the first potential, the host can read data in the slave, and the data transmission can be realized based on the potential of the target pin without periodically generating a clock signal by the host. In addition, when the potential of the target pin is the first potential, the host can continuously read data in the slave, and when the potential of the target pin is the second potential, the host can continuously send data to the slave, so that the transmission of the data with indefinite length is realized. Therefore, the problems that processor resources are wasted and only fixed-length data can be transmitted due to the fact that data are sent from the slave to the host in the data transmission process in the related technology can be solved, and the effects of saving the processor resources and transmitting the data with indefinite length are achieved.
Drawings
Fig. 1 is a block diagram of a hardware configuration of a mobile terminal of a data transmission method according to an embodiment of the present invention;
FIG. 2 is a first flowchart of a data transmission method according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a master and slave communication connection according to an exemplary embodiment of the present invention;
FIG. 4 is a flow chart of a slave sending data to a master according to an exemplary embodiment of the present invention;
fig. 5 is a waveform diagram when a slave transmits data according to an exemplary embodiment of the present invention;
FIG. 6 is a flow chart of data sent by a slave receiving master in accordance with an exemplary embodiment of the present invention;
FIG. 7 is a second flowchart of a data transmission method according to an embodiment of the present invention;
FIG. 8 is a flow chart of a master receiving data sent by a slave according to an exemplary embodiment of the present invention;
FIG. 9 is a flow chart of a master sending data to a slave according to an exemplary embodiment of the present invention;
fig. 10 is a waveform diagram when a host transmits data according to an exemplary embodiment of the present invention;
FIG. 11 is a block diagram of a data transmission apparatus according to an embodiment of the present invention;
fig. 12 is a block diagram of a data transmission apparatus according to an embodiment of the present invention.
Detailed Description
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings in conjunction with the embodiments.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.
The method embodiments provided in the embodiments of the present application may be executed in a mobile terminal, a computer terminal, or a similar computing device. Taking an example of the operation on a mobile terminal, fig. 1 is a hardware structure block diagram of the mobile terminal of a data transmission method according to an embodiment of the present invention. As shown in fig. 1, the mobile terminal may include one or more (only one shown in fig. 1) processors 102 (the processor 102 may include, but is not limited to, a processing device such as a microprocessor MCU or a programmable logic device FPGA), and a memory 104 for storing data, wherein the mobile terminal may further include a transmission device 106 for communication functions and an input-output device 108. It will be understood by those skilled in the art that the structure shown in fig. 1 is only an illustration, and does not limit the structure of the mobile terminal. For example, the mobile terminal may also include more or fewer components than shown in FIG. 1, or have a different configuration than shown in FIG. 1.
The memory 104 may be used to store computer programs, for example, software programs and modules of application software, such as computer programs corresponding to the data transmission method in the embodiment of the present invention, and the processor 102 executes various functional applications and data processing by running the computer programs stored in the memory 104, so as to implement the method described above. The memory 104 may include high speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include memory located remotely from the processor 102, which may be connected to the mobile terminal over a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The transmission device 106 is used to receive or transmit data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider of the mobile terminal. In one example, the transmission device 106 includes a Network adapter (NIC) that can be connected to other Network devices through a base station to communicate with the internet. In one example, the transmission device 106 may be a Radio Frequency (RF) module, which is used to communicate with the internet in a wireless manner.
In this embodiment, a data transmission method is provided, and fig. 2 is a first flowchart of the data transmission method according to the embodiment of the present invention, as shown in fig. 2, the flowchart includes the following steps:
step S202, under the condition that first data to be transmitted to a host computer exist in a slave computer, acquiring a data receiving state of a first Direct Memory Access (DMA) arranged in the slave computer;
step S204, under the condition that the data receiving state is determined to be a data unreceiving state, determining the current potential of a target pin preset between the host and the slave, wherein the current potential of the target pin is used for indicating the data transmission direction between the host and the slave, when the potential is a first potential, the data transmission direction is that the host reads the data in the slave, and when the potential is a second potential, the data transmission direction is that the host sends the data to the slave;
step S206, when it is determined that the current potential of the target pin is the second potential, adjusting the potential of the target pin to the first potential to instruct the host to read the first data in the slave.
In the above embodiment, the master and the slave may be respectively a processor, and the master and the slave may be connected by an SPI bus. As shown in fig. 3, four wires of MOSI, MISO, CLK, and CS are 4 wires necessary for SPI master-slave communication. Since the SPI is connected to the master and the slave, respectively, and the clock signal is provided by the master, the slave cannot actively transmit a signal to the master when only the MOSI, MISO, CLK, and CS lines are present. Therefore, a NOTIFY line is introduced on the basis of a standard 4-line SPI, and is used for enabling the host to provide a clock signal and enabling the host to be ready for receiving data before the slave sends data. For example, before the slave needs to send data, the NOTIFY pin is pulled high, at this time, the host provides a clock signal, after the slave finishes sending the data, the NOTIFY pin is pulled low, and the host stops generating the clock signal.
In the above embodiments, the first data may be data stored in a slave buffer, such as a memory. The target pin can be a NOTIFY pin, when first data to be transmitted to the host exist in the slave, the potential of the NOTIFY pin is determined, when the potential of the NOTIFY pin is the first potential, the host can read the first data in the slave, when the potential of the NOTIFY pin is the second potential and the first direct memory access DMA is in a data unreceiving state, the potential of the NOTIFY pin can be adjusted to the first potential, and when the host detects the first potential, the first data can be read. The first potential may be a high potential, and the second potential may be a low potential. Of course, the first potential may be a low potential and the second potential may be a high potential. The data transmission direction corresponding to the potential is not limited, that is, the host can read the first data of the slave when the potential of the NOTIFY pin is high, or read the first data of the slave when the potential of the NOTIFY pin is low.
It should be noted that the process of the master reading the data in the slave is actually the process of the slave sending the data to the master. When first data to be sent to the host exist in the slave, the slave can set the potential of the NOTIFY pin to be the first potential, and the host can read the first data when detecting the first potential, so that the effect of actively sending the data to the host is achieved. The clock signal is not required to be periodically provided by the host, so that the resource of a processor (such as a CPU) is saved.
In the above embodiment, the slave may be provided with a direct memory access DMA, and the DMA may be used to receive data sent by the host. And under the condition that the DMA is determined to be not receiving data and the buffer area of the slave computer comprises data to be sent to the host computer, when the potential of the target pin is the second potential, adjusting the potential of the target pin to be the first potential. That is, it is necessary to determine the data reception state of the DMA before adjusting the potential of the target pin to the first potential, and to keep the potential of the target pin unchanged when the DMA is in the data reception state, and to adjust the potential to the first potential when the DMA has finished receiving data. That is, the half-duplex mode is used to realize data transmission, and data is not transmitted when data is received. It should be noted that, when the host and the slave transmit data through the SPI, the actually used SPI is in a full-duplex mode in a hardware structure (the SPI itself supports the full-duplex mode and the half-duplex mode), and the half-duplex mode used here is a software half-duplex mode, that is, the two ends are prevented from transmitting data at the same time by the potential of the target pin, so that the software half-duplex mode is implemented.
According to the invention, under the condition that first data to be sent to a host computer exists in the slave computer, the data receiving state of a first direct memory access DMA arranged in the slave computer is obtained, under the condition that the data receiving state is determined to be a data unreceiving state, the current potential of a target pin preset between the host computer and the slave computer is determined, under the condition that the current potential of the target pin is determined to be a second potential, the current potential of the target pin is adjusted to be the first potential, and at the moment, the host computer can read the first data in the slave computer. When the current potential of the target pin is the second potential, the host can send data to the slave. When the first direct memory access DMA is in a data unreceived state and the potential of the target pin is the first potential, the host can read data in the slave, and data transmission can be realized based on the potential of the target pin without periodically generating a clock signal by the host. In addition, when the potential of the target pin is the first potential, the host can continuously read data in the slave, and when the potential of the target pin is the second potential, the host can continuously send data to the slave, so that the transmission of the data with indefinite length is realized. Therefore, the problems that processor resources are wasted and only fixed-length data can be transmitted due to the fact that data are sent from the slave to the host in the data transmission process in the related technology can be solved, and the effects of saving the processor resources and transmitting the data with indefinite length are achieved.
Optionally, the executing body of the above steps may be a slave.
In an exemplary embodiment, after adjusting the current potential of the target pin to the first potential, the method further includes: acquiring the state of the host for reading the first data; and under the condition that the host is determined to finish reading the first data, adjusting the current potential of the target pin to be the second potential. In this embodiment, when the current potential of the target pin is adjusted to the first potential, the host may read the first data, and when it is determined that the host has completed reading the data, the current potential of the target pin is adjusted to the second potential. When the data reading by the host is completed, the slave is considered to send the first data to the host. That is, when the potential of the target pin is the first potential, the host can read the data in the slave until the potential of the target pin becomes the second potential, so that the host can receive the indefinite length data. Referring to fig. 4, the flow chart of transmitting data from the slave to the master may be seen, because the slave is in a receiving state most of the time, the DMA for transmitting data needs to be reset before transmitting data, and whether the DMA is currently receiving data needs to be checked before setting, and if the DMA is currently receiving data, the DMA is not allowed to transmit, and whether the DMA is allowed to transmit needs to be determined again when the timer times out next time. The method of determining whether or not the DMA is in a reception state is to determine whether or not the amount of data received in the DMA is non-zero. After the slave sends the data, the slave needs to immediately switch back to the receiving state, that is, the potential of the target pin is adjusted to the second potential, so as to quickly prepare for receiving the data which can be sent by the host at any time. A timer is introduced to monitor the DMA, when the DMA is in a data receiving state, the potential of a target pin is kept unchanged, and the slave can be ensured to receive data all the time, namely the slave can complete the function of receiving the indefinite length data sent by the host without additional hardware. Fig. 5 is a waveform diagram of the slave sending data.
In an exemplary embodiment, after adjusting the current potential of the target pin to the second potential, the method further includes: utilizing the first direct memory access DMA to receive second data sent by the host and recording the receiving time of the second data; determining a first storage state of the first direct memory access DMA if the reception time exceeds a predetermined time; determining that receiving the second data is complete if it is determined that the first storage status indicates that the amount of data included in the first direct memory access is constant and greater than a predetermined threshold. In this embodiment, the slave may set the storage capacity of the first direct memory access DMA before receiving the second data sent by the host. Since the slave does not know the size of the data to be sent by the host, the storage capacity of the first direct memory access DMA needs to be set slightly larger as long as the data size is not smaller than the maximum one frame data size of the host (for example, 128 bytes, this value is only an exemplary illustration, and the storage capacity of the DMA is not limited by the present invention, for example, it may also be set to 64 bytes, 256 bytes, etc.). Also, because the slave does not know the size of the data volume to be sent by the master, therefore, the slave does not know when the master completes sending, in order to solve this problem, a timer may be introduced to detect the receiving state of the DMA, and as long as the data volume received by the DMA is maintained for a short period of time (corresponding to the predetermined time, for example, 5ms, this value is merely an exemplary illustration, the present invention does not limit the predetermined time, and a person skilled in the art may set the predetermined time according to the SPI communication rate of a specific application and the byte number customization of the transmission, for example, it may also take 3ms, 6ms, etc.) and is non-zero, the slave regards that the receiving is completed (here, the timer may also be a thread). Actually, some serial ports of the single chip microcomputer have an idle interrupt function and can receive indefinite data, while the SPI generally has no idle interrupt function, and the introduction of the timer is to realize similar functions in a software manner. It should be noted that the predetermined threshold may be set to 0, and may also be set to other values, and the predetermined threshold is not limited by the present invention. The flow chart of the data sent by the slave receiving host can be seen in fig. 6.
In this embodiment, a data transmission method is further provided, and fig. 7 is a second flowchart of the data transmission method according to the embodiment of the present invention, as shown in fig. 7, the flowchart includes the following steps:
step S702, detecting a current potential of a target pin preset between a host and a slave, wherein the current potential of the target pin is used for indicating a data transmission direction between the host and the slave, the data transmission direction is that the host reads data in the slave when the potential is a first potential, and the data transmission direction is that the host sends data to the slave when the potential is a second potential;
step S704, under the condition that the current potential of the target pin is determined to be the first potential, reading first data stored in the slave machine and to be transmitted to a host machine;
step S706, sending, to the slave, second data stored in the host to be transmitted to the slave, when it is determined that the current potential of the target pin is a second potential.
In the above embodiment, the master and the slave may be respectively a processor, and the master and the slave may be connected by an SPI bus. As shown in fig. 3, four wires of MOSI, MISO, CLK, and CS are 4 wires necessary for SPI master-slave communication. Since the SPI is connected to the master and the slave, respectively, and the clock signal is provided by the master, the slave cannot actively transmit a signal to the master when only the MOSI, MISO, CLK, and CS lines are present. Therefore, a NOTIFY line is introduced on the basis of a standard 4-line SPI, and is used for enabling the host to provide a clock signal and enabling the host to be ready for receiving data before the slave sends data. For example, before the slave needs to send data, the NOTIFY pin is pulled high, at this time, the host provides a clock signal, after the slave finishes sending the data, the NOTIFY pin is pulled low, and the host stops generating the clock signal.
In the above embodiments, the first data may be data stored in a slave buffer, such as a memory. The target pin can be a NOTIFY pin, when first data to be transmitted to the host exist in the slave, the potential of the NOTIFY pin is determined, when the potential of the NOTIFY pin is the first potential, the host can read the first data in the slave, when the potential of the NOTIFY pin is the second potential and the first direct memory access DMA is in a data unreceiving state, the potential of the NOTIFY pin can be adjusted to the first potential, and when the host detects the first potential, the first data can be read. The first potential may be a high potential, and the second potential may be a low potential. Of course, the first potential may be a low potential and the second potential may be a high potential. The data transmission direction corresponding to the potential is not limited, that is, the host can read the first data of the slave when the potential of the NOTIFY pin is high, or read the first data of the slave when the potential of the NOTIFY pin is low.
In the above embodiment, when the potential of the target pin is the second potential, the host may send the second data stored in the host to the slave, where the location where the second data is stored may be a buffer area, such as a memory area, in the host.
It should be noted that the process of the master reading the data in the slave is actually the process of the slave sending the data to the master. When first data to be sent to the host exist in the slave, the slave can set the potential of the NOTIFY pin to be the first potential, and the host can read the first data when detecting the first potential, so that the effect of actively sending the data to the host is achieved. The clock signal is not required to be periodically provided by the host, so that the resource of a processor (such as a CPU) is saved.
In the above embodiment, the slave may be provided with a direct memory access DMA, and the DMA may be used to receive data sent by the host. And under the condition that the DMA is determined to be not receiving data and the buffer area of the slave computer comprises data to be sent to the host computer, when the potential of the target pin is the second potential, adjusting the potential of the target pin to be the first potential. That is, it is necessary to determine the data reception state of the DMA before adjusting the potential of the target pin to the first potential, and to keep the potential of the target pin unchanged when the DMA is in the data reception state, and to adjust the potential to the first potential when the DMA has finished receiving data. That is, the half-duplex mode is used to realize data transmission, and data is not transmitted when data is received. It should be noted that, when the host and the slave transmit data through the SPI, the actually used SPI is in a full-duplex mode in a hardware structure (the SPI itself supports the full-duplex mode and the half-duplex mode), and the half-duplex mode used here is a software half-duplex mode, that is, the two ends are prevented from transmitting data at the same time by the potential of the target pin, so that the software half-duplex mode is implemented.
According to the invention, the current potential of the target pin preset between the host and the slave is detected, the first data to be transmitted to the host stored in the slave is read under the condition that the current potential of the target pin is determined to be the first potential, the second data to be transmitted to the slave stored in the host is sent to the slave under the condition that the current potential of the target pin is determined to be the second potential, and the host can read the first data in the slave without periodically generating a clock signal when the target pin is the first potential due to the fact that different potentials indicate different data transmission directions. In addition, when the potential of the target pin is the first potential, the host can continuously read data in the slave, and when the potential of the target pin is the second potential, the host can continuously send data to the slave, so that the transmission of the data with indefinite length is realized. Therefore, the problems that in the data communication data transmission process in the related technology, the slave machine cannot actively send data to the host machine, processor resources are wasted, and only fixed-length data can be transmitted can be solved, and the effects that the slave machine can actively send data to the host machine, the host machine does not need to periodically provide clock signals, the processor resources are saved, and the data with indefinite length are transmitted are achieved.
Illustratively, the main body of execution of the above steps may be a host.
In an exemplary embodiment, in the case that it is determined that the current potential of the target pin is the first potential, reading first data stored in a slave to be transmitted to a host includes: generating a clock signal under the condition that the current potential of the target pin is determined to be a first potential; reading the first data if the clock signal reaches a target state. In this embodiment, when the current potential of the host transmission target pin is the first potential, the host generates a clock signal to provide the clock signal, wherein the clock signal may be a clock signal with a certain period. After the host provides the clock signal, the first data in the slave can be read, and the effect of sending the first data from the slave to the host is achieved. For example, when the first potential is high, the host actively reads the data of the slave until the NOTIFY pin is low when the host finds that the potential of the NOTIFY pin is high. The master actively reads the slave data in order to provide a clock signal to the slave. The flow chart of the host receiving the data sent by the slave can be seen in fig. 8, as shown in fig. 8, when the slave sends data, it is actually the host that reads 1 byte of data in the slave. It should be noted that the number of bytes read by the host at a time depends on the specific application, and the invention is not limited thereto. For example, the host may also read 4 bytes each time, and since the host reads 4 bytes each time when sending from the slave, it may read 3 more bytes, which is the case in fig. 5. The slave pulls down the NOTIFY pin immediately after the completion of the transmission, so that the waveform shown in fig. 5 appears, that is, 3 bytes of data are also transmitted from the slave after the NOTIFY.
In one exemplary embodiment, after reading the first data to be transmitted to the master stored in the slave, the method further comprises: and storing the first data into a direct memory arranged in the host by utilizing a second Direct Memory Access (DMA). In this embodiment, the host may store the received first data in direct memory using a second direct memory access DMA, which may specify a data source and a data deposit point (direct memory), that handles data from the data source to the data deposit point (direct memory, e.g., memory).
In one exemplary embodiment, sending the second data stored in the master to be transmitted to the slave comprises: sending the second data to the slave; discarding third data transmitted by the slave received during transmission of the second data. In this embodiment, the flow chart of the host sending data to the slave when the second potential is the low potential can be seen in fig. 9, as shown in fig. 8, the host needs to determine whether the NOTIFY pin is the low potential before sending, and if the pin is the low potential, it means that the slave has no data to send. At this time, the host can directly send data; if the NOTIFY pin is at a high level, it indicates that the slave is about to send data at this time, and it is necessary to receive the slave data first and then determine the NOTIFY signal again to determine whether the sending operation can be performed. That is, a half-duplex mode is adopted, and software controls both the master and the slave to send valid data at the same time by only one party. Because in the half-duplex mode, only one side is sending data and the other side is receiving data at a certain time, the DMA size of the sending side is known, and the data received by the sending side can be directly discarded. It should be noted that, when the host and the slave transmit data through the SPI, the actually used SPI is in a full-duplex mode in a hardware structure (the SPI itself supports the full-duplex mode and the half-duplex mode), and the half-duplex mode used here is a software half-duplex mode, that is, the two ends are prevented from transmitting data at the same time by the potential of the target pin, so that the software half-duplex mode is implemented. The waveform diagram of the host sending data can be seen in fig. 10.
In the embodiment, the slave machine active notification host machine mechanism is used, so that the function that the SPI slave machine can actively send data to the host machine is realized, the host machine does not need to periodically generate clock signals, CPU resources are saved, the clock signals can be immediately provided when the slave machine needs to send data, and the real-time performance is strong. A timer is introduced to monitor DMA. The DMA receiving state of the slave is monitored at regular time by using a timer or a thread, and the slave can complete the function of receiving indefinite-length data sent by the host without additional hardware. The problem of DMA sending size setting is solved by using a software half-duplex mechanism, and a sending anti-collision mechanism is introduced to avoid the situation that a master machine and a slave machine send simultaneously: the host monitors the state of the NOTIFY pin, and the slave monitors the DMA receiving state. In addition, the host and the slave can actively transmit data, and the use is more flexible. Under the condition that resources such as serial ports and the like are scarce, the communication between the embedded processors can be finished by using the SPI. In addition, the host and the slave both use DMA, thereby greatly improving the actual communication rate of the SPI and lightening the load of the CPU.
Through the above description of the embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but the former is a better implementation mode in many cases. Based on such understanding, the technical solutions of the present invention may be embodied in the form of a software product, which is stored in a storage medium (e.g., ROM/RAM, magnetic disk, optical disk) and includes instructions for enabling a terminal device (e.g., a mobile phone, a computer, a server, or a network device) to execute the method according to the embodiments of the present invention.
In this embodiment, a data transmission device is further provided, and the data transmission device is used to implement the foregoing embodiments and preferred embodiments, which have already been described and are not described again. As used below, the term "module" may be a combination of software and/or hardware that implements a predetermined function. Although the means described in the embodiments below are preferably implemented in software, an implementation in hardware, or a combination of software and hardware is also possible and contemplated.
Fig. 11 is a block diagram of a first structure of a data transmission device according to an embodiment of the present invention, as shown in fig. 11, the device includes:
an obtaining module 1102, configured to obtain a data receiving state of a first direct memory access DMA set in a slave when it is determined that first data to be transmitted to a host exists in the slave;
a determining module 1104, configured to determine a current potential of a target pin preset between the host and the slave when it is determined that the data receiving state is a data unreceived state, where the current potential of the target pin is used to indicate a data transmission direction between the host and the slave, the data transmission direction is that the host reads data in the slave when the potential is a first potential, and the data transmission direction is that the host sends data to the slave when the potential is a second potential;
an adjusting module 1106, configured to adjust the potential of the target pin to a first potential to instruct the host to read the first data in the slave if it is determined that the current potential of the target pin is a second potential.
In an exemplary embodiment, the apparatus may be configured to obtain a state that the host reads the first data after adjusting a current potential of the target pin to a first potential; and under the condition that the host is determined to finish reading the first data, adjusting the current potential of the target pin to be the second potential.
In an exemplary embodiment, the apparatus is further configured to receive second data sent by the host by using the first direct memory access DMA after adjusting the current potential of the target pin to the second potential, and record a receiving time of receiving the second data; determining a first storage state of the first direct memory access DMA if the reception time exceeds a predetermined time; determining that receiving the second data is complete if it is determined that the first storage status indicates that the amount of data included in the first direct memory access is constant and greater than a predetermined threshold.
Fig. 12 is a block diagram of a second structure of a data transmission device according to an embodiment of the present invention, and as shown in fig. 12, the device includes:
a detection module 1202, configured to detect a current potential of a target pin preset between a host and a slave, where the current potential of the target pin is used to indicate a data transmission direction between the host and the slave, and when the potential is a first potential, the data transmission direction is that the host reads data in the slave, and when the potential is a second potential, the data transmission direction is that the host sends data to the slave;
a reading module 1204, configured to read, when it is determined that the current potential of the target pin is a first potential, first data stored in the slave to be transmitted to the host;
a sending module 1206, configured to send, to the slave, second data stored in the host to be transmitted to the slave when it is determined that the current potential of the target pin is a second potential.
In an exemplary embodiment, the reading module 1204 may be configured to read first data stored in a slave to be transmitted to a host if it is determined that the current potential of the target pin is the first potential: generating a clock signal under the condition that the current potential of the target pin is determined to be a first potential; reading the first data if the clock signal reaches a target state.
In an exemplary embodiment, the apparatus may be further configured to store first data stored in a slave to be transmitted to a host in a direct memory in the host using a second direct memory access DMA after reading the first data.
In an exemplary embodiment, the sending module 1206 may implement sending, to the slave, the second data stored in the master to be transmitted to the slave, by: sending the second data to the slave; discarding third data transmitted by the slave received during transmission of the second data.
The embodiment of the invention also provides a data transmission system, which comprises the host, the slave and the target pin in any embodiment, wherein the host and the slave are connected through the target pin.
It should be noted that, the above modules may be implemented by software or hardware, and for the latter, the following may be implemented, but not limited to: the modules are all positioned in the same processor; alternatively, the modules are respectively located in different processors in any combination.
Embodiments of the present invention also provide a computer-readable storage medium having a computer program stored thereon, wherein the computer program is arranged to perform the steps of any of the above-mentioned method embodiments when executed.
In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to: various media capable of storing computer programs, such as a usb disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic disk, or an optical disk.
Embodiments of the present invention also provide an electronic device comprising a memory having a computer program stored therein and a processor arranged to run the computer program to perform the steps of any of the above method embodiments.
In an exemplary embodiment, the electronic apparatus may further include a transmission device and an input/output device, wherein the transmission device is connected to the processor, and the input/output device is connected to the processor.
For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary embodiments, and details of this embodiment are not repeated herein.
It will be apparent to those skilled in the art that the various modules or steps of the invention described above may be implemented using a general purpose computing device, they may be centralized on a single computing device or distributed across a network of computing devices, and they may be implemented using program code executable by the computing devices, such that they may be stored in a memory device and executed by the computing device, and in some cases, the steps shown or described may be performed in an order different than that described herein, or they may be separately fabricated into various integrated circuit modules, or multiple ones of them may be fabricated into a single integrated circuit module. Thus, the present invention is not limited to any specific combination of hardware and software.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the principle of the present invention should be included in the protection scope of the present invention.
Claims (12)
1. A method of data transmission, comprising:
acquiring a data receiving state of a first Direct Memory Access (DMA) arranged in a slave;
under the condition that the data receiving state is determined to be a data unreceiving state, determining the current potential of a target pin preset between a host and a slave, wherein the current potential of the target pin is used for indicating the data transmission direction between the host and the slave, when the potential is a first potential, the data transmission direction is that the host reads data in the slave, and when the potential is a second potential, the data transmission direction is that the host sends data to the slave;
and under the condition that the current potential of the target pin is determined to be a second potential, adjusting the current potential of the target pin to be a first potential so as to instruct the host to read first data in the slave.
2. The method of claim 1, wherein after adjusting the current potential of the target pin to the first potential, the method further comprises:
acquiring the state of the host for reading the first data;
adjusting the potential of the target pin to the second potential if it is determined that the host reading the first data is complete.
3. The method of claim 2, wherein after adjusting the current potential of the target pin to the second potential, the method further comprises:
utilizing the first direct memory access DMA to receive second data sent by the host and recording the receiving time of the second data;
determining a first storage state of the first direct memory access in a case where the reception time exceeds a predetermined time;
determining that reception of the second data is completed, in a case where it is determined that the first storage state indicates that the amount of data included in the first direct memory access DMA is constant and greater than a predetermined threshold.
4. A method of data transmission, comprising:
detecting the current potential of a target pin preset between a host and a slave, wherein the current potential of the target pin is used for indicating the data transmission direction between the host and the slave, when the potential is a first potential, the data transmission direction is that the host reads data in the slave, and when the potential is a second potential, the data transmission direction is that the host sends data to the slave;
under the condition that the current potential of the target pin is determined to be a first potential, reading first data stored in the slave machine and to be transmitted to a host machine;
and sending second data stored in the host machine and to be transmitted to the slave machine under the condition that the current potential of the target pin is determined to be a second potential.
5. The method according to claim 4, wherein in the case that the current potential of the target pin is determined to be the first potential, reading first data stored in a slave to be transmitted to a host comprises:
generating a clock signal under the condition that the current potential of the target pin is determined to be a first potential;
reading the first data if the clock signal reaches a target state.
6. The method of claim 4, wherein after reading the first data stored in the slave to be transmitted to the master, the method further comprises:
storing the first data in a direct memory in the host using a second Direct Memory Access (DMA).
7. The method of claim 4, wherein sending second data stored in the master to the slave for transmission to the slave comprises:
sending the second data to the slave;
discarding third data transmitted by the slave received during transmission of the second data.
8. A data transmission apparatus, comprising:
the device comprises an acquisition module, a processing module and a processing module, wherein the acquisition module is used for acquiring a data receiving state of a first Direct Memory Access (DMA) arranged in a slave under the condition that first data to be transmitted to a host exist in the slave;
the determining module is configured to determine a current potential of a target pin preset between the host and the slave when the data receiving state is determined to be a data unreceived state, where the current potential of the target pin is used to indicate a data transmission direction between the host and the slave, the data transmission direction is that the host reads data in the slave when the potential is a first potential, and the data transmission direction is that the host sends data to the slave when the potential is a second potential;
and the adjusting module is used for adjusting the current potential of the target pin to be a first potential under the condition that the potential of the target pin is determined to be a second potential so as to instruct the host to read the first data in the slave.
9. A data transmission apparatus, comprising:
the detection module is used for detecting the current potential of a target pin preset between a host and a slave, wherein the current potential of the target pin is used for indicating the data transmission direction between the host and the slave, the data transmission direction is that the host reads data in the slave when the potential is a first potential, and the data transmission direction is that the host sends data to the slave when the potential is a second potential;
the reading module is used for reading first data stored in the slave machine and to be transmitted to the host machine under the condition that the current potential of the target pin is determined to be a first potential;
and the sending module is used for sending second data stored in the host machine and to be transmitted to the slave machine under the condition that the current potential of the target pin is determined to be a second potential.
10. A data transmission system comprising a master, a slave and a target pin according to any one of claims 1 to 9, wherein the master and the slave are connected via the target pin.
11. A computer-readable storage medium, in which a computer program is stored, wherein the computer program is arranged to perform the method of any of claims 1 to 3 when executed, or to perform the method of any of claims 4 to 7.
12. An electronic device comprising a memory and a processor, wherein the memory has stored therein a computer program, and wherein the processor is arranged to execute the computer program to perform the method of any of claims 1 to 3, or to perform the method of any of claims 4 to 7.
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Application publication date: 20210827 |