CN113312274B

CN113312274B - Data sorting method of memory, memory storage device and control circuit unit

Info

Publication number: CN113312274B
Application number: CN202010125393.4A
Authority: CN
Inventors: 陈国荣
Original assignee: Phison Electronics Corp
Current assignee: Phison Electronics Corp
Priority date: 2020-02-27
Filing date: 2020-02-27
Publication date: 2024-03-22
Anticipated expiration: 2040-02-27
Also published as: CN113312274A

Abstract

The invention provides a data sorting method of a memory, a memory storage device and a memory control circuit unit, which are used for the memory storage device comprising a rewritable nonvolatile memory module. The data sorting method of the memory comprises the following steps: receiving an instruction from a host system, wherein the instruction includes a data interval; calculating data scattering degree according to the logic estimated values of a plurality of logic block addresses of the data interval and the entity estimated values of a plurality of entity erasing units mapped by the logic block addresses; and judging whether to execute data sorting operation according to the data scattering degree and the threshold value so as to move the data in the entity erasing unit according to the logical block address.

Description

Data sorting method of memory, memory storage device and control circuit unit

Technical Field

The present invention relates to memory data sorting technology, and more particularly, to a memory data sorting method, a memory storage device, and a memory control circuit unit.

Background

Digital cameras, mobile phones and MP3 players have grown very rapidly over the years, such that consumer demand for storage media has also increased rapidly. Since a rewritable non-volatile memory module (e.g., flash memory) has characteristics of non-volatility of data, power saving, small size, and no mechanical structure, it is very suitable for being built in the above-exemplified various portable multimedia devices.

However, if the write data from the host system belongs to discontinuous data, for example, the write data belongs to discontinuous logic sub-units, the logic sub-units in one logic unit may be mapped to physical program units of different physical erase units. In this case, when the host system wants to read the data belonging to the logical sub-units corresponding to the consecutive addresses in one logical unit, the controller may need to load different logical-to-physical mapping tables to find out the physical program units scattered in different physical erase units. Then, the controller needs to send a plurality of read instructions to read the data from the scattered physical programming units, so that a relatively long time is spent for performing the read operation, and the data reading speed is reduced.

Disclosure of Invention

The invention provides a data sorting method of a memory, a memory storage device and a memory control circuit unit, which can judge whether data sorting operation is needed.

Embodiments of the present invention provide a data sort method for a memory storage device including a rewritable nonvolatile memory module. The data sorting method of the memory comprises the following steps: receiving an instruction from a host system, wherein the instruction includes a data interval; calculating data scattering degree according to the logic estimated values of a plurality of logic block addresses of the data interval and the entity estimated values of a plurality of entity erasing units mapped by the logic block addresses; and judging whether to execute data sorting operation according to the data scattering degree and the threshold value so as to move the data in the entity erasing unit according to the logic block address.

In one embodiment of the invention, the instruction comprises a fragment reorganization instruction.

In an embodiment of the present invention, the step of calculating the data divergence according to the logical estimation value of the logical block address of the data interval and the physical estimation value of the physical erasure unit mapped by the logical block address includes: calculating the logic estimation value according to the number of the logic block addresses of the data interval, the capacity of the logic block addresses and the physical page capacity of the rewritable nonvolatile memory module; determining the entity estimation value according to the entity page number in the entity erasing unit mapped by the logic block address; and calculating the ratio of the logic estimation value to the entity estimation value to determine the data divergence.

In an embodiment of the present invention, the step of calculating the logical estimation value according to the number of the logical block addresses, the capacity of the logical block addresses and the physical page capacity of the rewritable nonvolatile memory module of the data section includes: calculating the data capacity of the data interval according to the number of the logic block addresses and the capacity of the logic block addresses; and calculating the logic estimation value according to the data capacity and the entity page capacity of the rewritable nonvolatile memory module.

In an embodiment of the present invention, the step of determining whether to perform the data sort operation according to the data scattering degree and the threshold value to move the data in the physical erase unit according to the logical block address includes: and executing the data sorting operation according to the logic block address when the data divergence is not greater than a first threshold value.

In an embodiment of the present invention, the step of calculating the data divergence according to the logical estimation value of the logical block address of the data interval and the physical estimation value of the physical erasure unit mapped by the logical block address includes: determining the logic estimation value according to the number of the logic pages corresponding to the logic block addresses in the data interval; determining the entity estimation value according to the number of entity planes corresponding to the entity erasure unit mapped by the logical block address; and calculating the data divergence according to the logic estimation value and the entity estimation value.

In an embodiment of the present invention, the step of determining whether to perform the data sort operation according to the data scattering degree and the threshold value to move the data in the physical erase unit according to the logical block address includes: calculating a second threshold according to the data divergence and a third threshold; and executing the data sorting operation according to the logical block address when the number of pages configured in one entity plane corresponding to the entity erasing unit mapped by the logical block address is not smaller than the second threshold value.

The invention provides a memory storage device, which comprises a connection interface unit, a rewritable nonvolatile memory module and a memory control circuit unit. The connection interface unit is used for being coupled to a host system. The memory control circuit unit is coupled to the connection interface unit and the rewritable nonvolatile memory module. The memory control circuit unit is configured to receive an instruction from the host system, wherein the instruction includes a data interval. The memory control circuit unit is also used for calculating data scattering degree according to the logic estimated values of the plurality of logic block addresses of the data interval and the entity estimated values of the plurality of entity erasing units mapped by the logic block addresses. And the memory control circuit unit is also used for judging whether to execute data sorting operation according to the data scattering degree and the threshold value so as to move the data in the entity erasing unit according to the logic block address.

In an embodiment of the present invention, the operation of the memory control circuit unit further for calculating the data scattering degree according to the logical estimation value of the logical block address of the data interval and the physical estimation value of the physical erasure unit mapped by the logical block address includes: calculating the logic estimation value according to the number of the logic block addresses of the data interval, the capacity of the logic block addresses and the physical page capacity of the rewritable nonvolatile memory module; determining the entity estimation value according to the entity page number in the entity erasing unit mapped by the logic block address; and calculating the ratio of the logic estimation value to the entity estimation value to determine the data divergence.

In an embodiment of the present invention, the operation of calculating the logical estimation value according to the number of the logical block addresses, the capacity of the logical block addresses and the physical page capacity of the rewritable nonvolatile memory module of the data section includes: calculating the data capacity of the data interval according to the number of the logic block addresses and the capacity of the logic block addresses; and calculating the logic estimation value according to the data capacity and the entity page capacity of the rewritable nonvolatile memory module.

In an embodiment of the present invention, the memory control circuit unit further determines whether to perform the data sort operation according to the data scattering degree and the threshold value, so as to move the data in the physical erasing unit according to the logical block address, including: and executing the data sorting operation according to the logic block address when the data divergence is not greater than a first threshold value.

In an embodiment of the present invention, the operation of the memory control circuit unit further for calculating the data scattering degree according to the logical estimation value of the logical block address of the data interval and the physical estimation value of the physical erasure unit mapped by the logical block address includes: determining the logic estimation value according to the number of the logic pages corresponding to the logic block addresses in the data interval; determining the entity estimation value according to the number of entity planes corresponding to the entity erasure unit mapped by the logical block address; and calculating the data divergence according to the logic estimation value and the entity estimation value.

In an embodiment of the present invention, the memory control circuit unit further determines whether to perform the data sort operation according to the data scattering degree and the threshold value, so as to move the data in the physical erasing unit according to the logical block address, including: calculating a second threshold according to the data divergence and a third threshold; and executing the data sorting operation according to the logical block address when the number of pages configured in one entity plane corresponding to the entity erasing unit mapped by the logical block address is not smaller than the second threshold value.

The invention provides a memory control circuit unit which is used for controlling a memory storage device comprising a rewritable nonvolatile memory module and comprises a host interface, a memory interface and a memory management circuit. The host interface is configured to be coupled to a host system. The memory interface is configured to be coupled to the rewritable non-volatile memory module. The memory management circuit is coupled to the host interface and the memory interface. The memory control circuit unit is configured to receive an instruction from the host system, wherein the instruction includes a data interval. The memory control circuit unit is also used for calculating data scattering degree according to the logic estimated values of the plurality of logic block addresses of the data interval and the entity estimated values of the plurality of entity erasing units mapped by the logic block addresses. And the memory control circuit unit is also used for judging whether to execute data sorting operation according to the data scattering degree and the threshold value so as to move the data in the entity erasing unit according to the logic block address.

Based on the above, the data sorting method, the memory storage device and the memory control circuit unit of the memory according to the embodiments of the present invention can calculate the data scattering degree according to the logic estimation values of the plurality of logic block addresses of the data interval included in the instruction and the entity estimation values of the plurality of entity erasure units mapped by the logic block addresses, and compare the data scattering degree with the threshold value to determine whether the data is concentrated or scattered. Therefore, whether the data interval needs to be subjected to data arrangement operation or not can be determined, and the speed of reading data is further improved.

Drawings

FIG. 1 is a schematic diagram of a host system, memory storage device, and input/output (I/O) device shown in accordance with an example embodiment;

FIG. 2 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device shown in accordance with another example embodiment;

FIG. 3 is a schematic diagram of a host system and a memory storage device according to another example embodiment;

FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention;

FIG. 5 is a schematic block diagram of a memory control circuit unit according to an example embodiment of the invention;

FIGS. 6 and 7 are schematic diagrams illustrating exemplary management entity blocks according to an exemplary embodiment of the present invention;

FIG. 8 is a flowchart of a method of data sort of a memory according to an example embodiment of the present invention;

FIG. 9 is a flowchart of a method of sorting data of a memory according to an example embodiment of the invention;

fig. 10 is a flowchart illustrating a data sort method of a memory according to an exemplary embodiment of the present invention.

Description of the reference numerals

10. 30: memory storage device

11. 31: host system

110: system bus

111: processor and method for controlling the same

112: random access memory

113: read-only memory

114: data transmission interface

12: input/output (I/O) device

20: motherboard

201: USB flash disk

202: memory card

203: solid state disk

204: wireless memory storage device

205: global positioning system module

206: network interface card

207: wireless transmission device

208: keyboard with keyboard body

209: screen panel

210: horn with horn body

32: SD card

33: CF card

34: embedded memory device

341: embedded multimedia card

342: embedded multi-chip packaging storage device

402: connection interface unit

404: memory control circuit unit

406: rewritable nonvolatile memory module

410 (0) to 410 (N): physical erasing unit

502: memory management circuit

504: host interface

506: memory interface

508: error checking and correcting circuit

510: buffer memory

512: power management circuit

602: data area

604: idle zone

606: system area

608: substitution region

LBA (0) to LBA (H): logical block address

LZ (0) to LZ (M): logic area

S802 to S806, S902 to S912, S1002 to S1014: and (3) step (c).

Detailed Description

Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable nonvolatile memory module and a controller (also referred to as a control circuit unit). Memory storage devices are typically used with host systems so that the host system can write data to or read data from the memory storage device.

FIG. 1 is a schematic diagram of a host system, memory storage device, and input/output (I/O) device, according to an example embodiment. And FIG. 2 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to another example embodiment.

Referring to fig. 1 and 2, the host system 11 generally includes a processor 111, a random access memory (random access memory, RAM) 112, a Read Only Memory (ROM) 113, and a data transfer interface 114. The processor 111, the random access memory 112, the read only memory 113, and the data transfer interface 114 are all coupled to a system bus 110.

In the present exemplary embodiment, host system 11 is coupled to memory storage device 10 via data transfer interface 114. For example, host system 11 may write data to memory storage device 10 or read data from memory storage device 10 via data transfer interface 114. In addition, host system 11 is coupled to I/O device 12 via system bus 110. For example, host system 11 may transmit output signals to I/O device 12 or receive input signals from I/O device 12 via system bus 110.

In the present exemplary embodiment, the processor 111, the ram 112, the rom 113 and the data transmission interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. The motherboard 20 may be coupled to the memory storage device 10 via a wired or wireless connection via the data transmission interface 114. The memory storage device 10 may be, for example, a usb flash disk 201, a memory card 202, a solid state disk (Solid State Drive, SSD) 203, or a wireless memory storage device 204. The wireless memory storage 204 may be, for example, a near field wireless communication (Near Field Communication Storage, NFC) memory storage, a wireless facsimile (WiFi) memory storage, a Bluetooth (Bluetooth) memory storage, or a Bluetooth low energy memory storage (such as iBeacon) or the like based on a variety of wireless communication technologies. In addition, the motherboard 20 may also be coupled to various I/O devices such as a global positioning system (Global Positioning System, GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, a speaker 210, etc. through the system bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 through the wireless transmission device 207.

In an example embodiment, the host system referred to is any system that can cooperate with substantially a memory storage device to store data. Although the host system is described in the above exemplary embodiment as a computer system, FIG. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment. Referring to fig. 3, in another exemplary embodiment, the host system 31 may be a system such as a digital camera, a video camera, a communication device, an audio player, a video player or a tablet computer, and the memory storage device 30 may be a variety of nonvolatile memory storage devices such as an SD card 32, a CF card 33 or an embedded storage device 34. The embedded storage device 34 includes embedded storage devices of various types such as an embedded multimedia card (eMMC) 341 and/or an embedded multi-chip package (embedded Multi Chip Package, eMCP) storage device 342, which directly couples the memory module to a substrate of the host system.

FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention. Referring to fig. 4, the memory storage device 10 includes a connection interface unit 402, a memory control circuit unit 404, and a rewritable nonvolatile memory module 406.

The connection interface unit 402 is used to couple the memory storage device 10 to the host system 11. The memory storage device 10 may communicate with the host system 11 through the connection interface unit 402. In the present exemplary embodiment, the connection interface unit 402 is compatible with the serial advanced technology attachment (Serial Advanced Technology Attachment, SATA) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 402 may also be a standard compliant with a parallel advanced technology attachment (Parallel Advanced Technology Attachment, PATA) standard, an institute of electrical and electronics engineers (Institute of Electrical and Electronic Engineers, IEEE) 1394 standard, a High-Speed peripheral component interconnect (Peripheral Component Interconnect Express, PCI Express) standard, a universal serial bus (Universal Serial Bus, USB) standard, an SD interface standard, a Ultra High Speed-I (UHS-I) interface standard, a Ultra High Speed-II (UHS-II) interface standard, a Memory Stick (MS) interface standard, an MCP interface standard, an MMC interface standard, an eMMC interface standard, a universal flash Memory (Universal Flash Storage, s) interface standard, an ehcp interface standard, a CF interface standard, an integrated drive electronics interface (Integrated Device Electronics, IDE) standard, or other suitable standard. The connection interface unit 402 may be packaged with the memory control circuit unit 404 in a single chip, or the connection interface unit 402 may be disposed off-chip with the memory control circuit unit 404.

The memory control circuit unit 404 is configured to execute a plurality of logic gates or control instructions implemented in hardware or firmware and perform operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 406 according to the instructions of the host system 11.

The rewritable nonvolatile memory module 406 is coupled to the memory control circuit unit 404 and is used for storing data written by the host system 11. The rewritable nonvolatile memory module 406 may be a single-Level memory Cell (Single Level Cell, SLC) NAND type flash memory module (i.e., a flash memory module that can store 1 bit in one memory Cell), a Multi-Level memory Cell (MLC) NAND type flash memory module (i.e., a flash memory module that can store 2 bits in one memory Cell), a third-Level memory Cell (Triple Level Cell, TLC) NAND type flash memory module (i.e., a flash memory module that can store 3 bits in one memory Cell), a Quad-Level memory Cell (QLC) NAND type flash memory module (i.e., a flash memory module that can store 4 bits in one memory Cell), other flash memory modules, or other memory modules having the same characteristics.

Each memory cell in the rewritable nonvolatile memory module 406 stores one or more bits with a change in voltage (hereinafter also referred to as a threshold voltage). Specifically, there is a charge trapping layer between the control gate (control gate) and the channel of each memory cell. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data to the memory cell" or "programming" the memory cell. As the threshold voltage changes, each memory cell in the rewritable nonvolatile memory module 406 has multiple memory states. By applying the read voltage, it can be determined which memory state a memory cell belongs to, thereby obtaining one or more bits stored in the memory cell.

In the present exemplary embodiment, the memory cells of the rewritable nonvolatile memory module 406 may constitute a plurality of physical program cells, and the physical program cells may constitute a plurality of physical erase cells. Specifically, memory cells on the same word line may constitute one or more physical programming units. If each memory cell can store more than 2 bits, the physical programming units on the same word line can be categorized into at least a lower physical programming unit and an upper physical programming unit. For example, the least significant bit (Least Significant Bit, LSB) of a memory cell is that belonging to the lower physical programming cell, and the most significant bit (Most Significant Bit, MSB) of a memory cell is that belonging to the upper physical programming cell. In general, in MLC NAND-type flash memory, the writing speed of the lower physical programming unit is greater than the writing speed of the upper physical programming unit, and/or the reliability of the lower physical programming unit is higher than the reliability of the upper physical programming unit.

In the present exemplary embodiment, the physical programming unit is the minimum unit of programming. That is, the physical programming unit is the smallest unit of write data. For example, the physical programming unit may be a physical page (page) or a physical sector (sector). If the physical programming units are physical pages, the physical programming units may include data bits and redundancy bits. The data bit area includes a plurality of physical sectors for storing user data, and the redundant bit area is used for storing system data (e.g., management data such as error correction codes). In the present exemplary embodiment, the data bit area includes 32 physical sectors, and the size of one physical sector is 512 bytes (B). However, in other exemplary embodiments, 8, 16 or a greater or lesser number of physical fans may be included in the data bit zone, and the size of each physical fan may be greater or lesser. On the other hand, a physical erase unit is the minimum unit of erase. That is, each physically erased cell contains a minimum number of memory cells that are erased. For example, the physical erased cells are physical blocks (blocks).

FIG. 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention. Referring to fig. 5, the memory control circuit unit 404 includes a memory management circuit 502, a host interface 504 and a memory interface 506.

The memory management circuit 502 is used to control the overall operation of the memory control circuit unit 404. Specifically, the memory management circuit 502 has a plurality of control commands, and the control commands are executed to perform writing, reading and erasing operations of data while the memory storage device 10 is operating. The operation of the memory management circuit 502 is described as follows, which is equivalent to the description of the operation of the memory control circuit unit 404.

In the present exemplary embodiment, the control instructions of the memory management circuit 502 are implemented in firmware. For example, the memory management circuit 502 has a microprocessor unit (not shown) and a read-only memory (not shown), and the control instructions are burned into the read-only memory. When the memory storage device 10 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading and erasing data.

In another example embodiment, the control instructions of the memory management circuitry 502 may also be stored in code form in a specific area of the rewritable non-volatile memory module 406 (e.g., a system area of the memory module dedicated to storing system data). In addition, the memory management circuit 502 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the ROM has a boot code (boot code), and when the memory control circuit 404 is enabled, the microprocessor unit executes the boot code to load the control instructions stored in the rewritable nonvolatile memory module 406 into the RAM of the memory management circuit 502. Then, the microprocessor unit operates the control instructions to perform operations such as writing, reading and erasing of data.

Furthermore, in another example embodiment, the control instructions of the memory management circuit 502 may also be implemented in a hardware type. For example, the memory management circuit 502 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, the memory write circuit, the memory read circuit, the memory erase circuit and the data processing circuit are coupled to the microcontroller. The memory cell management circuit is used to manage memory cells or groups of memory cells of the rewritable nonvolatile memory module 406. The memory write circuit is configured to issue a write command sequence to the rewritable nonvolatile memory module 406 to write data into the rewritable nonvolatile memory module 406. The memory read circuit is configured to issue a read instruction sequence to the rewritable nonvolatile memory module 406 to read data from the rewritable nonvolatile memory module 406. The memory erase circuit is configured to issue an erase command sequence to the rewritable nonvolatile memory module 406 to erase data from the rewritable nonvolatile memory module 406. The data processing circuit is used for processing data to be written into the rewritable nonvolatile memory module 406 and data read from the rewritable nonvolatile memory module 406. The write command sequence, read command sequence, and erase command sequence may each include one or more codes or command codes and are used to instruct the rewritable nonvolatile memory module 406 to perform corresponding writing, reading, and erasing operations. In an example embodiment, the memory management circuitry 502 may also issue other types of sequences of instructions to the rewritable non-volatile memory module 406 to instruct the corresponding operations to be performed.

The host interface 504 is coupled to the memory management circuitry 502. The memory management circuitry 502 may communicate with the host system 11 through a host interface 504. The host interface 504 is used to receive and identify instructions and data transmitted by the host system 11. For example, instructions and data transferred by host system 11 may be transferred to memory management circuitry 502 via host interface 504. In addition, the memory management circuitry 502 may communicate data to the host system 11 through the host interface 504. In the present exemplary embodiment, host interface 504 is compliant with the SATA standard. However, it should be understood that the present invention is not limited thereto, and the host interface 504 may also be compatible with PATA standards, IEEE 1394 standards, PCI Express standards, USB standards, SD standards, UHS-I standards, UHS-II standards, MS standards, MMC standards, eMMC standards, UFS standards, CF standards, IDE standards, or other suitable data transfer standards.

The memory interface 506 is coupled to the memory management circuit 502 and is used to access the rewritable nonvolatile memory module 406. That is, the data to be written to the rewritable nonvolatile memory module 406 is converted into a format acceptable to the rewritable nonvolatile memory module 406 through the memory interface 506. Specifically, if the memory management circuit 502 is to access the rewritable nonvolatile memory module 406, the memory interface 506 will transmit the corresponding instruction sequence. For example, the instruction sequences may include a write instruction sequence that indicates write data, a read instruction sequence that indicates read data, an erase instruction sequence that indicates erase data, and corresponding instruction sequences to indicate various memory operations (e.g., changing read voltage levels or performing garbage collection operations, etc.). These sequences of instructions are, for example, generated by memory management circuitry 502 and transferred to rewritable non-volatile memory module 406 through memory interface 506. These instruction sequences may include one or more signals, or data, on a bus. Such signals or data may include instruction codes or codes. For example, the read instruction sequence may include information such as a read identification code and a memory address.

In an example embodiment, the memory control circuit unit 404 further includes an error checking and correction circuit 508, a buffer memory 510, and a power management circuit 512.

The error checking and correction circuit 508 is coupled to the memory management circuit 502 and is used for performing error checking and correction operations to ensure the correctness of the data. Specifically, when the memory management circuit 502 receives a write command from the host system 11, the error checking and correcting circuit 508 generates a corresponding error correction code (error correcting code, ECC) and/or error checking code (error detecting code, EDC) for the data corresponding to the write command, and the memory management circuit 502 writes the data corresponding to the write command and the corresponding error correction code and/or error checking code into the rewritable nonvolatile memory module 406. Then, when the memory management circuit 502 reads data from the rewritable nonvolatile memory module 406, the error correction code and/or the error check code corresponding to the data are read at the same time, and the error check and correction circuit 508 performs an error check and correction operation on the read data according to the error correction code and/or the error check code.

The buffer memory 510 is coupled to the memory management circuit 502 and is used for temporarily storing data and instructions from the host system 11 or data from the rewritable nonvolatile memory module 406. The power management circuit 512 is coupled to the memory management circuit 502 and is used to control the power of the memory storage device 10.

In an example embodiment, the rewritable non-volatile memory module 406 of fig. 4 is also referred to as a flash memory module, and the memory control circuit unit 404 is also referred to as a flash memory controller for controlling the flash memory module. In an example embodiment, the memory management circuit 502 of FIG. 5 is also referred to as a flash memory management circuit.

Fig. 6 and 7 are exemplary diagrams of management entity blocks according to an exemplary embodiment of the present invention. Referring to FIG. 6, the memory control circuit unit 404 (or the memory management circuit 502) logically groups the physical erase units 410 (0) -410 (N) into a data area 602, an idle area 604, a system area 606 and a replacement area 608.

The physical erase units logically belonging to the data area 602 and the spare area 604 are used to store data from the host system 11. Specifically, the physically erased cells of the data area 602 are considered physically erased cells of the stored data, and the physically erased cells of the spare area 604 are physically erased cells of the data area 602. That is, when a write command and data to be written are received from the host system 11, the memory control circuit unit 404 (or the memory management circuit 502) will use the physical erase unit extracted from the spare area 604 to write data to replace the physical erase unit of the data area 602.

The physical erase unit logically belonging to the system area 606 is used for recording system data. For example, the system data includes the manufacturer and model of the rewritable nonvolatile memory module, the number of physical erased cells of the rewritable nonvolatile memory module, the number of physical programmed cells of each physical erased cell, etc.

The physically erased cells logically belonging to the replacement area 608 are used for the replacement process of the bad physically erased cells to replace the damaged physically erased cells. Specifically, if the replacement area 608 still has normal physical erase units and the physical erase units of the data area 602 are damaged, the memory control circuit unit 404 (or the memory management circuit 502) extracts the normal physical erase units from the replacement area 608 to replace the damaged physical erase units.

In particular, the number of physically erased cells in the data area 602, the spare area 604, the system area 606, and the replacement area 608 may vary according to different memory specifications. In addition, it should be understood that during operation of the memory device 10, the grouping relationship of physical erase units associated with the data area 602, the spare area 604, the system area 606, and the replacement area 608 dynamically changes. For example, when the physically erased cells in the spare area 604 are damaged and replaced by physically erased cells of the replacement area 608, the physically erased cells of the replacement area 608 are associated with the spare area 604.

Referring to FIG. 7, the memory control circuit unit 404 (or the memory management circuit 502) configures logical block addresses LBA (0) -LBA (H) to map physical erase units of the data area 602, wherein each logical block address has a plurality of logical addresses to map physical program units of corresponding physical erase units. When the host system 11 wants to write data to the logical address or update the data stored in the logical address, the memory control circuit unit 404 (or the memory management circuit 502) extracts a physical erase unit from the spare area 604 as an active physical erase unit to write data, so as to replace the physical erase unit of the data area 602. When the physical erase unit is full, the memory management circuit 502 extracts empty physical erase units from the spare area 604 as the active physical erase units to continue writing the updated data corresponding to the write command from the host system 1000. In addition, when the number of available physical erase units in the spare area 604 is less than the predetermined value, the memory management circuit 502 performs a garbage collection (garbage collection) operation (also referred to as an active data merge operation) to sort the active data in the data area 602, so as to re-associate the physical erase units in the data area 602 that do not store the active data to the spare area 604.

The operation of the memory control circuit unit 404 is described below as the operation of the memory management circuit 502.

In order to solve the problem of slow data reading caused by continuous data scattering on different physical pages, the data sorting method of the memory according to the present embodiment is used for the memory storage device 10 including the rewritable nonvolatile memory module 406, and can determine whether to reform the data by analyzing the data as concentrated or scattered. In another embodiment, the decision of whether to reform the data can also be made by analyzing whether the data is evenly distributed across the channels. In yet another embodiment, the data may be analyzed to be concentrated or scattered at the same time, and whether the data is evenly distributed in each channel may be analyzed to determine whether to reform the data.

The memory control circuit unit 404 receives an instruction from the host system 11. The instruction transmitted by the host system 11 is a fragment reassembly (fragment) instruction, and the instruction includes a data section. The data interval is the range in which the host system 11 determines that the data sort operation is required.

In this embodiment, after the memory control circuit unit 404 receives the instruction from the host system 11, the data scattering degree can be calculated according to the logical estimation values of the plurality of logical block addresses (Logical Block Address, LBAs) in the data interval and the physical estimation values of the plurality of physical erasure units mapped by the logical block addresses. The memory control circuit 404 can determine whether to perform a data sort operation according to the data scattering degree and a threshold value to shift the data in the physical erasing unit according to the logical block address. The memory control circuit unit 404 performs a data sort operation, and copies the physical erase units respectively mapped by consecutive logical subunits belonging to the logical block address to the same physical erase units according to the logical block address. Here, consecutive logical subunits refer to that the logical block address of one logical subunit is subsequent to the logical block address of another logical subunit. In other words, the start logical block address of one logical subunit is followed by the end logical block address of another logical subunit. It should be noted that, those skilled in the art should know how to perform the data sort operation, so the description is omitted here.

In a first embodiment, the degree of scattering of the data is determined by analyzing the data as concentrated or scattered. That is, the data is concentrated or scattered by determining the number of physical pages of the physical erase units corresponding to the data, and whether to reform the data is determined according to the determination result.

In detail, assume that the capacity of one physical page is 16K, and the data interval included in the instruction received by the memory control circuit unit 404 from the host system 11 is a segment of consecutive logical row addresses LCA (0) to LCA (7), which is a total of 8 data of 4K, i.e., 32K data. Ideally 32K of data need only be stored in 2 physical pages. In other words, in the case of the minimum physical configuration amount, the data arrangement of 32K is distributed over 32/16=2 physical pages, and the memory control circuit unit 404 only needs to read the rewritable nonvolatile memory module 406 twice to read all the data. However, if the data of 32K is arranged in 32/4=8 physical pages under the condition of the maximum physical configuration, the memory control circuit unit 404 needs to read all the data by the eight times of the rewritable nonvolatile memory module 406, which results in slower reading speed. Therefore, the method provided in this embodiment calculates the logical estimation value and the physical estimation value, and determines the data scattering degree according to the ratio of the logical estimation value (i.e., the minimum physical configuration amount) to the physical estimation value (i.e., the actual physical configuration amount), so as to determine that the data is concentrated or scattered. And compares the calculated data divergence with a threshold (also referred to as a first threshold) to determine whether to perform data sort. Here, the first threshold is preset to, for example, 0.75 or other preset thresholds, which is not limited in the present invention.

Specifically, after the memory control circuit unit 404 receives the instruction from the host system 11, it can calculate the logical estimation value according to the number of logical blocks of the logical block address of the data section included in the instruction, the logical block capacity and the physical page capacity of the rewritable nonvolatile memory module 406. In detail, the memory control circuit unit 404 calculates the data capacity of the data interval according to the number of logical blocks and the capacity of the logical blocks, and calculates the logical estimation value according to the data capacity and the physical page capacity of the rewritable nonvolatile memory module 406.

And, the memory control circuit unit 404 determines the physical estimation value according to the number of physical pages in the physical erase unit mapped by the logical block addresses, wherein each logical block address has a plurality of logical addresses to map the physical block addresses (Physical Block Address, PBA) corresponding to the physical erase unit.

Then, the memory control circuit unit 404 calculates the ratio of the logical estimation value to the physical estimation value to determine the data scattering degree, and determines whether to perform the data sort operation according to the data scattering degree and the first threshold value to move the data in the physical erasure unit according to the logical block address. In detail, the memory control circuit unit 404 can determine whether the data divergence is not greater than a first threshold value, and perform a data sort operation according to the logical block address when the data divergence is not greater than the first threshold value.

For example, the memory control circuit unit 404 obtains the number of logical blocks corresponding to the logical block addresses in the data interval included in the instruction, the capacity of each logical block, and the capacity of the physical page of the rewritable nonvolatile memory module 406, and calculates the logical estimation value according to the following equations (1) and (2). The memory control circuit unit 404 obtains the number of physical pages corresponding to the plurality of physical erasure units mapped by the logical block addresses, and sets the number of physical pages as the physical estimation value.

Logical block number x logical block capacity=data capacity (1)

Data capacity/entity page capacity = logical estimate (2)

Taking the memory control circuit unit 404 as an example, the number of logical blocks is 8, the logical page capacity is assumed to be 4K, the physical page capacity is assumed to be 16K, and the number of physical pages in the plurality of physical erase units mapped by the logical row addresses LCA (0) to LCA (7) is 3. Accordingly, the calculated logical estimate is 8×4+.16=2, and the physical estimate is 3. It should be noted that the present invention is not limited to the logical page capacity and the physical page capacity, and the logical page capacity and the physical page capacity may be different according to the memory storage devices of different specifications. In this embodiment, the memory control circuit unit 404 can calculate the ratio of the logical estimation value to the physical estimation value to be 2/3, i.e. the ratio is 0.66. Since the calculated ratio is 0.66 (i.e., data divergence) which is smaller than the first threshold (e.g., 0.75 in the present embodiment), the data representing this data section is not sufficiently concentrated, and thus the data sort operation must be performed.

In another embodiment of the same memory storage device, the number of physical pages corresponding to the plurality of physical erase units mapped by the logical row addresses LCA (0) -LCA (7) is 2, and thus the physical estimation value is 2. Accordingly, the memory control circuit unit 404 can calculate the ratio of the logic estimation value to the entity estimation value to be 2/2, i.e. the ratio is 1. Since the calculated ratio is 1, which is greater than the first threshold (e.g., 0.75 in the present embodiment), representing the data set of this data section, there is no need to perform a data sort operation.

In a second embodiment, the degree of scattering of the data is determined by analyzing whether the data is uniformly distributed in each channel. That is, whether to reform the data is determined by determining whether the number of logical pages corresponding to the data is distributed on the plane is average.

Assuming that the capacity of one physical page is 16K, the data section included in the instruction received by the memory control circuit unit 404 from the host system 11 is a segment of consecutive logical row addresses LCA (0) to LCA (7), and a total of 8 data of 4K, that is, 32K data. Ideally 32K of data need only be stored in 2 physical pages. In the preferred state, the 2 physical pages are distributed on different physical planes, representing the average of the data on each physical plane. In this case, the memory control circuit unit 404 can read the data at each physical plane, so that the reading efficiency is better. Conversely, if the 2 physical pages are distributed on the same physical plane, which represents the data set on each physical plane, the reading efficiency of the memory control circuit unit 404 is poor in this case. Therefore, the method provided by the embodiment calculates the number of logical pages and the number of physical planes to determine the data scattering degree, so as to determine that the data included in each physical plane is concentrated or average. And comparing the number of pages configured in one of the physical planes corresponding to the physical erasure units mapped by the logical block address included in the data interval with a second threshold value to determine whether to execute data sorting. Where the number of pages here refers to the number of physical pages. The second threshold is determined by a third threshold and the data divergence, and the third threshold is preset to be 2 or other preset thresholds, which is not limited in the present invention.

Specifically, after receiving the instruction from the host system 11, the memory control circuit unit 404 determines the logic estimation value according to the number of logical pages corresponding to the logical block address of the data interval included in the instruction. The memory control circuit unit 404 determines the physical estimation value according to the number of physical planes corresponding to the physical erasure unit mapped by the logical block address. Next, the memory control circuit unit 404 calculates the data divergence from the logical estimation value and the physical estimation value, and calculates the second threshold value from the data divergence and the third threshold value. When the number of pages allocated in one of the physical planes corresponding to the physical erase units mapped by the logical block address is not less than the second threshold, the memory control circuit unit 404 performs a data sort operation according to the logical block address.

In detail, the memory control circuit unit 404 obtains the number of logical pages corresponding to the plurality of logical block addresses in the data interval included in the instruction, and sets the number as the logical estimation value. The memory control circuit unit 404 obtains the number of physical planes corresponding to the plurality of physical erasure units mapped by the logical block addresses, and sets the number as the physical estimation value. Then, the memory control circuit unit 404 calculates the data divergence according to the following equations (3) and (4).

Logical estimate +.physical estimate = a (3)

Logical estimate%physical estimate = B (4)

The calculated A is set as the data scattering degree, represents the minimum page number configured in one entity plane under the ideal condition of data average, and the calculated A+B represents the optimal maximum page number of each entity plane. While the most undesirable situation is that each logical page configuration is concentrated in the same physical plane. In this embodiment, a third threshold is preset as an allowable threshold for the number of pages configured in each physical plane, and the second threshold is determined according to the third threshold and the data divergence.

For example, the memory control circuit unit 404 receives the data interval including the number of logical pages corresponding to the plurality of logical block addresses of 17, and the number of physical planes corresponding to the plurality of physical erasure units mapped by the logical block addresses is 4 as an example. That is, in the present embodiment, the logical evaluation value is 17, and the physical evaluation value is 4. The memory control circuit unit 404 may calculate a=4 according to equation (3), and calculate the second threshold value as a+the third threshold value (e.g. 2) =6 in the present embodiment. If the memory control circuit unit 404 determines that the number of pages allocated in the physical plane corresponding to the physical erasure unit mapped by the logical block address included in the data interval is not less than 6 (i.e., the second threshold), which indicates that the data is too concentrated in some physical planes, the memory control circuit unit 404 performs a data sort operation according to the logical block address. Conversely, if the memory control circuit unit 404 determines that the number of pages configured in the physical plane corresponding to the physical erasure unit mapped by the logical block address included in the data interval is less than 6 (i.e., the second threshold), which indicates that the data is uniformly distributed in each physical plane, the memory control circuit unit 404 does not perform the data sort operation.

In the third embodiment, the memory control circuit unit 404 can use the methods of the first embodiment and the second embodiment to determine whether to reform data. The methods of the first embodiment and the second embodiment are described in detail above, and will not be described here again.

Fig. 8 is a flowchart illustrating a data sort method of a memory according to an exemplary embodiment of the present invention. Referring to fig. 8, in step S802, an instruction is received from a host system, wherein the instruction includes a first data interval. In step S804, the data scattering degree is calculated according to the logical estimation values of the plurality of logical block addresses and the physical estimation values of the plurality of physical erasure units mapped by the logical block addresses in the first data interval. In step S806, it is determined whether to perform a data sort operation according to the data scattering degree and the threshold value to move the data in the physical erase unit according to the logical block address.

Fig. 9 is a flowchart illustrating a data sort method of a memory according to an exemplary embodiment of the present invention. Referring to fig. 9, in step S902, an instruction is received from a host system, wherein the instruction includes a first data interval. In step S904, a logical estimation value is calculated according to the number of logical blocks of the logical block address, the logical block capacity and the physical page capacity of the rewritable nonvolatile memory module in the first data interval. In step S906, the physical estimation value is determined according to the number of physical pages in the physical erasure unit mapped by the logical block address. In step S908, a ratio of the logical estimate to the physical estimate is calculated to determine the data divergence. In step S910, it is determined whether the data divergence is not greater than a first threshold. If the data divergence is not greater than the first threshold (step S910, yes), in step S912, a data sort operation is performed according to the logical block address. If the data divergence is greater than the first threshold (step S910, no), the process returns to step S902 to wait for receiving the command.

Fig. 10 is a flowchart illustrating a data sort method of a memory according to an exemplary embodiment of the present invention. In step S1002, an instruction is received from a host system, wherein the instruction includes a first data interval. In step S1004, a logical estimation value is determined according to the number of logical pages corresponding to the logical block address of the first data interval. In step S1006, an estimated physical value is determined according to the number of physical planes corresponding to the physical erasure unit mapped by the logical block address. In step S1008, data divergence is calculated according to the logical estimation value and the physical estimation value. In step S1010, a second threshold is calculated according to the data divergence and the third threshold. In step S1012, it is determined whether the number of pages configured in one of the physical planes corresponding to the physical erasure unit mapped by the logical block address is not less than a second threshold. If the number of pages is not less than the second threshold (step S1012, yes), in step S1014, a data sort operation is performed according to the logical block address. If the number of pages is less than the second threshold (step S1012, no), the process returns to step S1002 to wait for receiving the instruction.

It should be noted that each step in fig. 8 to 10 may be implemented as a plurality of codes or circuits, which is not limited by the present invention. In addition, the methods of fig. 8 to 10 may be used with the above exemplary embodiments, or may be used alone, and the present invention is not limited thereto.

In summary, according to the data sorting method, the memory storage device and the memory control circuit unit of the memory provided by the embodiments of the present invention, the data scattering degree can be calculated according to the logic estimation values of the plurality of logic block addresses of the data interval included in the instruction and the entity estimation values of the plurality of entity erasure units mapped by the logic block addresses, and the data scattering degree and the threshold value are compared to determine whether the data is concentrated or scattered. Therefore, whether the data interval needs to be subjected to data arrangement operation or not can be determined, and the speed of reading data is further improved.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.

Claims

1. A method of data sort of a memory for a memory storage device comprising a rewritable non-volatile memory module, the method comprising:

Receiving an instruction from a host system, wherein the instruction includes a data interval;

calculating data scattering degree according to the logic estimated values of a plurality of logic block addresses of the data interval and the entity estimated values of a plurality of entity erasure units mapped by the plurality of logic block addresses, wherein the data scattering degree is the ratio of the logic estimated values to the entity estimated values; and

judging whether to execute data sorting operation according to the data disorder degree and the threshold value to move the data in the entity erasing units according to the logic block addresses, wherein the data interval is the range of the host system to execute the data sorting operation,

wherein the step of calculating the data scrambling degree according to the logical estimation values of the plurality of logical block addresses of the data interval and the physical estimation values of the plurality of physical erasure units mapped by the plurality of logical block addresses comprises:

calculating the logic estimation value according to the number of the plurality of logic block addresses of the data interval, the capacity of the plurality of logic block addresses and the physical page capacity of the rewritable nonvolatile memory module;

Determining the entity estimation value according to the entity page quantity in the entity erasing units mapped by the logic block addresses; and

calculating the ratio of the logic estimation value to the entity estimation value to determine the data divergence.

2. The data sort method of the memory according to claim 1, wherein the instruction includes a defragmentation instruction.

3. The data sort method of the memory according to claim 1, wherein the step of calculating the logical evaluation value from the number of the plurality of logical block addresses of the data section, the capacity of the plurality of logical block addresses, and the physical page capacity of the rewritable nonvolatile memory module includes:

calculating a data capacity of the data interval according to the number of the plurality of logical block addresses and the capacities of the plurality of logical block addresses; and

the logical estimate is calculated from the data capacity and the physical page capacity of the rewritable non-volatile memory module.

4. The method of claim 1, wherein determining whether to perform the data sort operation to move the data in the plurality of physical erase units according to the plurality of logical block addresses based on the data divergence and the threshold comprises:

And executing the data sorting operation according to the plurality of logic block addresses when the data divergence is not greater than a first threshold.

5. A method of data sort of a memory for a memory storage device comprising a rewritable non-volatile memory module, the method comprising:

Determining the logic estimation value according to the number of the logic pages corresponding to the plurality of logic block addresses in the data interval;

determining the entity estimation value according to the number of entity planes corresponding to the entity erasure units mapped by the logic block addresses; and

and calculating the data divergence according to the logic estimation value and the entity estimation value.

6. The method of claim 5, wherein determining whether to perform the data sort operation to move the data in the plurality of physical erase units according to the plurality of logical block addresses based on the data divergence and the threshold comprises:

calculating a second threshold according to the data divergence and a third threshold; and

and executing the data sorting operation according to the plurality of logical block addresses when the number of pages configured in one entity plane corresponding to the plurality of entity erasing units mapped by the plurality of logical block addresses is not smaller than the second threshold value.

7. A memory storage device, comprising:

the connection interface unit is used for being coupled to the host system;

a rewritable nonvolatile memory module; and

A memory control circuit unit coupled to the connection interface unit and the rewritable nonvolatile memory module,

wherein the memory control circuit unit is to receive an instruction from the host system, wherein the instruction includes a data interval;

the memory control circuit unit is further configured to calculate a data divergence according to the logical estimation values of the plurality of logical block addresses of the data interval and the physical estimation values of the plurality of physical erasure units mapped by the plurality of logical block addresses, wherein the data divergence is a ratio of the logical estimation values to the physical estimation values, and

the memory control circuit unit is further configured to determine whether to perform a data sort operation according to the data scattering degree and a threshold value, so as to move data in the plurality of physical erase units according to the plurality of logical block addresses, wherein the data interval is a range in which the host system is to perform the data sort operation,

the operation of the memory control circuit unit further for calculating the data divergence according to the logical estimation values of the plurality of logical block addresses of the data interval and the physical estimation values of the plurality of physical erasure units mapped by the plurality of logical block addresses comprises:

8. The memory storage device of claim 7, wherein the instructions comprise a defragmentation instruction.

9. The memory storage device of claim 7, wherein calculating the logical estimate from the number of the plurality of logical block addresses, the capacity of the plurality of logical block addresses, and the physical page capacity of the rewritable non-volatile memory module of the data interval comprises:

10. The memory storage device of claim 7, wherein the memory control circuit unit further to determine whether to perform the data sort operation to move data in the plurality of physical erase units according to the plurality of logical block addresses based on the data divergence and the threshold comprises:

11. A memory storage device, comprising:

the connection interface unit is used for being coupled to the host system;

a rewritable nonvolatile memory module; and

wherein the memory control circuit unit is configured to receive an instruction from the host system, wherein the instruction comprises a data interval,

12. The memory storage device of claim 11, wherein the memory control circuit unit further to determine whether to perform the data sort operation to move data in the plurality of physical erase units according to the plurality of logical block addresses based on the data divergence and the threshold comprises:

13. A memory control circuit unit for controlling a memory storage device including a rewritable nonvolatile memory module, and comprising:

a host interface for coupling to a host system;

a memory interface for coupling to the rewritable non-volatile memory module; and

a memory management circuit coupled to the host interface and the memory interface,

14. The memory control circuit unit of claim 13, wherein the instruction comprises a defragmentation instruction.

15. The memory control circuit unit of claim 13, wherein calculating the logical estimate from the number of the plurality of logical block addresses, the capacity of the plurality of logical block addresses, and the physical page capacity of the rewritable non-volatile memory module of the data interval comprises:

16. The memory control circuit unit of claim 13, wherein the memory control circuit unit further configured to determine whether to perform the data sort operation to move data in the plurality of physical erase units according to the plurality of logical block addresses based on the data divergence and the threshold comprises:

17. A memory control circuit unit for controlling a memory storage device including a rewritable nonvolatile memory module, and comprising:

A host interface for coupling to a host system;

18. The memory control circuit unit of claim 17, wherein the memory control circuit unit further configured to determine whether to perform the data sort operation to move data in the plurality of physical erase units according to the plurality of logical block addresses based on the data divergence and the threshold comprises: