CN113312204A - Enhanced error correction method and deep error correction method based on double-layer RAID information - Google Patents
Enhanced error correction method and deep error correction method based on double-layer RAID information Download PDFInfo
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Abstract
The invention discloses an enhanced error correction method and a deep error correction method based on double-layer RAID information, wherein when ECC uncorrectable error data occur in flash memory particles, the enhanced error correction method comprises the following steps: s1, determining the address of the uncorrectable data A, and setting the positions of the data A in the transverse RAID lines and the longitudinal RAID lines to be respectively X and Y ', X is more than or equal to 1 and less than or equal to N, Y' is more than or equal to 1 and less than or equal to M ', and recording the corresponding data as DATAX and DATAY' respectively; s2, calculating values DRAID and DRAID' obtained through transverse RAID line recovery and longitudinal RAID line recovery respectively; s3, re-reading the data A to obtain new data DATANew, and performing XOR, bit addition and calculation on the data A to obtain data DATAANew; and S4, decoding the obtained new frame of data. The invention improves the error correction capability of the SSD error correction algorithm and the service life of the NAND particles.
Description
Technical Field
The invention relates to the technical field of data storage, in particular to an enhanced error correction method and a deep error correction method based on double-layer RAID information.
Background
SSD (solid State drive) solid State drives, commonly referred to as solid State disks, are hard disks made of solid State electronic memory chip arrays, and usually include three major portions, namely, an SSD main control chip, a flash memory particle array for storing data, and a cache chip. The solid state disk has the characteristics of fast reading and writing, light weight, low energy consumption, small size and the like which are not possessed by the traditional mechanical hard disk, so that the solid state disk is widely applied to consumer-level markets, data centers and enterprise-level markets.
One characteristic of flash memory grains is that bit reversals occur to varying degrees during the life cycle, and to further increase the life of SSD disks, storage vendors correct bit errors by ECC (Error Correction Code, written to the disk with the user data generation) Error Correction techniques on top of the flash memory grains. When data is written into the host computer, ECC coding is adopted to write check bits, and when the data is in error due to bit inversion, the data can be corrected by using the ECC check bits when the data is read, and correct data is returned to the host computer. Common ECC correction mechanisms are BCH (Bose-Chaudhuri-Hocquenghem), RS (Reed-Solomon) and LDPC (Low Density Parity check), can realize the detection and recovery of data errors corresponding to the ECC with the error correction capability, and if the bit number of the errors exceeds the error correction capability of the ECC (called unorderable bit error), the ECC cannot be detected and recovered. If a RAID (redundant Array of redundant disks) architecture is adopted in the main control chip, the ECC is not correctable and can be recovered by using a RAID mechanism.
With the updating of flash memory particles, from SLC (single layer memory cell), MLC (double layer memory cell), to TLC (three layer memory cell), and QLC (four layer memory cell), the unit bit cost is lower and shorter, the lifetime is shorter and shorter, that is, the error rate is higher, and the error correction capability of ECC is also higher. Flash manufacturers will set error check code spaces (out-of-band, OOB spaces) in flash granules, and the error correction capability of error correction algorithms BCH, RS and LDPC will be limited by the OOB size, which makes it more and more difficult to meet the error correction capability requirements of TLC and QLC flash memories.
Chinese patent publication No. CN112383314B discloses "an LDPC error correction method based on RAID information", which is based on the characteristic of the LDPC error correction algorithm, and the output data of the LDPC decoding is better (closer to correct data) than the input data when most of the data is in an uncorrectable state; moreover, the LDPC error correction algorithm comprises soft information of each bit, and the bit which is possibly wrong is skillfully positioned by using the XOR characteristic of the RAID, so that the processed data is more accurate. The data processed by the method reduces the load of the LDPC, and improves the capacity of the LDPC error correction algorithm in a phase-changing manner.
Chinese patent publication No. CN111679934B discloses an "error correction method based on RAID information, a computer-readable storage medium, and a processor", which is based on the principle that a region 2, i.e., a bit having a high error probability, can be located by moving a read threshold using the Vt characteristic distribution of NAND; and the XOR characteristic of the RAID is utilized to replace the bit with high error probability, so that the processed data bit has confidence coefficient and is more accurate.
The invention provides an enhanced error correction method and a deep error correction method based on double-layer RAID information, which also use XOR operation, although the three patents all have XOR operation, the action point and the utilized principle are completely different; in addition, there is a certain deficiency in the data recovery capability of the two patents when they encounter some uncorrectable data that is very important to the user.
Disclosure of Invention
The invention provides an enhanced error correction method based on double-layer RAID information in order to overcome the defects of the technology, based on the RAID architecture in solid state storage, the error correction capability of a BCH or RS or LDPC error correction algorithm of an SSD master control chip is enhanced by adding a layer of RAID information protection, namely the thought of double-layer RAID, the error correction capability is greatly improved by replacing the service life of part of storage space, and the service life of flash memory particles is greatly prolonged. The invention also provides a depth error correction method.
The technical scheme adopted by the invention for overcoming the technical problems is as follows:
an enhanced error correction method based on double-layer RAID information adopts an error correction method when ECC uncorrectable error data appears in flash memory particles, and comprises the following steps:
s1, determining the address of ECC uncorrectable data A, and setting the position of the data A in a transverse RAID line to be X, wherein X is more than or equal to 1 and less than or equal to N, the corresponding data to be DATAX, the position of the data A in a longitudinal RAID line to be Y ', wherein Y ' is more than or equal to 1 and less than or equal to M ', the corresponding data to be DATAY ', wherein both the DATAX and the DATAY ' are data A and are the same data;
s2, calculating values DRAID and DRAID 'obtained by performing horizontal RAID line recovery and vertical RAID line recovery calculation respectively, wherein the DRAID and the DRAID' are obtained by performing exclusive OR operation on the horizontal RAID line and the vertical RAID line respectively;
and S3, re-reading the uncorrectable data A to obtain new data DATANew, and performing XOR, bit sum and calculation on the DATANew to obtain data DATAANew.
Further, in step S2, the data calculation of the DRAID includes the following steps:
according to the binding rule of the transverse RAID line and the address of the data A, calculating the addresses of all data except the data A in the same transverse RAID line, including the check code data of the transverse RAID line;
reading corresponding data according to the calculated address, and performing exclusive OR operation on output data of the data after ECC error correction one by one to obtain DRAID, wherein the operational expression of the DRAID is as follows:
DRAID=DXOR_H^DATA1^DATA2^…^DATA（X-1）^DATA（X+1）^…^DATAN
in the above equation, DXOR _ H is parity code DATA of a horizontal RAID line, and DXOR _ H = DATA1^ DATA2^ DATA3^ … ^ DATAN, where the number of N is not limited, and ^ represents XOR by bit.
Further, in step S2, the data calculation of DRAID' includes the following steps:
according to the binding rule of the longitudinal RAID line and the address of the data A, calculating the addresses of all data except the data A in the same longitudinal RAID line, including the check code data of the longitudinal RAID line;
reading corresponding data according to the calculated address, and performing exclusive OR operation on output data of the data after ECC error correction one by one to obtain DRAID ', wherein the operational expression of the DRAID' is as follows:
DRAID’=DXOR_V^DATA1’^DATA2’^…^DATA（Y-1）’^DATA（Y+1）’^…^DATAM’
in the above equation, DXOR _ V is parity code DATA of a vertical RAID line, and DXOR _ V = DATA1 ' ^ DATA2 ' ^ DATA3 ' ^ … ^ DATAM ', where the number of M ' is not limited, and ^ represents XOR by bit.
Further, in step S2, before calculating the DRAID and the DRAID', the output data after ECC error correction is subjected to exclusive or operation one by one regardless of whether ECC is uncorrectable.
Further, in step S3, the calculation formula of DATAANew is:
DATAANew = DATANew ^ ((DRAID ^DATANew) & (DRAID’^DATANew ))。
further, step S4 is included after step S3, and step S4 includes: the ECC decoding is performed again on the new frame of data processed in step S3.
Further, after ECC decoding, whether ECC decoding is successful is determined:
if the success is achieved, the correct data is directly returned;
otherwise, the information of decoding failure is returned.
The invention also provides a deep error correction method, when the enhanced error correction method based on the double-layer RAID information fails to recover the uncorrectable data A, the deep error correction method is executed, and the deep error correction method comprises the following steps:
(1) searching all other uncorrectable data of the transverse RAID line where the DATAX is located;
(2) if the data can be recovered, the recovered new data is used for covering the previous error data;
(3) judging whether all the uncorrectable data of the transverse RAID line is completely fetched: if yes, executing the next step; otherwise, returning to the step (2) to continue to fetch the uncorrectable data of the transverse RAID line;
(4) searching all other uncorrectable data of the longitudinal RAID line where the DATAY' is located;
(5) any uncorrectable data of the longitudinal RAID line is recovered by the enhanced error correction method based on the double-layer RAID information, and if the uncorrectable data can be recovered, the previous error data is covered by the recovered new data;
(6) judging whether all the uncorrectable data of the longitudinal RAID line is completely fetched: if yes, executing the next step; otherwise, returning to the step (5) to continue to obtain the uncorrectable data of the longitudinal RAID line;
(7) and after the data of all the transverse RAID lines and the longitudinal RAID lines are updated, executing the enhanced error correction method based on the double-layer RAID information again.
Further, the order of steps (1) - (3) and steps (4) - (6) may be changed, that is, the above steps (4) - (6) may be executed first, and then the above steps (1) - (3) may be executed, as long as it is ensured that all of the uncorrectable data of the horizontal RAID rows and the uncorrectable data of the vertical RAID rows are completed.
The invention has the beneficial effects that:
1. the invention establishes a double-layer RAID architecture by occupying a part of user space, and establishes a new algorithm based on the double-layer RAID architecture and the existing ECC algorithm. The invention skillfully utilizes the information of the double-layer RAID, and the double-layer RAID comprises the error bit information of the uncorrectable data, thereby effectively identifying the error bit of the uncorrectable data; the RAID line also has interference of error bit of other ECC uncorrectable data, but the NAND error has randomness or the probability of error of different NAND in the same bit is very small, so the interference is further reduced after the AND operation calculation, and the error bit number of the NAND read data is obviously reduced. After the calculation of the method, the large error probability of the NAND read data is offset by the calculation, the introduced errors are limited, the number of error bits of the NAND read data is greatly reduced, and after the error correction algorithm of the SSD is carried out, the error correction capability of the SSD error correction algorithm is improved in a phase-changing manner, and the service life of NAND particles is prolonged.
2. The method of the invention ensures that the ECC algorithm is not limited, and the traditional BCH, RS and LDPC algorithms are all applicable and have wide application range.
3. Compared with the patents with the publication numbers of CN112383314B and CN111679934B, the method of the present invention has at least two innovation points, and firstly, the method of the present invention has a special dual RAID architecture, which not only serves as a basis for the enhanced error correction method based on dual-layer RAID information described in the present invention, but also can meet the requirement of SSD deep error correction, i.e., the user data is recovered as far as possible without considering the influence of read latency and read bandwidth on the SSD controller, which is very important for the user. Second, the present invention utilizes the XOR property of dual RAID, since both the horizontal RAID and the vertical RAID include the target data, the error of the target data can be directly extracted by using the and operation, and the means for marking the error in the process of processing is direct and effective by using the special dual RAID architecture and the intersection point of the RAID to extract the error of the target data, without any limitation. Although the invention and the patent with the publication number of CN112383314B and the patent with the publication number of CN111679934B have XOR operation, the points of action and the principles of utilization of the three are completely different, the patent with the publication number of CN112383314B depends on the design of LDPC error correction algorithm, and the patent with the publication number of CN111679934B depends on the Vt characteristic distribution of NAND.
Drawings
Fig. 1 is a flowchart of an enhanced error correction method based on dual-layer RAID information according to an embodiment of the present invention.
Fig. 2 is a schematic distribution diagram of a dual-layer RAID according to an embodiment of the present invention.
Detailed Description
In order to facilitate a better understanding of the invention for those skilled in the art, the invention will be described in further detail with reference to the accompanying drawings and specific examples, which are given by way of illustration only and do not limit the scope of the invention.
Example 1
Embodiment 1 of the present invention provides an enhanced error correction method based on dual-layer RAID information, and in this embodiment, it is not limited to which level of RAID structure is specifically adopted in a flash memory controller, as long as the following constraint conditions are met.
Specifically, as shown in fig. 1 and fig. 2, in the enhanced error correction method based on dual-layer RAID information according to this embodiment, when error data that is uncorrectable by ECC occurs in a flash memory granule, the error correction method adopted includes the following steps:
in order to implement the error correction method described in this embodiment, a layer of RAID protection needs to be added, and a part of the NAND storage space is sacrificed. And for M' row RAID rows, longitudinal binding can be carried out, and DXOR _ V is check code data of the longitudinal RAID rows. The size of M 'can be designed according to the reduced space that users can bear, and the total NAND storage space is reduced by 1/(M' + 1).
Step S1, the address of ECC uncorrectable data a is determined.
Specifically, determining the address of ECC uncorrectable data a includes: and setting the position of the data A in the transverse RAID line to be X, wherein X is more than or equal to 1 and less than or equal to N, corresponding data to be DATAX, the position of the data A in the longitudinal RAID line to be Y ', wherein Y ' is more than or equal to 1 and less than or equal to M ', corresponding data to be DATAY ', wherein the DATAX and the DATAY ' are both the data A and are the same data.
Step S2, calculating values DRAID and DRAID 'obtained by performing horizontal RAID row recovery and vertical RAID row recovery calculation, respectively, where the DRAID and the DRAID' are obtained by performing an exclusive or operation on the horizontal RAID row and the vertical RAID row.
The conventional RAID recovery requires that, except for data that needs to be recovered, other data in a RAID row all need to satisfy an uncorrectable condition before RAID recovery is successful, but the method described in this embodiment does not have this limitation, that is, no matter whether other data in the RAID row is correctable, operation needs to be involved.
And setting DXOR _ H as check code data of a horizontal RAID line, wherein the expression of DXOR _ H is as follows:
DXOR_H=DATA1^DATA2^DATA3^…^DATAN
in the above equation, the number of N is not limited, and ^ represents exclusive or by bit.
Setting DXOR _ V as check code data of a vertical RAID line, wherein the expression of DXOR _ V is as follows:
DXOR_V=DATA1’^DATA2’^DATA3’^…^DATAM’
in the above equation, the number of M' is not limited, and ^ represents exclusive or by bit.
(1) The data calculation of the DRAID comprises the following steps:
firstly, according to the binding rule of the transverse RAID line and the address of the data A, calculating the addresses of all data except the data A in the same transverse RAID line, wherein check code data of the transverse RAID line are required to be read again;
secondly, reading out corresponding data according to the calculated address, and performing exclusive-or operation on output data (no matter whether ECC is uncorrectable) of the data after ECC error correction to obtain DRAID, wherein the operational expression of the DRAID is as follows:
DRAID=DXOR_H^DATA1^DATA2^…^DATA（X-1）^DATA（X+1）^…^DATAN。
(2) the data calculation of DRAID' comprises the following steps:
firstly, according to the binding rule of a longitudinal RAID line and the address of data A, calculating the addresses of all data except the data A in the same longitudinal RAID line, wherein check code data of the longitudinal RAID line are required to be read again;
secondly, reading out corresponding data according to the calculated address, and performing exclusive-or operation on output data (no matter whether ECC is uncorrectable) of the data after ECC error correction to obtain DRAID ', wherein the operational expression of the DRAID' is as follows:
DRAID’=DXOR_V^DATA1’^DATA2’^…^DATA（Y-1）’^DATA（Y+1）’^…^DATAM’。
and step S3, re-reading the uncorrectable data A to obtain new data DATANew, and performing XOR, bit and calculation on the DATANew to obtain data DATAANew, wherein the data DATAANew is new data after error correction.
Specifically, the calculation formula of DATAANew is as follows:
DATAANew = DATANew ^ ((DRAID ^ DATANew) & (DRAID’^ DATANew ))。
step S4 is to perform ECC decoding again on the new frame of data obtained through the processing in step S3.
After the data processing, a frame of new read data is formed, and the new read data needs to be decoded by using the existing ECC decoding method, so that the details are not repeated.
After ECC decoding, it needs to be judged whether ECC decoding is successful: if the success is achieved, the correct data is directly returned; otherwise, the decoding failure information is returned, and then the next process is entered, where the next process refers to another process of the controller, and is controlled by the FW, and may be a stronger error correction algorithm, or an error is reported to the user, depending on the controller.
After decoding, the whole process of the enhanced error correction method based on the dual-layer RAID information described in this embodiment is completed.
The key point of the invention is that the error bit of the uncorrectable data is marked by the information of the double-layer RAID and is reversed. The RAID line also has interference of error bit of other ECC uncorrectable data, but the NAND error has randomness or the probability of error of different NAND in the same bit is very small, so the interference is further reduced after AND operation calculation. The error bit information of the target data is screened out by the data processed by the method by utilizing the error probability of the flash memory particles, so that the capability of an error correction algorithm is greatly improved.
Example 2
The enhanced error correction method based on the dual-layer RAID information described in embodiment 1 can solve a scenario where an ECC is uncorrectable in a general SSD controller, and can ensure that normal reading and writing of the SSD controller are smoothly performed. When a user encounters some very important uncorrectable data, the present embodiment provides a deep error correction method that tries to recover the user data without considering the effect of read latency and read bandwidth on the SSD controller.
As shown in fig. 2, the depth error correction method includes the following steps:
(1) searching all other uncorrectable data of the transverse RAID line where the DATAX is located;
(2) any uncorrectable data of one transverse RAID line is recovered by the enhanced error correction method based on the double-layer RAID information in the embodiment 1, and if the uncorrectable data can be recovered, the recovered new data is used for covering the previous error data;
(3) judging whether all the uncorrectable data of the transverse RAID line is completely fetched: if yes, executing the next step; otherwise, returning to the step (2) to continue to obtain the uncorrectable data of the transverse RAID line until all the uncorrectable data of the transverse RAID line is obtained;
(4) searching all other uncorrectable data of the longitudinal RAID line where the DATAY' is located;
(5) any uncorrectable data of a longitudinal RAID line is recovered by the enhanced error correction method based on the double-layer RAID information in the embodiment 1, and if the uncorrectable data can be recovered, the recovered new data is used for covering the previous error data;
(6) judging whether all the uncorrectable data of the longitudinal RAID line is completely fetched: if yes, executing the next step; otherwise, returning to the step (5) to continue to fetch the uncorrectable data of the longitudinal RAID line until all the uncorrectable data of the longitudinal RAID line is fetched;
(7) after the data of all the transverse RAID lines and the longitudinal RAID lines are updated, the enhanced error correction method based on the double-layer RAID information described in the embodiment 1 is executed again.
The above-mentioned steps (1) - (3) and the order of the steps (4) - (6) may be exchanged as a whole, that is, the above-mentioned steps (4) - (6) may be executed first, and then the above-mentioned steps (1) - (3) may be executed, as long as it is ensured that all the uncorrectable data of the horizontal RAID rows and the uncorrectable data of the vertical RAID rows are completed.
The deep error correction method described in this embodiment may be freely combined according to the result of each step according to the requirement, and may also sequentially recover all the uncorrectable data in M ' +1 row and N +1 column for recovering the data DATAX (DATAY '), so as to greatly improve the recovery probability of the uncorrectable data DATAX (DATAY ').
The foregoing merely illustrates the principles and preferred embodiments of the invention and many variations and modifications may be made by those skilled in the art in light of the foregoing description, which are within the scope of the invention.
Claims (9)
1. An enhanced error correction method based on double-layer RAID information is characterized in that when ECC uncorrectable error data occur in flash memory particles, the adopted error correction method comprises the following steps:
s1, determining the address of ECC uncorrectable data A, and setting the position of the data A in a transverse RAID line to be X, wherein X is more than or equal to 1 and less than or equal to N, the corresponding data to be DATAX, the position of the data A in a longitudinal RAID line to be Y ', wherein Y ' is more than or equal to 1 and less than or equal to M ', the corresponding data to be DATAY ', wherein both the DATAX and the DATAY ' are data A and are the same data;
s2, calculating values DRAID and DRAID 'obtained by performing horizontal RAID line recovery and vertical RAID line recovery calculation respectively, wherein the DRAID and the DRAID' are obtained by performing exclusive OR operation on the horizontal RAID line and the vertical RAID line respectively;
and S3, re-reading the uncorrectable data A to obtain new data DATANew, and performing XOR, bit sum and calculation on the DATANew to obtain data DATAANew.
2. The method of claim 1, wherein the step S2, the data calculation of DRAID includes the following steps:
according to the binding rule of the transverse RAID line and the address of the data A, calculating the addresses of all data except the data A in the same transverse RAID line, including the check code data of the transverse RAID line;
reading corresponding data according to the calculated address, and performing exclusive OR operation on output data of the data after ECC error correction one by one to obtain DRAID, wherein the operational expression of the DRAID is as follows:
DRAID=DXOR_H^DATA1^DATA2^…^DATA（X-1）^DATA（X+1）^…^DATAN
in the above equation, DXOR _ H is parity code DATA of a horizontal RAID line, and DXOR _ H = DATA1^ DATA2^ DATA3^ … ^ DATAN, where the number of N is not limited, and ^ represents XOR by bit.
3. The method according to claim 2, wherein the data calculation of DRAID' in step S2 includes the following steps:
according to the binding rule of the longitudinal RAID line and the address of the data A, calculating the addresses of all data except the data A in the same longitudinal RAID line, including the check code data of the longitudinal RAID line;
reading corresponding data according to the calculated address, and performing exclusive OR operation on output data of the data after ECC error correction one by one to obtain DRAID ', wherein the operational expression of the DRAID' is as follows:
DRAID’=DXOR_V^DATA1’^DATA2’^…^DATA（Y-1）’^DATA（Y+1）’^…^DATAM’
in the above equation, DXOR _ V is parity code DATA of a vertical RAID line, and DXOR _ V = DATA1 ' ^ DATA2 ' ^ DATA3 ' ^ … ^ DATAM ', where the number of M ' is not limited, and ^ represents XOR by bit.
4. The method according to claim 3, wherein in step S2, before calculating DRAID and DRAID' respectively, the output data after ECC error correction is XOR-ed one by one regardless of ECC uncorrectable.
5. The method of claim 1, wherein in step S3, DATAANew is calculated as:
DATAANew = DATANew ^ ((DRAID ^ DATANew) & (DRAID’^ DATANew ))。
6. the method according to any one of claims 1 to 5, further comprising a step S4 after the step S3, wherein the step S4 comprises:
the ECC decoding is performed again on the new frame of data processed in step S3.
7. The method of claim 6, wherein after the ECC decoding, determining whether the ECC decoding was successful:
if the success is achieved, the correct data is directly returned;
otherwise, the information of decoding failure is returned.
8. A deep error correction method, when the enhanced error correction method based on dual-layer RAID information according to any one of claims 1 to 7 fails to recover uncorrectable data a, the deep error correction method is performed, and the deep error correction method includes the steps of:
(1) searching all other uncorrectable data of the transverse RAID line where the DATAX is located;
(2) recovering the uncorrectable data of any one horizontal RAID row by the enhanced error correction method based on the double-layer RAID information according to any one of claims 1 to 7, and if the uncorrectable data can be recovered, covering the previous error data by the recovered new data;
(3) judging whether all the uncorrectable data of the transverse RAID line is completely fetched: if yes, executing the next step; otherwise, returning to the step (2) to continue to fetch the uncorrectable data of the transverse RAID line;
(4) searching all other uncorrectable data of the longitudinal RAID line where the DATAY' is located;
(5) recovering the uncorrectable data of any one longitudinal RAID row by the enhanced error correction method based on the double-layer RAID information according to any one of claims 1 to 7, and if the uncorrectable data can be recovered, covering the previous error data by the recovered new data;
(6) judging whether all the uncorrectable data of the longitudinal RAID line is completely fetched: if yes, executing the next step; otherwise, returning to the step (5) to continue to obtain the uncorrectable data of the longitudinal RAID line;
(7) after updating the data of all the transverse RAID lines and the longitudinal RAID lines, executing the enhanced error correction method based on the double-layer RAID information of any claim 1 to 7 again.
9. The method of claim 8, wherein the order of steps (1) - (3) and steps (4) - (6) can be exchanged.
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| CN118016134A (en) * | 2024-04-09 | 2024-05-10 | 杭州阿姆科技有限公司 | RAID-based multiple enhancement type error correction method applied to SSD |
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