CN113281610A

CN113281610A - Electric power traveling wave fault location system

Info

Publication number: CN113281610A
Application number: CN202110529660.9A
Authority: CN
Inventors: 朱留存; 王骥月; 陈明友
Original assignee: Beibu Gulf University
Current assignee: Beibu Gulf University
Priority date: 2021-05-14
Filing date: 2021-05-14
Publication date: 2021-08-20

Abstract

The invention discloses a power traveling wave fault location system which comprises a CPU (central processing unit), an FPGA (field programmable gate array), a wave recording memory, a voltage and current acquisition module and a power supply module for power supply, wherein the voltage and current acquisition module is connected to the FPGA; the voltage and current acquisition module comprises a mutual inductor, a conditioning circuit and a high-speed AD module, and the mutual inductor is connected to the FPGA through the conditioning circuit and the high-speed AD module; the analog fault traveling wave signal acquired by the mutual inductor is processed by the conditioning circuit and then input into the high-speed AD module for processing, and the conditioning circuit performs resistance voltage division processing, transformer differential processing and RC low-pass filtering processing in sequence. The invention obtains the fault voltage current traveling wave on the line by the mutual inductor, the voltage current signal of 6 ways of analog quantity is changed into the digital signal to send to the FPGA through the high-speed AD analog-to-digital conversion, the SDRAM carried by the invention is used for storing the traveling wave signal, and the CPU reads the traveling wave signal data of the buffer area and processes the traveling wave signal data to calculate the fault distance.

Description

Electric power traveling wave fault location system

Technical Field

The invention relates to the technical field of measurement of power systems, in particular to a power traveling wave fault location system.

Background

The transmission line fault in the power system directly affects the whole power supply system, and the power supply system can be quickly repaired at the first time, so that the loss caused by power failure can be reduced. Therefore, the fault point can be quickly and accurately positioned, and the method has great application value.

The position of a line fault point is judged quickly and accurately, and the stability of the power system can be effectively guaranteed. Meanwhile, the accurate positioning can reduce the burden of traditional manual line patrol, reduce the loss caused by line faults and have great economic and social benefits.

The current fault location method mainly comprises the following steps: according to different distance measurement principles, the method is divided into an impedance method and a traveling wave method; compared with the former, the latter has the advantages of high ranging precision, small error, high adaptability and the like. According to different information acquisition modes required by ranging, the method is divided into a single-end method and a double-end method; by adopting a single-end method, the method is easy to realize, has lower cost and supports various different line current situations; and the double-end method is adopted, so that the reliability is low, the requirement on communication is high, and the clocks need to be accurately synchronized.

As described above, the present application provides a method for performing traveling wave fault location using a single-ended electrical measurement method, based on the current state of the art.

Disclosure of Invention

The invention aims to solve the problems and provides a power traveling wave fault location system, which adopts a single-end electrical quantity measurement method to perform traveling wave fault location, has high precision and reliability and is not influenced by fault resistance and line types.

In order to achieve the purpose, the technical scheme adopted by the invention is as follows:

a power traveling wave fault location system comprises a CPU, an FPGA, a wave recording memory, a voltage and current acquisition module and a power supply module for power supply, wherein the voltage and current acquisition module is connected to the FPGA; the voltage and current acquisition module comprises a mutual inductor, a conditioning circuit and a high-speed AD module, and the mutual inductor is connected to the FPGA through the conditioning circuit and the high-speed AD module; the analog fault traveling wave signal acquired by the mutual inductor is processed by a conditioning circuit and then input into a high-speed AD module for processing, and the conditioning circuit carries out resistance voltage division processing, transformer differential processing and RC low-pass filtering processing in sequence;

the FPGA control program comprises the following contents:

ALTLVDS _ RX module: the module is received by an IP (Internet protocol) nuclear tool, and the module inputs LVDS serial signals output by the high-speed AD module and outputs the LVDS serial signals into serial-to-parallel data;

a Package _ ctrl module: the module packs the received 6-channel data according to a specified frame format and sends the data to a CPU (central processing unit) through an FIFO (first in first out) cache; the input of the module is LVDS for receiving data output by an IP core, and the output is packed data and an rx _ data _ align signal;

ad _ ctrl block: the module is used for controlling the high-speed AD module to output test codes for synchronous test according to requirements; the input is a control signal of the CPU, and the output is a control signal of the high-speed AD module;

main _ ctrl module: the module is used for transferring all data and plays a role in coordination and control among interfaces; the module inputs include: the AD sampling data, the memory reading data and the reading control signal from the CPU are packed; the module outputs include: the AD sampling data which are sent to the memory cache after being packaged, the control signal of the memory and the data which are read from the memory and sent to the CPU;

sdram _ ctrl block: the module is used for controlling the memory; the module inputs include: the main control module sends a read-write control signal and read data; the module outputs include: read/write control signals for the memory, and data written to the memory.

As an option, the voltage and current acquisition module further comprises a low-speed AD module and a multi-path analog switch circuit, and the mutual inductor, the low-speed AD module and the multi-path analog switch circuit form 18 paths of voltage and current data acquisition channels. Preferably, the multi-path analog switch circuit adopts an ADG409 chip, and 3 groups of ADG409 chips are adopted to expand into 18 paths of analog signals; the low-speed AD module adopts an AD7656 chip, 18 paths of analog signals are input into the AD7656 chip after being processed by a filter circuit, the filter circuit firstly utilizes a low-pass filter formed by a capacitor and an operational amplifier which are connected in parallel to process, and then a voltage follower formed by the operational amplifier is used for processing. The low-speed AD is used for protecting data acquisition during measurement, 18 paths of analog signals need to be filtered and conditioned before being sent to the AD7656 for data acquisition, and a conditioning circuit mainly comprises an operational amplifier; because the output is the voltage value at the two ends of the capacitor, a low-pass filter is formed, and then an operational amplifier is connected to form a voltage follower with deep negative feedback; the circuit has the characteristics of high input impedance and low output impedance, and isolates a signal source and a load.

As an option, the high-speed AD module adopts an AD9257BCPZ-40 chip, analog fault traveling wave signals acquired by the mutual inductor are processed by a conditioning circuit and then input into the AD9257BCPZ-40 chip for processing, and the conditioning circuit carries out resistance voltage division processing, radio frequency transformer ADT4-1WT differential processing and RC low-pass filtering processing in sequence. The high-speed AD is used for collecting fault traveling wave signals, and because the input signals are single-ended and the input of the AD9257 is differential, the input signals need to be subjected to single-ended-to-differential conversion; the method comprises the steps of dividing voltage through resistors, compressing the amplitude by 4 times in a radio frequency transformer ADT4-1WT, converting the voltage into a differential signal, and then obtaining an input signal meeting the requirement by an RC low-pass filter circuit.

As an option, the power module adopts a switching power supply TPS54620 chip to convert and provide voltages of +/-12V, 5V, 3.3V, 2.5V, 1.8V and 1.2V, and adopts a linear voltage-stabilized power supply ADP1706ARDZ-1.8-R7 chip to convert and provide a voltage of 1.8V. The switch voltage-stabilized power supply adopts a TPS54620 chip to convert the voltage into 3.3V, 2.5V, 1.8V and 1.2V, and simultaneously adopts a linear voltage-stabilized power supply ADP1706ARDZ-1.8-R7 chip in order to obtain a stable 1.8V power supply high speed AD 9257.

As an option, the distance measuring system further comprises an upper host and a display screen connected with the upper host, the CPU is further connected with a positioning module and a wireless network transmission module, and the CPU is in communication connection with the upper host through the wireless network transmission module. As mentioned above, define the ranging system of constituteing such as CPU, FPGA, record ripples memory and voltage electric current collection module as the range finding terminal, and host computer and display screen etc. constitute host computer, so, the CPU of 1 at least range finding terminal can be based on IP agreement's internet communication with host computer of host computer at host computer, with data real-time transmission to host computer on.

Due to the adoption of the technical scheme, the invention has the following beneficial effects:

the invention relates to a power traveling wave fault location system, which is characterized in that a mutual inductor acquires fault voltage and current traveling waves on a line, 6 paths of analog voltage and current signals are converted into digital signals through high-speed AD (analog-to-digital) conversion and sent to an FPGA (field programmable gate array), a loaded SDRAM (synchronous dynamic random access memory) is used for storing traveling wave signals, and a CPU (central processing unit) reads traveling wave signal data in a buffer area and processes the traveling wave signal data to calculate the fault distance.

Drawings

FIG. 1 is a system block diagram of example 1 of the present invention.

Fig. 2 is a hardware layout of example 1 of the present invention.

Fig. 3 is a circuit diagram of a CPU crystal oscillator of example 1 of the present invention.

Fig. 4 is a circuit diagram of a CPU configuration of example 1 of the present invention.

FIG. 5 is a CPU BOOT start-up circuit diagram of example 1 of the present invention.

FIG. 6 is a circuit diagram of EPM3128ATC100 module of example 1 of the present invention.

Figure 7 is a circuit diagram of an SDRAM memory circuit of example 1 of the invention.

Fig. 8 is a circuit diagram of a low-speed AD module of example 1 of the present invention.

Fig. 9 is a circuit diagram of a multi-way analog switch of example 1 of the present invention.

Fig. 10 is a circuit diagram of a filter circuit of example 1 of the present invention.

Fig. 11 is a circuit diagram of a data buffer circuit of example 1 of the present invention.

Fig. 12 is a circuit diagram of a high-speed AD module of example 1 of the present invention.

Fig. 13 is a circuit diagram of a conditioning circuit of example 1 of the present invention.

FIG. 14 is a circuit diagram of the FPGA main string configuration of example 1 of the present invention.

Fig. 15 is an open light amount input circuit diagram of example 1 of the present invention.

Fig. 16 is an open light output circuit diagram of example 1 of the present invention.

Fig. 17 is a TPS54620 power conversion circuit diagram of example 1 of the present invention.

FIG. 18 is a power conversion circuit diagram of ADP1706ARDZ-1.8-R7 of example 1 of the present invention.

Fig. 19 is a circuit diagram of a power supply filter circuit of example 1 of the present invention.

FIG. 20 is a schematic block diagram of FPGA programming of example 1 of the present invention.

Fig. 21 is a serial-to-parallel conversion framework diagram of example 1 of the present invention.

Fig. 22 is a block diagram of a ping-pong buffer module of example 1 of the present invention.

Fig. 23 is an SDRAM control flow of example 1 of the present invention.

FIG. 24 is a pin connection diagram between the FPGA and DSP of example 1 of the present invention.

Fig. 25 is a system block diagram of example 2 of the present invention.

Detailed Description

Examples

Referring to fig. 1-2, the traveling wave fault location system for electric power according to example 1 includes a CPU, an FPGA, a wave recording memory, a voltage and current acquisition module, and a power supply module for supplying power, where the voltage and current acquisition module is connected to the FPGA, the wave recording memory is mounted on the FPGA, and the FPGA is connected to the CPU; the voltage and current acquisition module comprises a mutual inductor, a conditioning circuit and a high-speed AD module, and the mutual inductor is connected to the FPGA through the conditioning circuit and the high-speed AD module; the analog fault traveling wave signal acquired by the mutual inductor is processed by the conditioning circuit and then input into the high-speed AD module for processing, and the conditioning circuit performs resistance voltage division processing, transformer differential processing and RC low-pass filtering processing in sequence.

Referring to fig. 25, the distance measuring system of example 2 further includes an upper host and a display screen connected thereto, the CPU is further connected to a positioning module and a wireless network transmission module, and the CPU is in communication connection with the upper host through the wireless network transmission module; as mentioned above, define the ranging system of constituteing such as CPU, FPGA, record ripples memory and voltage electric current collection module as the range finding terminal, and host computer and display screen etc. constitute host computer, so, the CPU of 1 at least range finding terminal can be based on IP agreement's internet communication with host computer of host computer at host computer, with data real-time transmission to host computer on. The following will be specifically explained.

The CPU is OMPL _138 and is composed of a DSP + ARM dual core, and is mainly used for realizing a ranging algorithm. The FPGA is mainly used for high-speed data acquisition and storage.

The OMPL _138 chip is an ARM + DSP dual-core processor based on DaVinci (DaVinci) technology. A32-bit ARM926EJ-S system control core of a simplified instruction set and C6748 DSP data with powerful computing power are adopted as the computing core. The OMPL _138 processor chip adopts a non-equivalent heterogeneous dual-core design mode, and the ARM and the DSP communicate in a memory sharing mode to perform data interaction. The ARM core is used as a General Purpose Processor (GPP) and is responsible for the hardware management part of the whole system, and is the main control core of the system. The DSP core acts as a coprocessor and can be logically considered as a peripheral of ARM. ARM can carry out data read-write operation to DSP through internal bus, and this kind of structure makes data transmission rate high, and the error rate is little. In addition, OMPL _138 of TI integrates two processor cores on the same processor, greatly simplifying the development work of hardware circuit designers. Meanwhile, a C6748 DSP core built in the OMPL _138 chip supports double floating point operation, and the operation result is more accurate than that of a single floating point digital processor. Due to the adoption of a Harvard structure, the instruction and data can be read simultaneously, and a hardware multiplier special for a C6748 DSP is matched, so that the calculation efficiency is greatly improved, and hardware support is provided for the performance and real-time requirements of the system.

Besides the double processing cores, the chip is also provided with abundant peripheral resources. In the aspect of serial communication, a serial communication interface supporting serial communication protocols such as McBSP, I2C, SPI, UART and the like is also arranged; a general purpose parallel port (uPP); supporting USB2.0OTG and USB1.1 control interfaces; an 10/100Mb/s EMAC Ethernet communication interface integrated with an MDIO module; SATA controller, LCD controller interface; the DDR2 memory controller, the EMIFA flash memory interface and the like are arranged, so that the memory expansion is facilitated. The ARM core and the DSP core can independently perform access operation on the peripheral devices. The advantages of the OMPL _138 processor chip make the application market of the processor chip wide. The crystal oscillator, configuration circuit and BOOT start-up circuit in the OMPL _138 module of the system are respectively shown in FIGS. 3-5.

Referring to fig. 6, EPM3128ATC100 module circuitry. The system uses CPLD (Complex Programmable Logic device) EPM3128ATC100 chip of ALTER company, which contains 2500 Logic gates, 128 macro cells, 80 IO input/output ports, and 100 pins in total. The EPM3128ATC100 module is used for processing digital quantity converted by low-speed AD7656, and is used for controlling 16 remote signaling input, 10 paths of control output and frequency measurement, such as starting detection and the like. The download circuit is similar to the OMAP-L138 configuration circuit described above and will not be described here. The programmable Logic device PLD (programmable Logic device) realizes the Logic function of a certain digital system through specific software development tool programming, and has the characteristics of low power consumption, high speed, large capacity, high reliability and the like.

Fig. 7 is a schematic diagram of an SDRAM memory circuit mounted on OMPL _138, and is mainly used for protecting data storage during measurement. Compared with SRAM, SDRAM is one kind of synchronous dynamic random access memory with great capacity, low cost, high security and reliability and high storage density. The DDR2MT46H32M16LFBF-6 of the Meiguang Micron adopted by the memory chip for protection measurement is supplied with power by 1.8V, 4 BANK blocks have data storage capacity of 512Mb, and the memory chip is enough for protection measurement.

The SDRAMs mounted on the FPGA also adopt Meiguang SDR MT48LC16M16A2B4-6A, 3.3V power supply and 256Mb storage capacity. The method is mainly used for storing and recording fault traveling wave signals acquired by high-speed AD, and the storage capacity is high, so that the system requirements can be met. This SDR MT48LC16M16A2B4-6A circuit is connected in a manner similar to the SDRAM above.

Referring to fig. 8, a low-speed AD7656 circuit module, in which a low-speed ADC in the system is used for protecting data acquisition during measurement, an ADI (adno) AD7656 chip, 64 pins, LQFP package, and a low-power successive approximation type (SAR) ADC are used. The power supply is carried out by +/-12V double power supplies, the 6-channel independent ADC is adopted, and true bipolar analog input is realized. Optional range of measurement: 10V and 5V. 250KSPS throughput rate, typical power consumption 140 mW. The AD7656 has a 2.5V on-chip reference voltage source built in. When the falling edge of the CS control line is active, the transition is initiated by the CONVST pulse and the input signal begins to be sampled. The CONVSTA, CONVSTB, CONVSTC pins are connected so that the input V1-6 (six channels) can be sampled simultaneously. When the BUSY signal line is active low, it indicates the end of the AD conversion. RESET is a RESET pin. According to the amplitude of the input signal, the measurement range of +/-10V is selected as the low speed A7656 in the system.

Referring to fig. 9, which is a schematic diagram of a multi-path analog switch circuit, the whole system needs 18 low-speed acquisition channels for inputting analog signals, and mainly measures three-phase current and voltage, battery voltage, energy storage capacitor voltage, and the like. But each slice AD7656 has only 6 channel inputs, so three sets of multi-channel analog switch circuits ADG409 extension channels need to be added. The ADG409 is powered using a ± 12V dual supply, addresses are determined by 2-bit binary address lines a0 and a1, and one of the 4 differential input pairs of inputs is switched to a common differential output for output. The EN input of ADG409 acts as a switch to disable or enable the device, which disables all channels. In the system, the EN terminal is connected to positive 12V VDD, and all channels are enabled. The 3 groups of ADGs 409 can be expanded into 18-way channels to meet system requirements.

As shown in the conditioning circuit of fig. 10, before the 18 analog signals are sent to the AD7656 for data acquisition, the signals need to be filtered and conditioned, and mainly include an operational amplifier. Because the output is the voltage value at two ends of the capacitor, a low-pass filter is formed, and then an operational amplifier forms a deep negative feedback voltage follower. The circuit has the characteristics of high input impedance and low output impedance, and isolates a signal source and a load.

Such as the buffer circuit shown in fig. 11. In this system, a 16-bit bus transceiver, OMPL _138 and the CPLD, data needs to be buffered for communication. The parallel 16-bit data after AD conversion already occupies 16 pins of the CPLD EPM3128ATC100 chip. EPM3128ATC100 has a total of 100 pins, of which there are only 80 IO input/output ports, and in order to save pins, the pins occupied by the AD-converted parallel 16-bit digital quantity are multiplexed for communication with OMPL _ 138. The bus transceiver with 74LVCH162245A 16 bits of Philips is selected as a multi-way analog switch to play a role in bus isolation. OE is the enable, active low. The high and low levels of DIR determine the data transmission direction of the bus. The chip has two DIR control pins so that it can act as two 8-bit bus transceivers, and also as a 16-bit bus transceiver.

FIG. 12 is a circuit diagram of an AD9257 module, in which a high-speed AD in the system is used for collecting fault traveling wave signals, an ADI AD9257 chip is adopted, an 8-channel, 14-bit, 40MSPS/65MSPS analog-to-digital converter (ADC, 64-pin LFCSP package) is adopted, an on-chip sample-and-hold circuit is built in the chip, the chip is specially designed for the purposes of low cost, low power consumption, small size, easiness and the like, the conversion rate can reach up to 65MSPS, the chip has low power consumption characteristics and excellent dynamic performance, 1.8V single power supply is adopted for supplying power, each channel is supported to enter a power saving state independently, when all channels are forbidden, the typical power consumption is lower than 2 mW. AD9257 differential output conforms to ANSI _644 standard, the connection with LVDS receiver interfaces in custom ASIC and FPGA is convenient, a stable and accurate 1.0V reference voltage source is also built in the chip, through a large amount of research by predecessors, the frequency spectrum of transient traveling wave signals are generally distributed in a range of 10-350 kHz, the sampling frequency is equal to or greater than twice the highest frequency of the signal, and theoretically, the sampling frequency of the AD is at least 700 kHz. However, in practical applications, the sampling rate of AD is far greater than the theoretical value. The AD9257 selected is as high as 65MSPS, and a crystal oscillator with 20MHz is used to meet the system requirement.

As shown in fig. 13, which is a signal conditioning circuit at the front end of a high-speed AD9257, the input signal is single-ended, and the input of the AD9257 is differential, so that the input signal is subjected to single-ended to differential conversion. Differential input voltage 2V Vpp, common mode voltage 0.9V. However, the amplitude of the simulated fault traveling wave signal obtained by the CT is large, the signal is processed to be reduced to a 3.53V effective value, the signal cannot be directly sent to the AD9257 to be directly collected, the front-end signal needs to be conditioned and attenuated, and the reduced signal amplitude meets the input requirement of the AD 9257. The method comprises the steps of dividing voltage through resistors, compressing the amplitude by 4 times in a radio frequency transformer ADT4-1WT, converting the voltage into a differential signal, and then obtaining an input signal meeting the requirement by an RC low-pass filter circuit.

The system adopts a Cyclone IV series FPGA chip of ALTERA company, and the product model is EP4CE10F17C 8N. BGA package, 256 pins. It has 10320 logic cells; CLB (configure Logic blocks) array number is 645 blocks; the maximum number of I/O supported by the users is 179; the total RAM bits is 423936 bits. The flash is configured to be M25P128, and the external crystal frequency is set to be 20 MHz. The device has the function of directly receiving LVDS standard signals and a powerful data processing function. The Cyclone IV series chip mainly comprises an input/output unit IOB, a configurable logic Block CLB, a digital clock manager DCM and a Block RAM.

(1) Input/output interface IOB

The input and output unit IOB is a physical interface between the interior of the FPGA and an external circuit, and completes the driving and matching of input and output under different electrical characteristics. The I/O ports inside the FPGA can be divided into a plurality of groups (BANK), and each group (BANK) can be independently configured with different I/O standards. The I/O criteria are determined by connecting VCCIO and VREF to different voltages.

(2) Configurable logic Block CLB

The CLB is a basic logic unit in the FPGA chip, is used for realizing various logic functions, is composed of a plurality of highly flexible switch matrixes, and has configurability. The switch matrix contains 4 inputs, a multiplexing switch, and flip-flops. The logic function of most of combination and sequential circuits can be realized, and the relevant registers are configured.

(3) Digital clock manager DCM

The output frequency meeting the system requirement is obtained through the configuration of a clock manager DCM and a PLL phase-locked loop in the FPGA, and the DCM can also adjust the output phase of the clock, provide accurate clock synthesis and reduce the jitter of the clock.

(4) Embedded block RAM (Block RAM)

A plurality of embedded block RAMs are embedded in the FPGA, so that the application range of the FPGA is expanded, and the flexibility is improved. After the call, the memory can be configured into a single-port or double-port RAM, a Content Address Memory (CAM), a cache FIFO and other common memory structures. In addition, a plurality of embedded block RAMs can be cascaded to obtain larger RAM space, capacity is expanded, use is convenient, and flexibility is high.

The FPGA in the system selects an EP4CE10F17C8N chip, and has power-off volatility based on a RAM (random access memory) process. When the system is powered on and restarted, the on-chip RAM is reconfigured to initialize the circuit. The FPGA will then enter a user mode of operation to perform the logic functions of the circuit.

In the system, the FPGA circuit configuration of the coprocessor is realized by adopting two modes: 1. JTAG mode, 2, master serial mode. The JTAG mode configuration is similar to the main CPU and CPLD and is not cumbersome here. The configuration chip selected in the master serial mode is M25P128, a program can be solidified into the M25P128 through a JTAG port, and after the system is powered on, the M25P128 configures the FPGA. Fig. 14 is a circuit diagram in its main string configuration mode.

Fig. 15 is a partial schematic diagram of a switching value input module, which has 16 remote signaling switching value inputs for receiving and executing master station remote control commands and receiving master station time setting commands. When DIx is equal to high, transistor Q is turned on and DI _ x input to CPLD is pulled down to low. Fig. 16 is a schematic diagram of the switching value output module. The switch has 10 paths of switching value control output and is used for manually switching on and off and automatically reclosing to realize a protection function. The control output adopts an optical coupler for photoelectric isolation, when the output control end DO _ x of the CPLD outputs a low level, the left light emitting diode emits light through current, and the photosensitive element generates current after being illuminated, so that the CE end, namely the output end, is conducted.

The power supply plays an important role in the whole system to supply power to each module of the circuit. Once the power circuit has a problem, no power supply or insufficient power supply will result in the whole system not working normally. The chip may also be burned if over-voltage occurs. Therefore, the performance of the power supply directly affects the working state and efficiency of the whole system. According to the state difference of the regulating tube, the DC-DC conversion power supply comprises two types, namely a switching stabilized power supply and a linear stabilized power supply.

The power supplied to the core board in this system is 12V and 5V. The power supply of the 24V power supply of the function board is transformed. The core board comprises a plurality of groups of power supplies: the main CPU OMPL _138 chip requires 3.3V, 1.8V and 1.2V; the coprocessor FPGA chip needs a plurality of groups of power supply voltages, such as 3.3V, 2.5V and 1.8V, and 1.2V kernel power supply voltage; AD7656 and ADG409 chips need plus or minus 12V for power supply; SDRAM memory chips also require 1.8V. In order to meet the voltage requirement of the system, an externally provided power supply needs to be converted to convert a high voltage into a low voltage.

In the design of the system, in order to obtain the stable power supply, the power supply provided by the function board is converted into the required lower voltage to supply power to each module. The power conversion module is designed by comprehensively considering the aspects of efficiency, power consumption, interference resistance, output current and the like. Finally, according to the requirements of the system, one part adopts a switch voltage-stabilized power supply, and the other part adopts a linear voltage-stabilized power supply. The switch voltage-stabilized power supply adopts a TPS54620 chip to convert the voltage into 3.3V, 2.5V, 1.8V and 1.2V, and simultaneously adopts a linear voltage-stabilized power supply ADP1706ARDZ-1.8-R7 chip in order to obtain a stable 1.8V power supply high speed AD 9257. By utilizing the two voltage conversion chips, various voltages required by the system can be obtained, and the normal work of the system is guaranteed.

The switch power supply chip TPS54620 is mainly characterized in that: the maximum output current can reach 6A, the input voltage range is wide, 4.5V-17V voltage can be input, the static current is cut off when the voltage is reduced to 2uA, and overload protection and the like are realized. The circuit diagram is shown in fig. 17.

The output voltage value of the voltage reduction chip TPS54620 can be changed by adjusting a voltage division resistor R at an output end, 3.3V, 2.5V, 1.8V and 1.2V are output through the TPS54620 in the system, and the formula is as follows:

wherein V_REF＝0.8V；

According to the above formula, to obtain the required 3.3V, the resistor R1 is set to 1K, the resistor R2 is set to 3.24K, and other voltages are similar and are not redundant. The input and output ends of the voltage reduction chip are connected with decoupling capacitors for filtering and preventing interference so as to provide required stable voltage.

The linear voltage-stabilizing power supply chip ADP1706ARDZ-1.8-R7 is mainly characterized in that: fast transient response, excellent line and load regulation, and has wide input voltage range, low quiescent current, low noise, high PSRR. 1.8V output, maximum 1A output, ± 2.5% accuracy, the schematic diagram is shown in fig. 18.

Because noise interference is large in the power transmission line, in order to obtain more stable voltage to supply power to each module, filtering processing is carried out on a power supply. Therefore, a small capacitor of 0.1uF and a large capacitor of 10uF are arranged at each module power supply of the circuit, the small capacitor is used for filtering high-frequency noise waves, and the large capacitor is used for filtering low-frequency noise waves. Part of the power filter circuit is shown in fig. 19.

The system can realize various logic functions in the ranging process, namely the data processing process in a CPU, an FPGA and the like by adopting the conventional existing technology. Of course, the following schemes may be employed.

In the system, the FPGA mainly finishes data acquisition and storage, transmits the data to the main CPU, and realizes a ranging algorithm in the main CPU. The whole FPGA development process is completed in the Quartus II development environment of ALTERA company.

The AD9257 is a high-speed AD conversion chip, is mainly used for data acquisition, quantization and coding, and converts the data into a 14-bit serial digital signal and transmits the signal to the FPGA. In the system design, the FPGA samples 6 channels of AD data in real time at a sampling frequency of 20 MHz. And a control signal given out inside the FPGA is used for starting the AD9257, recording and collecting fault traveling wave data, and performing serial-parallel conversion on the data collected by each channel by fully utilizing the high-speed processing capability of the FPGA. The buffered traveling wave data is uninterruptedly stored by SDRAM, and the size of the buffer area can store 60ms sampling data. The SDRAM is divided into 4 independent buffer areas, the current buffer area is determined by an IO port of a main CPU, if the main CPU changes the state of the IO port, the buffer area is required to be replaced after 30ms delay, and the storage address of the last data in the buffer area is stored at a designated position. The programming realizes a first-in first-out queue (FIFO) read-write module which is used for ensuring that the read-write and the read-out are not influenced mutually, so that the data has no error.

The FPGA control program is designed in a modularized mode, wherein the basic principle of module division is mainly based on functions, and sometimes division is carried out according to data streams. For the design, data flow is mainly taken as a consideration factor. Aiming at the high-speed data acquisition technology required by the system, an FPGA part software design block diagram as shown in FIG. 20 is established.

The functions of the modules are described correspondingly according to the flow direction of the data stream as follows:

ALLVDS _ RX: the module is an IP core tool carried by software, and a common receiving mode cannot be used due to the fact that the code rate of the high-speed LVDS signals is high. Must be received through a special IP core tool. The module inputs LVDS serial signals output by the AD9257 and outputs serial-to-parallel data.

Package _ ctrl: the module has the main functions of packing the received 6-channel data according to a specified frame format and sending the data to the main control module through the FIFO buffer. In addition, the received data needs to be analyzed, and the received data is controlled by the BITSLIP function to realize the synchronization of the received words by the IP core receiving tool. The module has the input of LVDS for receiving data output by the IP core and outputs the data after being packaged and rx _ data _ align signals (the IP core outputs shift pulses).

Ad _ ctrl: the module is mainly used for controlling the AD9257 chip to output test codes for synchronous testing according to requirements. The input is a control signal of the main control module, and the output is a control signal of the AD 9257.

Main _ ctrl: the module is the transfer of all data and mainly plays a role in coordination and control among interfaces. The inputs to the module mainly include: the packed AD sampling data, SDRAM read data and a received reading control signal from a main control DSP; the output of this module mainly includes: and the AD sampling data, the control signal of the sdam and the data read from the sdam and sent to the main control DSP are sent to the SDRAM cache after being packed.

Sdram _ ctrl: the module is mainly used for controlling two sdram chips and is used for realizing the cache 60ms function and the requirements of 4 partitions in the technical requirements. The main inputs of the module include: the main control module sends a read-write control signal and read data; the module mainly outputs including: and the control signal of the sdram, and the data written into the sdram.

The FPGA is mainly used for high-speed acquisition of data, sampling, quantizing and coding analog signals by controlling a high-speed AD9257 chip, and finally reading digital quantity signals output by AD.

The data transmission between the FPGA chip and the high-speed ADC adopts a source synchronous communication technology. The maximum sampling frequency of the AD9257 reaches up to 65MHz, and the transient traveling wave analog signals processed at the front end are collected at the sampling rate of 20MHz in the system and converted into 14-bit serial data through quantization coding. And the LVDS is sent to the FPGA for storage through the low-power-consumption differential serial interface LVDS. When the sampling rate is 20MHz, the data rate of each serial stream is equal to 280Mbps, i.e., 14 × 40 MHz. If the sampling rate is equal to 65MHz, the data rate of each serial stream is up to 910 Mbps. The high speed AD9257 chip provides a data capture clock (DCO) and a frame capture clock (FCO), both output clocks better capturing data. FCO is used to indicate the start of a frame of data, equal to the sampling clock rate. The DCO is used to clock each bit of output data, which is equal to 7 times the sampling clock. Data is output from the AD9257 differential output bit by bit and is captured only on the rising and falling edges of the DCO, which also supports double rate (DDR) capture.

Because the internal reference voltage VREF that high-speed AD9257 chip adopted is 1V, and the sampling signal voltage amplitude scope is: 1V, and with a 14-bit resolution, the LSB (Least Significant bit) size is about 0.122 mV. The data output format after analog-to-digital conversion is shown in table 1 below

TABLE 1 analog-to-digital conversion Table

Analog signal V	Offset binary output mode	Binary complement mode
			-1V	00 0000 0000 0000	10 0000 0000 0000
0V	10 0000 0000 0000	00 0000 0000 0000
			1V	11 1111 1111 1111	01 1111 1111 1111

The selection of the chip output mode depends on an output data format selection pin (DFS), if the DFS pin is connected with a high level AVDD, the output mode is in a binary complement format, and if a default mode is adopted, the DFS pin of the chip is connected with a low level GND, the output mode is in an offset binary format. The system is connected with GND (default), namely an offset binary output mode is adopted.

Because each channel of the high-speed AD9257 is in a serial data output format, the common serial to parallel conversion module is realized by FPGA programming by using a mode of consuming FPGA hardware resources to exchange higher data throughput rate, so that the processing speed of data stream is increased, and better data storage is ensured. The serial-parallel conversion part mainly comprises a clock control module and a plurality of shift registers. The serial-parallel conversion frame diagram is shown in fig. 21.

Due to the difference in clock frequency of high-speed acquisition, data storage and DSP core read data rate, data buffering must be performed through an asynchronous FIFO. The FIFO is a First-In First-Out queue (First In First Out), and has two main functions: 1. data caching between different clock domains, and 2, data matching between different data bit widths. Altera corporation provides FIFO IP cores so that users can develop quickly. The FIFO core is divided into three types of SCFIFO, DCFIFO and DCFIFO _ MIXED _ WIDTHS. SCFIFO (Single Clock FIFO) is a single Clock first-in first-out queue. Dcfifo (double Clock fifo) is a double Clock fifo queue with equal data bit width and having two Clock inputs rdclk and wrclk, rdclk for synchronous read signals and wrclk for synchronous write signals. The other is DCFIFO _ MIXED _ width, which is also double clocked and the input and output data bit width may be unequal. The FIFO is generated by the RAM inside the FPGA. In the design, a double-clock IP core is adopted to realize asynchronous FIFO, a FIFO parameter editor can be selected from Megawizard Plug-In Manager under a TOOLS toolbar In quartz II to generate the required FIFO, and interface signals of the DCFIFO are illustrated as table 2:

TABLE 2 interface signals for DCFIFO

From the foregoing, the data size of the traveling wave fault recording is very large, and reaches 100.8 Mb. Generally, the on-chip memory is very small, and if only the on-chip memory such as RAM/FIFO is not enough to store, a large-capacity SDRAM is needed to transmit data. Because a single SDRAM can only read or write at the same time, two SDRAM are needed to perform ping-pong cache on data in order to keep the data complete, so that the real-time requirement of the system can be ensured, traveling wave signals on the power transmission line are continuously stored, and the data cannot be lost under any condition.

Fig. 22 shows a ping-pong buffer module, which determines to buffer data input into the FIFO1 into the SDRAM1 or the SDRAM2 by selecting "ping-pong 0" or "ping-pong 1" through the ping-pong buffer controller, and stores the data alternately, so that the read and write operations are not affected by each other. Similarly, the ping-pong buffer controls the output, so that the data reading and writing can be ensured not to be influenced by each other and not to be lost.

The SDRAM signal lines are mainly classified into address signals (a0 to a12), data signals (DQ0 to DQ15), and control signals. And the driving timing is complicated. The main control lines include CLK (clock signal input line), CK (clock enable line), CS (chip select signal line), RAS (row address select line), CAS (column address select line), WE (write enable line), BA0 to BA1(BANK address input signal line), and the like. At present, it is acknowledged that the storage life of capacitance data in a memory is only 64ms at most, so that the capacitor array must be refreshed by charging and discharging during operation, and read and write operations can be performed on a designated address space in a manner of designating an address line. When driving SDRAM, timing control usually uses two very important logic control units, namely a command decoder and a mode register. The operating commands are determined by the control line inputs CS #, RAS #, CAS #, WE #. Table 3 is a command set for basic operation of SDRAM.

TABLE 3 Command set for SDRAM base operations

The Mode Register (MR) is programmed by a load Mode Register command to save configuration information so that data is not lost before reprogramming or when power is lost. Each page of the MT48LC16M16A2B4-6A chip has 256 memory cells, and all the memory cells in a row of L-Bank can be transferred all the way through. This approach is called full page (FullPage) burst transfer.

The SDRAM controller of the system has a complex driving time sequence and mainly comprises five functional modules, namely an initialization and configuration module, an interface control module, a refresh control module, an address generation module and a command control module, wherein the initialization and configuration module mainly has the function of initializing and configuring the SDRAM. The interface control module mainly functions to translate the CMD commands into corresponding command requests, namely CMD decoding. And the device is also used for receiving command requests sent by the refreshing module and the initialization and configuration module. The main function of the data refresh module is to generate refresh command requests for refreshing data using a timer, which can be implemented using a counter. In order to prevent the data in the memory from being lost for a long time, the SDRAM must be refreshed at regular time intervals. The command control module is mainly used for receiving various command requests sent by the interface control module, arbitrating according to a certain priority principle (LMR > refresh > other command requests) and preferentially executing command requests with higher priority. At the present moment, the highest priority command request will be translated into the control signals required by the SDRAM, while the data is transferred over the data lines. The address generation module mainly completes the conversion of the address sent by the external address line into a row address, a column address and a BANK address required by the read-write operation of the SDRAM.

After the SDRAM is powered on, the SDRAM is first initialized and configured to complete the configuration of the mode register, so as to ensure that the SDRAM can operate according to the expected operation mode, and after the MT48LC16M16A2B4-6A is powered on, at least 100 and 200us are needed to wait for configuring the mode register. After waiting for the end, more than one idle operation command is needed to be executed, and the waiting time is prolonged as much as possible, so that the SDRAM enters a stable period. If the time is too short, the Mode Register (MR) may not be configured successfully. Because the L-Bank block of the SDRAM is in a capacitor structure, the time upper limit of data storage of the capacitor is 64ms, and power failure is easy, all ranks need to be refreshed at regular time to prevent data loss. And performing pre-charging treatment on all L-Bank blocks after stable startup. After waiting at least 8 pre-refresh cycles, the internal mode register is configured accordingly. After the block is activated, read/write operations to the SDRAM may begin. The SDRAM operation flow chart is shown in fig. 23.

According to the real-time requirement of the system, the bandwidth parameter needs to be considered when reading and writing the SDRAM. Bandwidth required for reading and writing data: 20M 166 1920 Mbits. The selected SDRAM has the clock of 166M, the bit width of 16 bits and the bandwidth of 166 × 16 ═ 2656Mbits >1920Mbits, and meets the speed requirement.

Data transfer between OMPL _138 and the FPGA uses a 32-bit LOCALBUS or EMIF interface. And the EMIF interface control module is used for transmitting traveling wave data loaded in SDRAM on the FPGA to a DSP core of the OMPL _138 for processing, and calculating the fault distance in the line. Fig. 24 is a connection diagram between the FPGA and the DSP.

The address line and the data line of the EMIF interface are both 16 bits, namely EMA [15.. 0] and EMA _ D [15.. 0], respectively. According to the requirements of an EMIF interface in an OMAP-L138 DSP core, selecting EMA _ CS [0] from a chip selection space. EMIFA has an operating clock EMA _ CLK up to 100MHz, an EMA _ SDCKE signal is used for clock enabling, an EMA _ RAS signal is used for row address selection, an EMA _ CAS signal is used for column address selection, columns are 8, 9, 10 and 11 selectable, and a/EMA _ WEN _ DQM [1] signal is a flag bit of write enabling/high eight-bit data. the/EMA _ WEN _ DQM [0] signal is the flag bit for the write enable/low eight bits of data. the/EMA _ WE signal is write enable and is used as a distinguishing signal for writing data in SDRAM on the FPGA into the DSP.

The DSP needs to write data into the FPGA through three steps: setup (Setup), write (Strobe), and Hold (Hold). The time that the chip select/EMA _ CS [0] falling edge is active to/EMA _ WE write enable falling edge is active is the setup time (setup). the/EMA _ WE is set low for a period of time to ensure that there is sufficient time for data transmission. The time interval during which the/EMA _ WE signal line is set low is the data retention time. The read operation time sequence is approximately similar to the write time sequence, the DSP core in the OMPL _138 reads data in the co-processing FPGA and needs to be established, written and maintained, and the time length required by each stage is almost consistent with the time length required by the write time sequence.

The system control component is arranged at a bus port of the power transmission line and is mainly used for collecting, processing and storing traveling waves. Fault voltage and current traveling waves on a line are acquired by a mutual inductor, voltage and current signals of 6 paths of analog quantity are converted into digital signals through high-speed AD (analog-to-digital) conversion and sent to an FPGA (field programmable gate array), and a loaded SDRAM (synchronous dynamic random access memory) is used for storing traveling wave signals. And the main CPU reads the traveling wave signal data of the buffer area through a 32-bit LOCAL BUS, and processes and calculates the fault distance. And can send the data to the external hard disk through USB storage equipment and keep or send to the host computer through the network port and show. The system is provided with a low-speed AD chip for measurement protection and frequency measurement. Meanwhile, a plurality of power conversion chips are arranged in the system and are used for meeting different power supply requirements of each module and enabling the whole system to normally operate. The following functions can be realized:

1. measurement function: the frequency, three-phase current and voltage, zero-sequence current and voltage, active power, reactive power, switching state, battery voltage, energy storage capacitor voltage and the like can be measured.

2. And (4) protection function: the protection circuit has the protection functions of instantaneous quick-break, time-limited quick-break, timed overcurrent, directional overcurrent, single-phase grounding, overvoltage, low voltage, open phase, control loop disconnection alarm, PT disconnection alarm, capacitance voltage low alarm and the like.

3. And (4) control functions: can realize manual divide-shut brake, automatic reclosing, receive and carry out main website remote control command, accept main website to time command or big dipper to time.

4. Fault positioning: and line fault detection is realized by adopting a single-end electric quantity traveling wave fault location method, and fault location and location are carried out.

5. Positioning the terminal equipment: and the position of the terminal equipment can be accurately positioned by installing a GPS or Beidou satellite navigation.

6. The communication function is as follows: providing RS232/RS485 and RJ 45 (crystal head) Ethernet ports; the communication protocol can be flexibly configured according to the needs and supports various communication protocols and derivative protocols such as 101, 104 and the like; and an NB-IOT communication mode and an MQTT Internet of things communication protocol are supported.

7. Setting parameters: the current protection constant value, the time constant value, the low voltage locking, the current direction, the mobile phone number, the CT transformation ratio, the voltage grade and the clock in the system can be set.

8. And (4) display function: the display system measures data and the working state thereof, and simultaneously displays the clock, thereby facilitating human-computer interaction.

9. A recording function: the system has a fault recording function and an event sequence recording function. When the system has power failure or communication interruption and other emergencies, the data can be stored for a long time without loss.

10. Electric locking: when the controller detects that the voltage input end is electrified and the isolating switch is in an opening (grounding) position, the closing function of the controller is locked. Has the function of residual pressure locking.

11. And (4) encryption function: an encryption chip is arranged in the system, so that the system safety is ensured. The specific requirements of the power system industry and the information technology application level firewall security technology are met.

12. The intelligent power supply monitoring management function is achieved, the voltage of the storage battery can be fed back in real time, and the state of an operation power supply can be monitored.

13. The multifunctional board has self-diagnosis and self-recovery functions, each functional board and each core chip can perform self-diagnosis, alarm information can be transmitted when a fault occurs, automatic reset can be performed when a system is abnormal, and the like.

The foregoing description is directed to the details of preferred and exemplary embodiments of the invention, and not to the limitations defined thereby, which are intended to cover all modifications and equivalents of the invention as may come within the spirit and scope of the invention.

Claims

1. The utility model provides an electric power travelling wave fault location system which characterized in that: the device comprises a CPU, an FPGA, a recording memory, a voltage and current acquisition module and a power supply module for power supply, wherein the voltage and current acquisition module is connected to the FPGA; the voltage and current acquisition module comprises a mutual inductor, a conditioning circuit and a high-speed AD module, and the mutual inductor is connected to the FPGA through the conditioning circuit and the high-speed AD module; the analog fault traveling wave signal acquired by the mutual inductor is processed by a conditioning circuit and then input into a high-speed AD module for processing, and the conditioning circuit carries out resistance voltage division processing, transformer differential processing and RC low-pass filtering processing in sequence;

the FPGA control program comprises the following contents:

2. A power travelling wave fault location system according to claim 1, wherein: the voltage and current acquisition module further comprises a low-speed AD module and a multi-path analog switch circuit, and the mutual inductor, the low-speed AD module and the multi-path analog switch circuit form 18 paths of voltage and current data acquisition channels.

3. A power travelling wave fault location system according to claim 2, wherein: the multi-path analog switch circuit adopts an ADG409 chip, and 3 groups of ADG409 chips are adopted to expand into 18 paths of analog signals; the low-speed AD module adopts an AD7656 chip, 18 paths of analog signals are input into the AD7656 chip after being processed by a filter circuit, the filter circuit firstly utilizes a low-pass filter formed by a capacitor and an operational amplifier which are connected in parallel to process, and then a voltage follower formed by the operational amplifier is used for processing.

4. A power travelling wave fault location system according to claim 1, wherein: the high-speed AD module adopts an AD9257BCPZ-40 chip, analog fault traveling wave signals acquired by the mutual inductor are processed by a conditioning circuit and then input into the AD9257BCPZ-40 chip for processing, and the conditioning circuit carries out resistance voltage division processing, radio frequency transformer ADT4-1WT differential processing and RC low-pass filtering processing in sequence.

5. A power travelling wave fault location system according to claim 1, wherein: the FPGA adopts an EP4CE10F17C8N chip, the circuit configuration adopts a JTAG mode and a main serial mode, and the carried wave recording memory adopts an SDR MT48LC16M16A2B4-6A memory; the CPU is an ARM + DSP dual-core processor OMPL _138, and a DDR2MT46H32M16LFBF-6 memory is loaded on the CPU.

6. A power travelling wave fault location system according to claim 1, wherein: the power module adopts a switching stabilized voltage supply TPS54620 chip to convert and provide voltages of +/-12V, 5V, 3.3V, 2.5V, 1.8V and 1.2V, and adopts a linear stabilized voltage supply ADP1706ARDZ-1.8-R7 chip to convert and provide a voltage of 1.8V.

7. A power travelling wave fault location system according to claim 1, wherein: the CPU is also connected with a positioning module and a wireless network transmission module, and is in communication connection with the upper host through the wireless network transmission module.