CN113270132B - TCAM (ternary content addressable memory) storage and search method and system based on SRAM (static random Access memory) - Google Patents
TCAM (ternary content addressable memory) storage and search method and system based on SRAM (static random Access memory) Download PDFInfo
- Publication number
- CN113270132B CN113270132B CN202110821759.6A CN202110821759A CN113270132B CN 113270132 B CN113270132 B CN 113270132B CN 202110821759 A CN202110821759 A CN 202110821759A CN 113270132 B CN113270132 B CN 113270132B
- Authority
- CN
- China
- Prior art keywords
- bits
- entry
- bit
- sram
- sub
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
- G11C15/04—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
Landscapes
- Data Exchanges In Wide-Area Networks (AREA)
Abstract
The invention relates to a TCAM storing and searching method and a TCAM storing and searching system based on SRAM, wherein the method comprises the following steps: will input for storageRespectively carrying out segmentation processing on W-bit Data and W-bit Mask in the storage address to obtain n sub-Data blocks with the length of W bits respectively and n sub-Mask blocks with the length of W bits respectively; combining the sub Data block and the sub Mask block in pairs to obtain n first entries with the lengths of 2w bits respectively; respectively obtaining the number of 0 in the low w bit in each first item; encoding each first entry to obtain n entries of length 2wBit second entry; and storing the second entries in the SRAM bit by bit respectively. The invention can reduce the cost and the search power consumption by using the SRAM.
Description
Technical Field
The invention relates to the technical field of memories, in particular to a TCAM (ternary content addressable memory) storing and searching method and system based on SRAM (static random access memory).
Background
Currently, with the increasing of network bandwidth, the requirement for the forwarding speed of the router is higher and higher, and a current popular mode is to use a TCAM (ternary content addressable memory) device to perform fast route lookup. Compared with a general Static Random-Access Memory (SRAM), the current TCAM is more expensive in unit bit and the capacity of a Memory chip is relatively smaller; in addition, because the TCAM uses a parallel matching comparison method, the power consumption of the TCAM chip is large.
Disclosure of Invention
The invention aims to provide a TCAM storage and search method and a TCAM storage and search system based on SRAM, which reduce cost and power consumption.
In order to achieve the purpose, the invention provides the following scheme:
a TCAM storage method based on SRAM comprises:
carrying out segmentation processing on W-bit Data input into an address to be stored to obtain n sub Data blocks with the length of W bits respectively, and carrying out segmentation processing on W-bit Mask input into the address to be stored to obtain n sub Mask blocks with the length of W bits respectively;
combining the sub Data block and the sub Mask block in pairs to obtain n first entries with the lengths of 2w bits respectively; the high w bit of each first entry is Data of the sub Data block, and the low w bit is Data of the sub Mask;
respectively obtaining the number of '0' in the low w bit in each first item;
coding each of the first entries to obtain n entries of length 2wNumber two entry: if the number of '0' in the low w bits in the first entry is 0, encoding the low w bits of the first entry through a second encoder; if the number of '0' in the low w bits of the first entry is greater than 0, encoding the high w bits of the first entry through a first encoder;
and storing the second entries in the SRAM bit by bit respectively.
Optionally, the obtaining the number of '0' in the low w bits of each first entry respectively specifically includes:
the number of '0' in the low w bits in each of the first entries is obtained by a counter, respectively.
Optionally, W is 9.
Optionally, w is 3.
Optionally, n is 3.
The invention also discloses a TCAM storage system based on SRAM, comprising:
the address input segmentation module is used for segmenting W-bit Data input into an address to be stored to obtain n sub Data blocks with the length of W bit respectively, and segmenting W-bit Mask input into the address to be stored to obtain n sub Mask blocks with the length of W bit respectively;
the first entry acquisition module is used for combining the sub Data block and the sub Mask block in pairs to obtain n first entries with the lengths of 2w bits respectively; the high w bit of each first entry is Data of the sub Data block, and the low w bit is Data of the sub Mask;
a counting module, configured to obtain the number of '0' in the low w bits of each first entry;
a second entry obtaining module, configured to encode each of the first entries to obtain n entries with a length of 2wNumber two entry: if the first itemIf the number of '0' in the middle low w bits is 0, encoding the low w bits of the first entry by a second encoder; if the number of '0' in the low w bits of the first entry is greater than 0, encoding the high w bits of the first entry through a first encoder;
and the storage module is used for storing each second entry in the SRAM according to bits.
The invention also discloses a TCAM searching method based on the SRAM, which is applied to the TCAM storing method based on the SRAM and comprises the following steps:
carrying out segmentation processing on the input W-bit keys to obtain n sub-keys with the length of W bits;
respectively taking each sub-key as the address input of n SRAMs;
inputting the outputs of the n SRAMs into an AND gate;
and connecting the output of the AND gate with the input of a priority encoder, wherein the output of the priority encoder is the address to be searched.
The invention also discloses a TCAM searching system based on SRAM, which is applied to the TCAM storing system based on SRAM, and comprises:
the input segmentation processing module is used for carrying out segmentation processing on the input W-bit keys to obtain n sub-keys with the length of W bits;
the input SRAM module is used for inputting the sub-keys as the addresses of the n SRAMs;
the AND operation module is used for inputting the outputs of the n SRAMs into an AND gate;
and the address output module is used for connecting the output of the AND gate with the input of a priority encoder, and the output of the priority encoder is the address to be searched.
According to the specific embodiment provided by the invention, the invention discloses the following technical effects:
the TCAM based on the SRAM realizes storage and search, the SRAM can effectively reduce cost and search power consumption, and meanwhile, the search is realized by one-time memory access.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without inventive exercise.
FIG. 1 is a schematic flow chart of a TCAM storage method based on SRAM in accordance with the present invention;
FIG. 2 is a schematic diagram of a TCAM parallel search structure;
FIG. 3 is a schematic flow chart of a TCAM storing and searching method based on SRAM in accordance with the present invention;
FIG. 4 is a diagram illustrating the SRAM storage result according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a TCAM memory system based on SRAM according to the present invention;
FIG. 6 is a schematic flow chart of a TCAM lookup method based on SRAM in accordance with the present invention;
FIG. 7 is a schematic diagram of a TCAM lookup system based on SRAM according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention aims to provide a TCAM storage and search method and a TCAM storage and search system based on SRAM, which reduce cost and power consumption.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
The ternary content addressable memory TCAM saves the key word list item with any length by saving the key word mask code, thus the TCAM is very suitable for carrying out the route search of longest prefix matching. The lookup structure of TCAM is shown in fig. 2.
TCAM uses parallel technology, has the searching complexity of O (1) (the searching process is independent of the input data bit width and the data quantity), so the searching speed is high. Compared with the general static random access memory SRAM, the TCAM with unit bit is more expensive, and the capacity of the memory chip is relatively smaller; (2) because the TCAM uses a parallel matching comparison mode, the power consumption of the TCAM chip is larger.
Fig. 1 is a schematic flow chart of a TCAM storage method based on an SRAM according to the present invention, and as shown in fig. 1, the TCAM storage method based on the SRAM includes the following steps:
step 101: segmenting W-bit Data (Data) input into an address to be stored to obtain n sub-Data blocks with the length of W bits respectively, and segmenting W-bit Mask (Mask) input into the address to be stored to obtain n sub-Mask blocks with the length of W bits respectively;
step 102: combining the sub Data block and the sub Mask block in pairs to obtain n first entries with the lengths of 2w bits respectively; the high w bit of each first entry is Data of the sub Data block, and the low w bit is Data of the sub Mask;
step 103: respectively obtaining the number of '0' in the low w bit in each first item;
step 104: encoding each first entry to obtain n entries of length 2wNumber two entry: if the number of '0' in the low w bits in the first entry is 0, encoding the low w bits of the first entry through a second encoder; if the number of '0' in the low w bits of the first entry is greater than 0, encoding the high w bits of the first entry through a first encoder;
step 105: and storing the second entries in the SRAM bit by bit respectively.
Wherein, step 103 specifically comprises:
the number of '0' in the low w bits in each first entry is obtained by a counter, respectively.
Fig. 5 is a schematic structural diagram of a TCAM storage system based on an SRAM according to the present invention, and as shown in fig. 5, a TCAM storage system based on an SRAM includes:
the address input segmentation module 201 is configured to segment W-bit Data input into the address to be stored to obtain n sub-Data blocks with lengths of W bits, and segment W-bit masks input into the address to be stored to obtain n sub-Mask blocks with lengths of W bits;
a first entry obtaining module 202, configured to combine every two of the sub Data blocks and the sub Mask blocks to obtain n first entries with lengths of 2w bits respectively; the high w bit of each first entry is Data of the sub Data block, and the low w bit is Data of the sub Mask;
a counting module 203, configured to obtain the number of '0' in the low w bits in each first entry;
a second entry obtaining module 204, configured to encode each first entry to obtain n entries with a length of 2wNumber two entry: if the number of '0' in the low w bits in the first entry is 0, encoding the low w bits of the first entry through a second encoder; if the number of '0' in the low w bits of the first entry is greater than 0, encoding the high w bits of the first entry through a first encoder;
and a storage module 205, configured to store the second entries in the SRAM bit by bit.
Fig. 6 is a schematic flow chart of a TCAM lookup method based on an SRAM according to the present invention, and as shown in fig. 6, the TCAM lookup method based on the SRAM includes the following steps:
step 301: carrying out segmentation processing on the input W-bit keys (keywords) to obtain n sub-keys with the length of W bits;
step 302: respectively taking each sub-key as the address input of n SRAMs;
step 303: inputting the output of the n SRAMs into an AND gate;
step 304: and connecting the output of the AND gate with the input of a priority encoder, wherein the output of the priority encoder is the address to be searched.
As shown in fig. 3, the new TCAM implementation based on SRAM includes two processes, respectively: a storage procedure and a search procedure.
(1) Storing procedure
1) The input W-bit Data and the input W-bit Mask are respectively segmented to obtain n sub-Data blocks with the length of W bits and n sub-Mask blocks with the length of W bits.
2) And combining the sub Data block and the sub Mask block in pairs to obtain n entries with the length of 2w bits respectively, wherein the high w bits of the entries are the Data of the sub Data block, and the low w bits of the entries are the Data of the sub Mask.
3) The number of "0" in the lower w bits of the resulting entry of length 2w bits is counted by a counter.
4) Passing the low w bits of the entry of length 2w bits obtained in step 2) through encoder 2 (second encoder) if the counter result is "0", and passing the high w bits of the entry of length 2w bits obtained in step 2) through encoder 1 (first encoder) otherwise.
N pieces of length 2 can be obtained by the stepwA new entry of bits.
5) N obtained in the step 4) have the length of 2wThe new entries of bits are stored in the n SRAMs by bit.
(2) Search process
1) And carrying out segmentation processing on the input W-bit keys to obtain n sub-keys with the lengths of W bits respectively.
2) And inputting n w-bit sub-keys as the addresses of the n SRAMs.
3) The outputs of the n SRAMs are passed through AND gates.
And passing the output of the AND gate through a priority encoder, wherein the output of the priority encoder is the address to be searched.
Table 1 shows a routing table with W = 9.
Table 1 routing table
(1) Storing procedure
Data and Mask are segmented according to n =3, as shown in tables 2 and 3:
TABLE 2 Data segmentation results
TABLE 3 Mask segmentation results
The first entry for the combination of the sub-Data block and the sub-Mask block is shown in table 4:
TABLE 4 first entry
Taking the data at address 11 as an example for the following description, as can be seen from table 4, the n =3 entries obtained after the data at the first row is segmented and reassembled are 001111,100111,110000 respectively. Counting the number of "0" in the low w =3 bits of the three first entries, it is known that the entry 001111 has the low 3 bits of 111 and the number of "0" is 0, so that the high 3 bits 001 thereof are passed through the encoder 2 to obtain the new entry 01000000, and the encoding process adopts a one-hot encoding method. Similarly, entry 100111 passes through the counter and encoder 2 to obtain a new entry 00001000. For the entry 110000, since the lower 3 bits are 000, where the number of "0" is 3>0, it is necessary to get the new entry 11111111 through the encoder 1, and the encoding process is determined according to the number of "0".
The data obtained after step 4) is shown in table 5, similarly to the data conversion process of the first row:
TABLE 5 second item
As shown in fig. 4, the data of table 5 is stored in 3 blocks of SRAM by columns.
(2) Search process
At this time, if the key entered is 011000001, then addresses 2 and 3 both match from the routing table, and the result should be 2 based on the low address priority output.
According to the search method proposed by the present invention, first, a key is divided into n =3 segments, which are 011,000,001 respectively.
0110,0110,1111 can be obtained by using the three sub-keys as the addresses of the three SRAM blocks as input.
The three output data (0110,0110,1111) are passed through an AND gate, resulting in a result of 0110.
And (4) passing the result 0110 obtained by the AND gate through a priority encoder to obtain an output address of 2.
Fig. 7 is a schematic structural diagram of a TCAM lookup system based on an SRAM according to the present invention, and as shown in fig. 7, a TCAM lookup system based on an SRAM includes:
the input segmentation processing module 401 is configured to perform segmentation processing on the input W-bit keys to obtain n sub-keys with a length of W bits;
an input SRAM module 402, configured to input each sub-key as an address of n SRAMs, respectively;
an and operation module 403, configured to input outputs of the n SRAMs into an and gate;
and an address output module 404, configured to connect an output of the and gate to an input of a priority encoder, where an output of the priority encoder is an address to be searched.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. For the system disclosed by the embodiment, the description is relatively simple because the system corresponds to the method disclosed by the embodiment, and the relevant points can be referred to the method part for description.
The principles and embodiments of the present invention have been described herein using specific examples, which are provided only to help understand the method and the core concept of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed. In view of the above, the present disclosure should not be construed as limiting the invention.
Claims (8)
1. A TCAM storage method based on SRAM is characterized by comprising the following steps:
carrying out segmentation processing on W-bit Data input into an address to be stored to obtain n sub Data blocks with the length of W bits respectively, and carrying out segmentation processing on W-bit Mask input into the address to be stored to obtain n sub Mask blocks with the length of W bits respectively;
combining the sub Data block and the sub Mask block in pairs to obtain n first entries with the lengths of 2w bits respectively; the high w bit of each first entry is Data of the sub Data block, and the low w bit is Data of the sub Mask;
respectively obtaining the number of '0' in the low w bit in each first item;
coding each of the first entries to obtain n entries of length 2wNumber two entry: if the number of '0' in the low w bits in the first entry is 0, encoding the low w bits of the first entry through a second encoder; if the number of '0' in the low w bits of the first entry is greater than 0, encoding the high w bits of the first entry through a first encoder;
and storing the second entries in the SRAM bit by bit respectively.
2. The TCAM storing method according to claim 1, wherein the obtaining the number of '0' in the low w bits of each of the first entries respectively includes:
the number of '0' in the low w bits in each of the first entries is obtained by a counter, respectively.
3. The SRAM-based TCAM storage method of claim 1, in which W is 9.
4. The SRAM-based TCAM storage method of claim 1, in which w is 3.
5. The SRAM-based TCAM storage method of claim 1, in which n is 3.
6. An SRAM-based TCAM memory system, comprising:
the address input segmentation module is used for segmenting W-bit Data input into an address to be stored to obtain n sub Data blocks with the length of W bit respectively, and segmenting W-bit Mask input into the address to be stored to obtain n sub Mask blocks with the length of W bit respectively;
the first entry acquisition module is used for combining the sub Data block and the sub Mask block in pairs to obtain n first entries with the lengths of 2w bits respectively; the high w bit of each first entry is Data of the sub Data block, and the low w bit is Data of the sub Mask;
a counting module, configured to obtain the number of '0' in the low w bits of each first entry;
a second entry obtaining module, configured to encode each of the first entries to obtain n entries with a length of 2wNumber two entry: if the number of '0' in the low w bits in the first entry is 0, encoding the low w bits of the first entry through a second encoder; if the number of '0' in the low w bits of the first entry is greater than 0, encoding the high w bits of the first entry through a first encoder;
and the storage module is used for storing each second entry in the SRAM according to bits.
7. A TCAM searching method based on SRAM, which is applied to the TCAM storing method based on SRAM of any one of claims 1-5, and comprises:
carrying out segmentation processing on the input W-bit keys to obtain n sub-keys with the length of W bits;
respectively taking each sub-key as the address input of n SRAMs;
inputting the outputs of the n SRAMs into an AND gate;
and connecting the output of the AND gate with the input of a priority encoder, wherein the output of the priority encoder is the address to be searched.
8. An SRAM-based TCAM lookup system using the SRAM-based TCAM lookup method of claim 7, comprising:
the input segmentation processing module is used for carrying out segmentation processing on the input W-bit keys to obtain n sub-keys with the length of W bits;
the input SRAM module is used for inputting the sub-keys as the addresses of the n SRAMs;
the AND operation module is used for inputting the outputs of the n SRAMs into an AND gate;
and the address output module is used for connecting the output of the AND gate with the input of a priority encoder, and the output of the priority encoder is the address to be searched.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110821759.6A CN113270132B (en) | 2021-07-21 | 2021-07-21 | TCAM (ternary content addressable memory) storage and search method and system based on SRAM (static random Access memory) |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110821759.6A CN113270132B (en) | 2021-07-21 | 2021-07-21 | TCAM (ternary content addressable memory) storage and search method and system based on SRAM (static random Access memory) |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113270132A CN113270132A (en) | 2021-08-17 |
| CN113270132B true CN113270132B (en) | 2021-09-24 |
Family
ID=77236940
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110821759.6A Active CN113270132B (en) | 2021-07-21 | 2021-07-21 | TCAM (ternary content addressable memory) storage and search method and system based on SRAM (static random Access memory) |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113270132B (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103546378A (en) * | 2013-05-20 | 2014-01-29 | 李险峰 | Multi-match 2-level hierarchical search method for ranges on basis of TCAM (ternary content addressable memory) |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7689889B2 (en) * | 2006-08-24 | 2010-03-30 | Cisco Technology, Inc. | Content addressable memory entry coding for error detection and correction |
| JP5140849B2 (en) * | 2008-02-13 | 2013-02-13 | ルネサスエレクトロニクス株式会社 | Content reference memory |
| US10388396B2 (en) * | 2014-08-25 | 2019-08-20 | Rambus Inc. | Buffer circuit with adaptive repair capability |
-
2021
- 2021-07-21 CN CN202110821759.6A patent/CN113270132B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103546378A (en) * | 2013-05-20 | 2014-01-29 | 李险峰 | Multi-match 2-level hierarchical search method for ranges on basis of TCAM (ternary content addressable memory) |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113270132A (en) | 2021-08-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6985483B2 (en) | Methods and systems for fast packet forwarding | |
| US7019674B2 (en) | Content-based information retrieval architecture | |
| US20030135691A1 (en) | Input data selection for content addressable memory | |
| US20040254909A1 (en) | Programming routes and access control lists in comparison tree data structures and their use such as in performing lookup operations | |
| US8966167B1 (en) | Content search system having multiple pipelines | |
| Zerbini et al. | Performance evaluation of packet classification on FPGA-based TCAM emulation architectures | |
| US7403526B1 (en) | Partitioning and filtering a search space of particular use for determining a longest prefix match thereon | |
| Veeramani et al. | Minimization of flow table for TCAM based openflow switches by virtual compression approach | |
| US6970971B1 (en) | Method and apparatus for mapping prefixes and values of a hierarchical space to other representations | |
| Li et al. | Memory‐efficient recursive scheme for multi‐field packet classification | |
| Sun et al. | A hybrid approach to CAM-based longest prefix matching for IP route lookup | |
| CN113270132B (en) | TCAM (ternary content addressable memory) storage and search method and system based on SRAM (static random Access memory) | |
| SE531947C2 (en) | Procedure, device and system for multi-field classification in a data communication network | |
| CN112818185A (en) | Method for searching longest prefix matching hardware system based on SRAM | |
| Akhbarizadeh et al. | Prefix segregation scheme for a TCAM-based IP forwarding engine | |
| US7523251B2 (en) | Quaternary content-addressable memory | |
| Akhbarizadeh et al. | A nonredundant ternary CAM circuit for network search engines | |
| Ghosh et al. | A hash based architecture of longest prefix matching for fast IP processing | |
| Sun et al. | Content-based route lookup using CAMs | |
| Govindaraj et al. | An efficient technique for longest prefix matching in network routers | |
| Lu | Improved trie partitioning for cooler TCAMs | |
| Murugesan et al. | A novel range matching architecture for packet classification without rule expansion | |
| Zhang et al. | A resource-saving TCAM structure based on SRAM | |
| Le et al. | High-throughput ip-lookup supporting dynamic routing tables using fpga | |
| US20090210382A1 (en) | Method for priority search using a tcam |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |