CN113257909A - Silicon On Insulator (SOI) -based gallium nitride (GaN) wafer and preparation method thereof - Google Patents
Silicon On Insulator (SOI) -based gallium nitride (GaN) wafer and preparation method thereof Download PDFInfo
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- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 title claims abstract description 66
- 238000002360 preparation method Methods 0.000 title claims abstract description 11
- 239000010703 silicon Substances 0.000 title claims description 19
- 229910052710 silicon Inorganic materials 0.000 title claims description 18
- 239000012212 insulator Substances 0.000 title description 4
- 229910002601 GaN Inorganic materials 0.000 claims abstract description 57
- 238000000034 method Methods 0.000 claims abstract description 21
- 229910002704 AlGaN Inorganic materials 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 230000006911 nucleation Effects 0.000 claims abstract description 5
- 238000010899 nucleation Methods 0.000 claims abstract description 5
- 239000010410 layer Substances 0.000 claims description 56
- 229910052681 coesite Inorganic materials 0.000 claims description 4
- 229910052906 cristobalite Inorganic materials 0.000 claims description 4
- 239000013078 crystal Substances 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052682 stishovite Inorganic materials 0.000 claims description 4
- 229910052905 tridymite Inorganic materials 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- 229910052733 gallium Inorganic materials 0.000 claims description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 2
- 229910052799 carbon Inorganic materials 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 claims description 2
- 239000002356 single layer Substances 0.000 claims description 2
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 claims 6
- 230000003247 decreasing effect Effects 0.000 claims 1
- 230000010354 integration Effects 0.000 abstract description 4
- 238000001816 cooling Methods 0.000 abstract description 2
- 230000002349 favourable effect Effects 0.000 abstract description 2
- 230000000977 initiatory effect Effects 0.000 abstract description 2
- 235000012431 wafers Nutrition 0.000 description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 12
- 238000000103 photoluminescence spectrum Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 4
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 description 4
- 230000000052 comparative effect Effects 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 238000006731 degradation reaction Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000002243 precursor Substances 0.000 description 2
- XCZXGTMEAKBVPV-UHFFFAOYSA-N trimethylgallium Chemical compound C[Ga](C)C XCZXGTMEAKBVPV-UHFFFAOYSA-N 0.000 description 2
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 239000008186 active pharmaceutical agent Substances 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 238000012512 characterization method Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000005489 elastic deformation Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000001000 micrograph Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910000069 nitrogen hydride Inorganic materials 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- 238000012876 topography Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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Abstract
The invention relates to an SOI-based GaN wafer and a preparation method thereof, wherein the GaN wafer sequentially comprises the following components from bottom to top: SOI substrate, AlN nucleation layer, AlxGayN superlattice, carbon-doped gallium nitride C, a GaN buffer layer, a GaN channel layer, an AlGaN/AlN heterojunction and a GaN cap layer. By adopting optimized SOI customized parameters and C, GaN/AlGaN/AlN heterojunction technology and utilizing lattice mismatch of heterojunction to match thermal mismatch between GaN and SOI, the problems of over-large warping, even crack initiation and the like of an SOI-based GaN wafer in the high-temperature growth and cooling processes are avoided, and the method is favorable for realizing single-chip integration of GaN power electronics.
Description
Technical Field
The invention belongs to the field of GaN wafers and preparation thereof, and particularly relates to an SOI-based GaN wafer and a preparation method thereof.
Background
The single-chip integrated gallium nitride (GaN) power electronics can effectively inhibit parasitic effects introduced by packaging, PCB connection, driving circuits and the like, can greatly reduce the size and the number of chips, and can improve the design flexibility.
GaN-on-silicon (GaN-on-Si) has the advantages of low cost, large size and the like, and is the development trend of GaN wafers, but device crosstalk, background effect and the like caused by sharing a silicon substrate enable GaN-on-silicon (GaN-on-Si)-Si single chip integration is extremely challenging. If silicon-on-insulator (SOI) -based GaN (GaN-on-SOI) is used, the SOI BOX layer (SiO) is used2) The all-dielectric isolation characteristic can effectively eliminate crosstalk, inhibit background effect and reduce on-resistance degradation.
However, the difference between the thermal expansion coefficients of Si and GaN is large, i.e., there is a large thermal mismatch, and the BOX layer (SiO) in SOI2) The thermal mismatch with GaN is larger, so that the GaN wafer is easily transformed from elastic deformation to plastic deformation in the growth process on the SOI substrate, the wafer is warped too much and even broken, and the wafer warping degree is generally required not to exceed 50 mu m by the flow sheet requirement; moreover, silicon and GaN have larger lattice difference, and the lattice mismatch is as high as 17%, thereby further increasing the difficulty of large-size SOI-based GaN wafer epitaxy.
Disclosure of Invention
The invention aims to solve the technical problem of providing an SOI-based GaN wafer and a preparation method thereof, and overcoming the defect that the prior art can not prepare GaN wafers with low defect density, large size and no device crosstalk.
The invention provides an SOI-based GaN wafer, which sequentially comprises the following components from bottom to top: SOI substrate, AlN nucleation layer, AlxGayN superlattice, carbon-doped gallium nitride C, a GaN buffer layer, a GaN channel layer, an AlGaN/AlN heterojunction and a GaN cap layer; wherein x is 0.95-0.05 and y is 0.05-0.95.
The SOI substrate comprises top layer silicon and BOX layer SiO2And underlying silicon.
The thickness of the top layer silicon is 0.1-10 μm, and the crystal directions are (111) and (100); BOX layer SiO2The thickness is 0.1-2 μm; the thickness of the bottom layer silicon is 0.5-1.5mm, and the crystal orientation is (100), (111).
Furthermore, the doping type of the top layer silicon is P-type doping, the resistivity of the top layer silicon is 0.002-200Ohm cm, and the thickness ratio of the BOX layer to the top layer silicon is 0.01-10.
The AlN nucleating layer is 20-500nm thick.
The Al isxGayThe N superlattice is composed of a plurality of layers of superlattices with different Al and Ga components, the Al component gradually decreases from bottom to top, and the single layer of AlxGayThe thickness of N is 2-500nm, and the molar content of Al component elements is 1-50%.
The shown superlattice of the multilayer with different Al and Ga components is 4-20 layers.
The total thickness of the carbon-doped gallium nitride C and the GaN buffer layer is 1-10 mu m; the thickness of the GaN channel layer is 50-500 nm; the thickness of the GaN capping layer is 1-50 nm.
The AlGaN thickness in the AlGaN/AlN heterojunction is 1-100nm, and the molar content of Al component elements in the AlGaN is 10-50%; the AlN thickness is 0.5-10 nm.
The invention discloses a preparation method of an SOI-based GaN wafer, which comprises the following steps:
AlN nucleating layer growth and Al are carried out on the surface of the SOI substrate in sequencexGayGrowing an N superlattice, doping carbon with gallium nitride C, growing a GaN buffer layer, growing a GaN channel layer, growing an AlGaN/AlN heterojunction and growing a GaN cap layer to obtain the SOI-based GaN wafer.
The SOI substrate is pretreated, and specifically comprises the following steps: in the MOCVD cavity, performing TMAl pretreatment on the surface of the SOI wafer for 12-15s at 800-2And the pressure is 10-200 mbar.
The AlN nucleating layer growing method adopts one of MOCVD, MBE and ALD; al (Al)xGayThe N superlattice growth method adopts one of MOCVD, MBE and ALD; c, adopting one of MOCVD, MBE and ALD as a GaN buffer layer growth method; the GaN channel layer growth method adopts one of MOCVD, MBE and ALD; the AlGaN/AlN heterojunction growth method adopts any one or combination of MOCVD, MBE, ALD and the like; the GaN capping layer growing method adopts one of MOCVD, MBE and ALD.
The invention discloses application of the SOI-based GaN wafer in the field of GaN power electronics.
Advantageous effects
The method is mainly applied to the field of high-voltage high-frequency GaN power electronics, combines the natural advantage of SOI full-medium isolation and the advantage of GaN wide forbidden band, can prepare high-quality and large-size GaN-on-SOI wafers (the defects introduced in the stripping process before bonding are avoided, the size of the GaN wafer is consistent with that of an SOI substrate, the size of the substrate is large, and the size of the wafer can be large), and is favorable for realizing high-performance GaN single-chip integration.
According to the invention, optimized SOI customized parameters (such as doping type and resistivity of top layer silicon and thickness ratio of a BOX layer and the top layer silicon) and C: GaN/AlGaN/AlN heterojunction technology are adopted, lattice mismatch of heterojunction is utilized to match thermal mismatch between GaN and SOI, so that the problems of overlarge warping, even crack initiation and the like of an SOI-based GaN wafer in the high-temperature growth and cooling processes are avoided, and the GaN power electronics can be favorably realized by single chip integration.
Drawings
FIG. 1 is a photomicrograph of the Atomic Force Microscope (AFM) of the surface of a GaN-on-SOI wafer of example 1;
FIG. 2 is data representing photoluminescence spectra (PL) of GaN-on-SOI wafers of example 1;
FIG. 3 is a flow chart of the GaN-on-SOI wafer fabrication process of the present invention;
FIG. 4 is a micrograph of the surface Atomic Force Microscope (AFM) of a GaN-on-SOI wafer of comparative example 1;
FIG. 5 is data characterizing photoluminescence spectra (PL) of a GaN-on-SOI wafer of comparative example 1;
FIG. 6 is a graph of the output characteristics of a HEMT device fabricated from the GaN-on-SOI wafer of example 1;
FIG. 7 is a view showing the structure of an SOI-based GaN HEMT device.
Detailed Description
The invention will be further illustrated with reference to the following specific examples. It should be understood that these examples are for illustrative purposes only and are not intended to limit the scope of the present invention. Further, it should be understood that various changes or modifications of the present invention may be made by those skilled in the art after reading the teaching of the present invention, and such equivalents may fall within the scope of the present invention as defined in the appended claims.
Al precursor: trimethylaluminum (TMAl), the purity is more than or equal to 99.9999%;
ga precursor: trimethyl gallium (TMGa) with the purity of more than or equal to 99.9999 percent;
NH3high-purity ammonia gas with the purity more than or equal to 99.999 percent is adopted.
Example 1
1. The SOI substrate material was selected with the following parameters, as shown in table 1 below:
TABLE 1
2. The silicon-on-insulator (SOI) is deposited on the surface of the SOI from bottom to top by a Metal Organic Chemical Vapor Deposition (MOCVD) method, and the following table 2 shows that:
TABLE 2
The specific preparation method of the GaN wafer comprises the following steps: firstly, in an MOCVD cavity, performing TMAl pretreatment on the surface of an SOI wafer for 12-15s at 1060 ℃, wherein the carrier gas is H2The following table 3 shows the preparation of the materials with a pressure of 100mbar and subsequent growth of the layers in succession:
TABLE 3
The specific measured performance parameters are shown in table 4:
TABLE 4
The AlGaN barrier layer is 23.55nm (center) and 23.58nm (edge) thick.
As shown in fig. 1, the structure shows: the coarse excess RMS is only 0.6 nm;
as shown in fig. 2, the results show that: warpage is only 26.8 μm.
The GaN HEMT device prepared by the material of the invention (as shown in figure 7) can be applied at the source-drain voltage (V) of up to 400VDS) The on-resistance did not significantly degrade, and the degradation rate was 0, as shown in fig. 6.
Comparative example 1
If the SOI substrate shown in the following Table 5 is selected, and C is GaN/AlxGayIn the N/AlN heterojunction, GaN is replaced by GaN, and the other preparation and structure are the same as those in the embodiment 1, so that the technical effect of the invention cannot be achieved. The corresponding characterization data of the micro-topography photo and photoluminescence spectrum (PL) of the GaN-on-SOI wafer surface Atomic Force Microscope (AFM) are respectively shown in FIG. 4 and FIG. 5, the surface roughness is increased from 0.6nm to 2.4nm, the wafer warpage is deteriorated from 26.8 μm to 80.4 μm, and the wafer-level flow sheet requirement (warpage is within 50 μm) is not met.
TABLE 5
Claims (10)
1. An SOI-based GaN wafer is characterized in that the GaN wafer sequentially comprises from bottom to top: SOI substrate, AlN nucleation layer, AlxGayN superlattice, carbon-doped gallium nitride C, a GaN buffer layer, a GaN channel layer, an AlGaN/AlN heterojunction and a GaN cap layer; wherein x is 0.95-0.05 and y is 0.05-0.95.
2. The SOI-based GaN wafer of claim 1, wherein the SOI substrate comprises a top layer of silicon, a BOX layer of SiO2And underlying silicon.
3. The SOI-based GaN wafer according to claim 2, wherein the top layer silicon has a thickness of 0.1-10 μm and crystal orientations of (111), (100); BOX layer SiO2The thickness is 0.5-2 μm; the thickness of the bottom layer silicon is 0.5-1.5mm, and the crystal orientation is (100), (111).
4. The SOI-based GaN wafer of claim 1, wherein the AlN nucleation layer has a thickness of 20-500 nm.
5. The SOI-based GaN wafer of claim 1, wherein the AlxGayThe N superlattice is composed of a plurality of layers of superlattices with different Al and Ga components, and the Al components are arranged from bottom to topGradually decreased in Al monolayerxGayThe thickness of N is 2-500nm, and the molar content of Al element component is 1-50%.
6. The SOI-based GaN wafer of claim 1, wherein the carbon-doped gallium nitride C is a GaN buffer layer with a total thickness of 1-10 μm; the thickness of the GaN channel layer is 50-500 nm; the thickness of the GaN capping layer is 1-50 nm.
7. The SOI-based GaN wafer according to claim 1, wherein the AlGaN/AlN heterojunction has an AlGaN thickness of 1 to 100nm and an Al component molar content of 10 to 50%; the AlN thickness is 0.5-10 nm.
8. A method for manufacturing an SOI-based GaN wafer, comprising:
AlN nucleating layer growth and Al are carried out on the surface of the SOI substrate in sequencexGayGrowing an N superlattice, doping carbon with gallium nitride C, growing a GaN buffer layer, growing a GaN channel layer, growing an AlGaN/AlN heterojunction and growing a GaN cap layer to obtain the SOI-based GaN wafer.
9. The preparation method according to claim 8, wherein the AlN nucleation layer growth method adopts one of MOCVD, MBE and ALD; al (Al)xGayThe N superlattice growth method adopts one of MOCVD, MBE and ALD; c, adopting one of MOCVD, MBE and ALD as a GaN buffer layer growth method; the GaN channel layer growth method adopts one of MOCVD, MBE and ALD; the AlGaN/AlN heterojunction growth method adopts any one or combination of MOCVD, MBE, ALD and the like; the GaN capping layer growing method adopts one of MOCVD, MBE and ALD.
10. Use of the SOI-based GaN wafer of claim 1 in the GaN power electronics field.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080023706A1 (en) * | 2006-07-26 | 2008-01-31 | Kabushiki Kaisha Toshiba | Nitride semiconductor device |
| CN101302648A (en) * | 2008-01-28 | 2008-11-12 | 中国电子科技集团公司第五十五研究所 | Gallium nitride thin film epitaxial growth structure and method |
| US20150357451A1 (en) * | 2012-12-26 | 2015-12-10 | Agency For Science, Technology And Research | Semiconductor device for high-power applications |
| US20160225887A1 (en) * | 2015-01-20 | 2016-08-04 | International Business Machines Corporation | Control of current collapse in thin patterned gan |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080023706A1 (en) * | 2006-07-26 | 2008-01-31 | Kabushiki Kaisha Toshiba | Nitride semiconductor device |
| CN101302648A (en) * | 2008-01-28 | 2008-11-12 | 中国电子科技集团公司第五十五研究所 | Gallium nitride thin film epitaxial growth structure and method |
| US20150357451A1 (en) * | 2012-12-26 | 2015-12-10 | Agency For Science, Technology And Research | Semiconductor device for high-power applications |
| US20160225887A1 (en) * | 2015-01-20 | 2016-08-04 | International Business Machines Corporation | Control of current collapse in thin patterned gan |
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Application publication date: 20210813 |