CN113257680B - Method for manufacturing fully antistatic base of integrated circuit - Google Patents
Method for manufacturing fully antistatic base of integrated circuit Download PDFInfo
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- CN113257680B CN113257680B CN202110379155.0A CN202110379155A CN113257680B CN 113257680 B CN113257680 B CN 113257680B CN 202110379155 A CN202110379155 A CN 202110379155A CN 113257680 B CN113257680 B CN 113257680B
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- 238000000034 method Methods 0.000 title claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 239000002356 single layer Substances 0.000 claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 238000011049 filling Methods 0.000 claims abstract description 16
- 239000011159 matrix material Substances 0.000 claims abstract description 15
- 239000010410 layer Substances 0.000 claims abstract description 14
- 239000002002 slurry Substances 0.000 claims abstract description 10
- 238000007747 plating Methods 0.000 claims abstract description 6
- 238000005520 cutting process Methods 0.000 claims abstract description 5
- 238000005530 etching Methods 0.000 claims abstract description 5
- 238000001746 injection moulding Methods 0.000 claims abstract description 4
- 238000010030 laminating Methods 0.000 claims abstract description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 15
- 239000000945 filler Substances 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 9
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 231100000350 mutagenesis Toxicity 0.000 claims description 8
- 238000002703 mutagenesis Methods 0.000 claims description 8
- 230000006698 induction Effects 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 5
- 239000010949 copper Substances 0.000 claims description 5
- 229910000679 solder Inorganic materials 0.000 claims description 5
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 4
- 239000011248 coating agent Substances 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 4
- 238000009713 electroplating Methods 0.000 claims description 4
- 229910021389 graphene Inorganic materials 0.000 claims description 4
- 239000003822 epoxy resin Substances 0.000 claims description 3
- 229920000647 polyepoxide Polymers 0.000 claims description 3
- 238000005476 soldering Methods 0.000 claims description 3
- 230000001052 transient effect Effects 0.000 claims description 3
- 238000007789 sealing Methods 0.000 claims description 2
- 239000013078 crystal Substances 0.000 abstract description 8
- 230000005611 electricity Effects 0.000 abstract description 2
- 230000003068 static effect Effects 0.000 abstract description 2
- 231100000219 mutagenic Toxicity 0.000 description 6
- 230000003505 mutagenic effect Effects 0.000 description 6
- 239000002245 particle Substances 0.000 description 3
- 239000011295 pitch Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 230000001960 triggered effect Effects 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 238000012938 design process Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000005610 quantum mechanics Effects 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
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Abstract
The invention relates to the technical field of integrated circuits, in particular to a method for manufacturing a fully antistatic base of an integrated circuit. Etching a plurality of grounding wires with the same space and parallel to each other on the circuit substrate; fixing N needle-shaped electrodes with the same length on a grounding wire in parallel along a direction vertical to the grounding wire through a conducting ring; injecting insulating filling slurry, and cutting the edges of the matrix formed by injection molding to expose two ends of the grounding wire to form a single-layer electrode matrix; repeating the above operations to obtain M single-layer electrode substrates; laminating and curing M single-layer electrode substrates into a base blank a; plating a conductive layer around the base blank to form a base blank b; and slicing the base blank b along the gap direction of the adjacent grounding wires to obtain a plurality of integrated circuit fully-antistatic bases. The base manufactured by the manufacturing method can be used for connecting an integrated circuit with a circuit board, so that each pin of the connected integrated circuit is protected against static electricity. Therefore, the area of a crystal source for manufacturing the electrostatic protection in the chip can be saved, and the safety of the chip is fully guaranteed.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a method for manufacturing a fully antistatic base of an integrated circuit.
Background
With the increasing industrial process of integrated circuits, the integration level of transistors is higher, the wiring in a chip is finer, and the antistatic function of the chip is lower. In order to make the chip have a certain antistatic capability, enough crystal source surfaces have to be reserved in the chip design and production processes, and an antistatic protection circuit is additionally arranged in a circuit inside the chip to perform antistatic protection from 0 volt to several thousand volts on inlets of a plurality of chips. This takes up valuable die source area and also keeps chip costs high. If the electrostatic protection circuit is reduced to reduce the crystal source occupation, the antistatic capability of the chip is greatly reduced, thereby affecting the use.
Therefore, how to manufacture an integrated circuit that satisfies the antistatic capability of the chip and reduces the occupation of the crystal source becomes a difficult point in the integrated circuit manufacturing industry.
Disclosure of Invention
The invention aims to provide a method for manufacturing a fully antistatic base of an integrated circuit, aiming at the defects of the prior art, and being applied to the periphery of the integrated circuit for resisting static electricity, the method can greatly reduce the occupation of precious crystal source area by manufacturing the antistatic circuit in a chip and simultaneously achieve better antistatic effect.
The technical scheme of the invention is as follows: comprises that
Etching a plurality of grounding wires with the same interval and parallel to each other on the circuit substrate;
fixing N needle-shaped electrodes with the same length on a grounding wire in parallel along a direction vertical to the grounding wire through a conducting ring;
injecting insulating filling slurry, and cutting the edge of the matrix formed by injection molding to expose two ends of the grounding wire to form a single-layer electrode matrix only provided with one row of needle electrodes;
repeating the above operations to obtain M single-layer electrode substrates;
laminating and curing M single-layer electrode substrates into a cuboid base blank a;
plating a conductive layer around the base blank to form a base blank b;
slicing the base blank b along the gap direction of the adjacent grounding wires to obtain a plurality of integrated circuit fully antistatic bases;
n is the column number of the ball grid array pins of the protected chip, and M is the row number of the ball grid array pins of the protected chip.
Preferably, when the circuit substrate is used for etching the ground wires, the positioning pins are used for positioning, so that the width of each ground wire is the height of the conductive ring.
Preferably, the N needle electrodes with the same length are fixed in parallel through the auxiliary support, clamping grooves which are arranged at equal intervals and used for fixing the needle electrodes are formed in the auxiliary support, and the clamping grooves are formed in the positions, corresponding to the upper portion and the lower portion of the needle electrodes, of the auxiliary support.
Preferably, after the needle electrodes are fixed on the auxiliary support, the needle electrodes are plated with copper in an electroplating manner to form conducting rings, and each needle electrode is plated with a conducting ring at a position corresponding to the grounding wire.
Preferably, also comprises
The auxiliary bracket and the needle-shaped electrodes fixed on the auxiliary bracket are paved on the planes of a plurality of grounding wires of the circuit substrate together;
finely adjusting the position of the auxiliary support to ensure that each conducting ring is completely overlapped with the grounding wire along the height direction;
respectively carrying out coordinate marking on the first conducting rings at the head and the tail of the needle-shaped electrode row;
and printing solder paste at the contact positions of the conducting rings and the grounding wire, and performing reflow soldering to ensure that each conducting ring is in conductive connection with the grounding wire.
Preferably, when the insulating filling paste is injected, the surface of the insulating filling paste is flush with the surface of the conducting ring.
Preferably, the single-layer electrode substrates are placed in a mode that the needle electrodes face upwards, and the single-layer electrode substrates are solidified layer by layer in a mode of coating insulating filling slurry until M single-layer electrode substrates are solidified into a whole;
in the curing process, the first M-1 layers need to ensure that the first conducting rings at the head and the tail of the line in each single-layer electrode matrix are coincided with the previous layer.
Preferably, when the mth single-layer electrode substrate is manufactured, a needle electrode a is additionally arranged at the tail of the row, and the needle electrode a is a metal bare wire which is in conductive connection with the grounding wire of the last row.
Preferably, the needle electrode is a voltage-induced-mutation-resistance-film-covered wire which is manufactured by coating a voltage-induced-mutation-resistance film on an outer surface of a conductive core wire.
Preferably, the insulating filler is a high-temperature curing material which contains 0.3% -30% of graphene, 70% -99.5% of epoxy resin and 0.2% of other materials and has the function of absorbing transient energy caused by secondary induction generated by a high-voltage pulse circuit.
The invention has the beneficial effects that:
1. the base manufactured by the scheme is applied to a combination part of an integrated circuit and a circuit board, after the base is connected into a chip pin, when any pin in the chip senses a pulse high voltage, the switch function of the voltage mutagenesis resistance film on the surface of an electrode in a base cavity corresponding to the pin is triggered, the voltage is enabled to release energy along the pin → the voltage mutagenesis resistance film → a metal ring → a grounding wire → a circuit board grounding wire in a current mode, and therefore the internal circuit of the chip is completely protected by the high-voltage pulse. The base is equivalent to a high-voltage electrostatic pulse filter screen constructed on the periphery of a chip, and absorbs and clamps high-voltage pulses which possibly enter the chip and exceed 300V at a lower voltage (generally 150V), so that the interior of the chip only needs to carry out antistatic protection below 300V without carrying out antistatic protection from several volts to kilovolts, most of crystal source areas for manufacturing the electrostatic protection are saved, the saved crystal source areas can greatly increase the number of transistors, the crystal source utilization rate is greatly improved, and the safety of the chip is fully guaranteed while the chip cost is reduced.
2. This scheme adopts earlier whole base idiosome b of producing, acquires the required full antistatic base of integrated circuit of this scheme through sliced mode again, compares in independently making the full antistatic base of every integrated circuit respectively, and it has promoted the preparation efficiency greatly, has effectively avoided single base thickness too little simultaneously, is difficult to the difficult problem of processing.
3. The clamping grooves which are arranged at equal intervals are arranged on the auxiliary support to fix the electrodes, so that the problem that the distance between the electrodes is extremely small and the precision is difficult to guarantee can be solved, the manufacturing precision of the base is effectively improved, and the manufacturing difficulty is reduced.
4. The mode of adopting the insulating filling thick liquid of moulding plastics to realize the isolation between the electrode, be favorable to high-pressure torrent that produces when the high-voltage pulse is strikeed in the twinkling of an eye and the secondary high pressure in the twinkling of an eye that scattered magnetic field induced carry out the vortex energy and synthesize, prevent that these secondary inductions from appearing the resonance like repeated induction between high density pin and causing the continuation influence.
5. The copper ring is formed by cutting the edge of the substrate to expose two ends of the grounding wire and plating copper, all grounding electrodes are connected in parallel, each electrode can be grounded only through one grounding wire, and the structure is compact and the reliability is high.
6. The needle-shaped electrodes a made of metal bare wires are additionally arranged at the tail of the last row, so that all grounding electrodes can be grounded through the needle-shaped electrodes a, when the needle-shaped electrodes a are arranged on a circuit board, only one grounding pin needs to be reserved, and the arrangement space of the circuit board is effectively saved.
Drawings
FIG. 1 is a schematic view of a manufacturing process of the present invention;
FIG. 2 is a schematic flow chart of S2 according to the present invention;
FIG. 3 is a schematic diagram of the arrangement of the ground lines on the circuit substrate according to the present invention;
FIG. 4 is a schematic view of the conductive ring on the needle electrode according to the present invention;
FIG. 5 is a schematic view of an auxiliary frame and a needle electrode fixed thereon according to the present invention;
FIG. 6 is a schematic diagram showing the positional relationship of the needle electrode, the ground line and the conductive ring in the single-layer electrode substrate according to the present invention;
FIG. 7 is a schematic perspective view of a base (including a grounding outer ring) manufactured by the method of the present invention;
FIG. 8 is a schematic perspective view of a base (without a grounding outer ring) manufactured by the method of the present invention;
FIG. 9 is a schematic longitudinal cross-sectional view of the base;
FIG. 10 is an enlarged view of section A of FIG. 9;
FIG. 11 is a schematic transverse end view of the base;
fig. 12 is an enlarged schematic view of a portion B of fig. 11.
In the figure: 1-needle electrode, 2-insulating filler, 3-grounding outer ring, 4-needle electrode a, 5-grounding wire, 6-conductive ring, 7-circuit substrate, 8-auxiliary support
Detailed Description
The invention will be further described in detail with reference to the following drawings and specific examples, which are not intended to limit the invention, but are for clear understanding.
As shown in FIG. 1, a method for fabricating a fully anti-static substrate for integrated circuits comprises
S1: a plurality of ground lines 5 are etched on the circuit board 7 at the same pitch and in parallel with each other.
As shown in FIG. 3, the copper-attached layer is etched by a single-copper-face circuit board with the thickness of 0.12mm, the width of 8cm and the height of 30cm under the positioning of a positioning pin to form copper-attached wires with the width of 0.8mm, and the interval between every two copper-attached wires is also 0.8 mm.
S2: n needle-shaped electrodes 1 with the same length are fixed on a grounding wire 5 in parallel along the direction vertical to the grounding wire 5 through a conducting ring 6;
as shown in fig. 2, this step further includes S201 to S206:
s201: n needle electrodes 1 with the same length are fixed in parallel by an auxiliary bracket 7. The auxiliary support 7 is a rectangular frame with the width of 10cm and the height of 33cm, and equidistant clamping grooves are uniformly formed in the positions, corresponding to the upper portion and the lower portion of the needle electrode 1, of the upper end and the lower end of the frame. In the embodiment, the spacing between the slots is 0.4mm, and a plurality of film-covered wires (i.e. electrodes in the present embodiment) with the length slightly greater than 33cm (in this case, 22 rows, the last row is 23, and the last one is a bare copper wire) are fixed on the slots of the stent, as shown in fig. 5. The voltage mutagenesis resistance film covered wire in the scheme comprises a conductive core wire and a voltage mutagenesis resistance film coated outside the core wire. It is also possible to use a voltage-induced resist-covered wire having a wire diameter of 0.15mm as in patent No. ZL 201210557353.2. The scheme is not limited to the voltage-induced film-blocking envelope, and the film envelope which can meet the particle tunneling effect is within the protection range of the scheme.
S202: the needle electrode 1 is plated with copper by electroplating to form the conductive ring 6. The height of the copper ring is 0.8mm, the wall thickness is 10um, and the interval is 0.3 mm-0.8 mm. The film package wire spacing and number correspond to the pin count of a chip row.
S203: the auxiliary holder is laid on the plane of the ground lines 5 of the circuit board 7 together with the needle electrodes 1 fixed to the auxiliary holder.
S204: the position of the auxiliary support is finely adjusted so that each conductive ring 6 is completely overlapped with the ground wire 5 in the height direction.
S205: the first conducting rings 6 at the head and the end of the row of the needle electrode 1 are respectively marked with coordinates.
S206: solder paste is printed at the contact positions of the conductive rings 6 and the grounding wire 5, and reflow soldering is performed to ensure that each conductive ring 6 is electrically connected with the grounding wire 5.
S3: and (3) injecting insulating filling slurry, and cutting the edges of the matrix formed by injection molding to expose the two ends of the grounding wire 5 and the upper and lower ends of each needle electrode 1, so as to form a single-layer electrode matrix only provided with one row of needle electrodes. When the insulating filling paste is injected, the surface of the insulating filling paste is flush with the surface of the conducting ring 6. And then putting the substrate into a temperature box, setting the temperature to be 150 ℃, and curing to obtain a single-layer needle-shaped electrode substrate.
S4: and repeating the operations to obtain M single-layer electrode matrixes, wherein when the Mth single-layer electrode matrix is manufactured, a needle electrode a 4 is additionally arranged at the tail of the line, and the needle electrode a 4 is a metal bare wire which is in conductive connection with the grounding wire of the last line.
S5: m single-layer electrode substrates are laminated and solidified into a cuboid base blank a.
A first single-layer electrode matrix is placed on a positioning plane in a mode that a needle-shaped electrode 1 faces upwards, special resin slurry is coated, then a second single-layer electrode matrix is placed on the first single-layer electrode matrix in the same direction, and the first conducting rings 6 at the head and the tail of a row are ensured to be coincided with the previous layer in the paving and pasting process. And (5) repeatedly laying until the M single-layer electrode matrixes are completely laid, putting the M single-layer electrode matrixes into a temperature box, and curing at high temperature to obtain a base blank a. Because one more needle electrode 1 is arranged in the last single-layer electrode substrate, the first conducting ring 6 in the last but one row is aligned with the first conducting ring 6 at the tail of the last row.
S6: plating copper and nickel around the base blank, and connecting all the grounding electrodes in parallel to form a base blank b.
S7: and slicing the base blank b along the gap direction of the adjacent grounding wires 5 to obtain a plurality of integrated circuit fully antistatic bases, wherein each integrated circuit fully antistatic base is provided with an array formed by 441 needle-shaped electrodes 1.
In the scheme, N is the column number of the ball grid array pins of the protected chip, and M is the row number of the ball grid array pins of the protected chip. The arrangement pitch is the distance between the center point of an electrode and the center point of an adjacent electrode. The needle-like electrodes 1 are usually arranged at 6 different pitches, such as 0.4mm, 0.5mm, 0.6mm, 0.8mm, 1.0mm, 1.27mm, in both the lateral and longitudinal directions, depending on the kind of chip. In this embodiment, the needle electrodes 1 are 22 rows and 22 columns, wherein the last row is 23 electrodes.
The base structure manufactured by the present solution is shown in fig. 7-12, and the base includes a needle electrode 1, a conductive ring 6, a grounding wire 5, an insulating filler 2 and a grounding outer ring 3. The needle electrodes 1 are voltage-induced resistance film covered wires, and as shown in fig. 3 and 4, the needle electrodes 1 are distributed in the grounding outer ring 3 in an array mode. Each row of needle electrodes 1 is vertically provided with a grounding wire 5, each needle electrode 1 is tightly sleeved with a conducting ring 6, the conducting ring 6 is electrically connected with the grounding wire 5, two ends of the grounding wire 5 are electrically connected with the grounding outer ring 3, the grounding outer ring 3 is hermetically fixed with the needle electrodes 1, the conducting rings 6 and the grounding wire 5 through insulating fillers 2, and two ends of each needle electrode 1 are not lower than the surface of the insulating fillers 2. The last row of the needle-shaped electrodes 1 is additionally provided with a needle-shaped electrode a 4 at the tail of the row, and the needle-shaped electrode a 4 is a metal bare wire which is in conductive connection with the grounding wire 5 at the last row. The ground outer ring 3 is a conductive layer plated around the insulating filler 2. All the needle electrodes 1 can be connected to the grounded needle electrode a 4 by the grounded outer ring 3.
The conducting ring 6 and the core wire covered by the conducting ring 6 satisfy the particle tunnel relation. The height of the grounding wire 5 is consistent with that of the conductive ring 6 and is smaller than that of the needle-shaped electrode 1. The conductive ring 6 is a metal ring formed by plating around the needle electrode 1. The metal ring is a copper ring made by electroplating, the length of the copper ring is 0.8mm, and the thickness of the copper ring is about 10 um. The distance between the two ends of the copper ring and the two ends of the electrode is 0.35mm respectively. The rectangular area formed by the copper ring is more than or equal to 0.5mm2, and the corresponding particle tunnel relation defined by quantum mechanics is formed by the copper ring and the surface expansion area of the film-covered wire core covered by the copper ring.
The insulating filler 2 is formed by filling and sealing special resin slurry, such as graphene resin slurry, and is beneficial to integration of eddy energy of high-voltage turbulence generated during instantaneous high-voltage pulse impact and instantaneous secondary high voltage induced by a scattering magnetic field, and continuous influence caused by repeated induction like resonance generated among high-density pins due to the secondary induction is prevented. In this embodiment, the insulating filler 2 is: 0.3% -30% of graphene, 70% -99.5% of epoxy resin and 0.2% of other materials, and the high-temperature curing material can absorb transient energy caused by secondary induction generated by a high-voltage pulse circuit.
The use method and the working process of the base are as follows:
the existing mature welding process of the ball grid array pin chip is adopted to print solder paste on one surface of a base and implant solder balls, the base is attached to the position of a printed circuit board where a chip pin is installed, then the chip is attached to the base by the same method, reflow welding is carried out, the chip is welded with the base and the base is welded with the printed circuit board, and the grounding pin of the base is connected with the ground of the circuit board. Because the needle-shaped electrode in the cavity of the base is made of the voltage mutagenic resistance film covered wire, the voltage mutagenic resistance film on the voltage mutagenic resistance film covered wire has the function of voltage trigger switch, under normal voltage, the voltage mutagenic resistance film is in an insulating state, when a core wire of the film covered wire induces a higher voltage, the mutagenic resistance film is triggered to jump from the insulating state to a conducting state, the induced high voltage is released to the ground in a current mode (the response time is 1ns), and after the high voltage energy is released, the voltage mutagenic resistance film is restored to the insulating state. After the base is connected with the chip pins, namely, each pin of the chip is connected with a trigger switch controlled by voltage, when any pin in the chip senses a pulse high voltage, the switch function of the voltage mutagenesis resistance film on the surface of one electrode in the base cavity corresponding to the pin is triggered, so that the voltage is subjected to energy release in a current mode along the pin → the voltage mutagenesis resistance film → the metal ring → the grounding wire → the circuit board grounding wire, and the whole internal circuit of the chip is protected by the high-voltage pulse.
Details not described in this specification are within the skill of the art that are well known to those skilled in the art.
Claims (10)
1. A method for manufacturing an integrated circuit full-antistatic base is characterized by comprising the following steps: comprises that
Etching a plurality of grounding wires (5) which have the same distance and are parallel to each other on the circuit substrate (7);
n needle-shaped electrodes (1) with the same length are fixed on a grounding wire (5) in parallel along the direction vertical to the grounding wire (5) through a conducting ring (6);
injecting insulating filling slurry, and cutting the edges of the matrix formed by injection molding to expose two ends of the grounding wire (5) and the upper and lower ends of each needle electrode (1) to form a single-layer electrode matrix only provided with one row of needle electrodes;
repeating the operations to obtain M single-layer electrode matrixes;
laminating and curing M single-layer electrode substrates into a cuboid base blank a;
plating a conductive layer around the cuboid base blank to form a base blank b;
slicing the base blank b along the gap direction of the adjacent grounding wires (5) to obtain a plurality of integrated circuit full-antistatic bases;
n is the column number of the ball grid array pins of the protected chip, and M is the row number of the ball grid array pins of the protected chip.
2. The method of claim 1, wherein the step of forming the fully anti-static base comprises: when the circuit substrate (7) is used for etching the grounding wire, the positioning pin is used for positioning, so that the width of each grounding wire (5) is equal to the height of the conducting ring (6).
3. The method of claim 1, wherein the step of forming the fully anti-static base comprises: n needle electrodes (1) with the same length are fixed in parallel through an auxiliary support, clamping grooves which are arranged at equal intervals and used for fixing the needle electrodes (1) are formed in the auxiliary support, and the clamping grooves are formed in the positions, corresponding to the upper portion and the lower portion of the needle electrodes (1), of the auxiliary support.
4. The method of claim 3, wherein the step of forming the fully anti-static base comprises: after the needle electrodes (1) are fixed on the auxiliary support, the needle electrodes (1) are plated with copper in an electroplating mode to form conducting rings (6), and each needle electrode (1) is plated with a conducting ring (6) at a position corresponding to the grounding wire (5).
5. The method of claim 3, wherein the step of forming the fully anti-static base comprises: also comprises
The auxiliary bracket and the needle-shaped electrodes (1) fixed on the auxiliary bracket are paved on the planes of a plurality of grounding wires (5) of a circuit substrate (7) together;
finely adjusting the position of the auxiliary support to ensure that each conducting ring (6) is completely overlapped with the grounding wire (5) along the height direction;
respectively carrying out coordinate marking on the first conducting rings (6) at the head and the end of the row of the needle-shaped electrode (1);
solder paste is printed at the contact position of the conductive rings (6) and the grounding wire (5), and reflow soldering is carried out, so that each conductive ring (6) is electrically connected with the grounding wire (5).
6. The method of claim 1, wherein the step of forming the fully anti-static base comprises: and when the insulating filling paste is injected, the surface of the insulating filling paste is leveled with the surface of the conducting ring (6).
7. The method of claim 1, wherein the step of forming the fully anti-static base comprises: placing the single-layer electrode substrates in a mode that the needle-shaped electrodes (1) face upwards, and curing each single-layer electrode substrate layer by layer in a mode of coating insulating filling slurry until M single-layer electrode substrates are cured into a whole;
in the curing process, the first M-1 layers need to ensure that the first conducting rings (6) at the head and the tail of the line in each single-layer electrode matrix are superposed with the previous layer.
8. The method of claim 1, wherein the step of forming the fully anti-static base comprises: when the Mth single-layer electrode matrix is manufactured, a needle electrode a (4) is additionally arranged at the tail of the row, and the needle electrode a (4) is a metal bare wire which is in conductive connection with the grounding wire of the last row.
9. The method of claim 1, wherein the step of forming the fully anti-static base comprises: the needle-shaped electrode (1) is a voltage mutagenesis resistance film covered wire and is manufactured by coating a voltage mutagenesis resistance film outside a conductive core wire.
10. The method of claim 1, wherein the step of forming the fully anti-static base comprises: the insulating filler (2) is formed by filling and sealing the insulating filling slurry, and the insulating filler (2) is a high-temperature curing material which contains 0.3% -30% of graphene, 70% -99.5% of epoxy resin and 0.2% of other materials and has the function of absorbing transient energy caused by secondary induction generated by high-voltage pulse voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110379155.0A CN113257680B (en) | 2021-04-08 | 2021-04-08 | Method for manufacturing fully antistatic base of integrated circuit |
Applications Claiming Priority (1)
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2010147442A (en) * | 2008-12-22 | 2010-07-01 | Panasonic Electric Works Co Ltd | Flexible printed wiring board, method of manufacturing the same, and flexible printed circuit board |
| CN205211713U (en) * | 2015-11-27 | 2016-05-04 | 天水华天集成电路包装材料有限公司 | Automatic antistatic liquid device that coats in integrated circuit boundary belt surface |
| CN110062519A (en) * | 2019-04-15 | 2019-07-26 | 武汉芯宝科技有限公司 | Multilayer Instantaneous high-pressure pulse energy absorbs bi-symmetric matrix plate and circuit board and its manufacturing method |
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| ES2883242T3 (en) * | 2015-09-26 | 2021-12-07 | Alpha Innovation Inc | Static Eliminator |
| CN107635385B (en) * | 2017-07-31 | 2024-04-30 | 武汉芯宝科技有限公司 | ESD full-shielding functional foil, full-shielding functional foil circuit board and manufacturing method |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010147442A (en) * | 2008-12-22 | 2010-07-01 | Panasonic Electric Works Co Ltd | Flexible printed wiring board, method of manufacturing the same, and flexible printed circuit board |
| CN205211713U (en) * | 2015-11-27 | 2016-05-04 | 天水华天集成电路包装材料有限公司 | Automatic antistatic liquid device that coats in integrated circuit boundary belt surface |
| CN110062519A (en) * | 2019-04-15 | 2019-07-26 | 武汉芯宝科技有限公司 | Multilayer Instantaneous high-pressure pulse energy absorbs bi-symmetric matrix plate and circuit board and its manufacturing method |
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