CN113220240A - Non-volatile memory chip - Google Patents
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- CN113220240A CN113220240A CN202110578244.8A CN202110578244A CN113220240A CN 113220240 A CN113220240 A CN 113220240A CN 202110578244 A CN202110578244 A CN 202110578244A CN 113220240 A CN113220240 A CN 113220240A
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- 230000015654 memory Effects 0.000 claims abstract description 44
- 238000013500 data storage Methods 0.000 abstract description 4
- 239000004065 semiconductor Substances 0.000 description 7
- 230000002457 bidirectional effect Effects 0.000 description 3
- 230000002035 prolonged effect Effects 0.000 description 2
- 239000011232 storage material Substances 0.000 description 2
- 230000003712 anti-aging effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0604—Improving or facilitating administration, e.g. storage management
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/062—Securing storage systems
- G06F3/0622—Securing storage systems in relation to access
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
- G06F3/0652—Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
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Abstract
The invention discloses a nonvolatile memory chip, which comprises a timing circuit, a read-write control circuit and a memory array, wherein the timing circuit is used for reading and writing data; the storage array includes a primary storage area; the main storage area is used for storing conventional data; the timing circuit starts timing when the nonvolatile memory chip leaves a factory, and when the timing time reaches a set time, a chip service life expiration signal is output to the read-write control circuit; when receiving a chip life expiration signal sent by the timing circuit, the read-write control circuit reads and stores the data in the main storage area, then performs an erasing operation on the main storage area, and then rewrites the data read and stored from the main storage area into the main storage area. The nonvolatile memory chip can effectively prolong the data storage life of the nonvolatile memory chip, improve the data security and save the chip cost.
Description
Technical Field
The invention relates to the technical field of memories, in particular to a nonvolatile memory chip.
Background
Conventional semiconductor non-volatile memories are typically comprised of a charge storage memory cell, which is a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) having a layer of charge storage material under a control gate and over a MOSFET channel, and an access MOSFET. The amount of charge in the charge storage material can affect the threshold voltage applied to the control gate to turn on the channel of the MOSFET memory cell. The threshold voltage of an N-type semiconductor memory cell shifts to a higher voltage due to the storage of electrons (negative charges) in the charge storage layer. However, the threshold voltage of the P-type semiconductor memory cell shifts to a lower voltage due to the storage of electrons (negative charges) in the charge storage layer. If the charge in the storage layer can be retained for a long period (typically greater than 10 years for a typical semiconductor non-volatile memory), the semiconductor memory cell becomes non-volatile. If the Non-Volatile Memory device can perform Multiple erase/program cycles, the Non-Volatile Memory device is a Multiple time Programming Non-Volatile Memory (MTPNVM). Typically, for semiconductor non-volatile memories, the number of erase/program cycles is between thousands and millions of times.
Operations of the nonvolatile memory to store data include an erase operation and a program operation. The erase operation typically includes 2 steps: pre-programming and erasing. The pre-programming is performed by a weak programming operation to program the memory cells to be erased in the memory to a weak programming state, so that the initial states of the memory cells are relatively close to each other. Erasing changes the state of the memory cells to be erased to the erased state. The program operation generally includes 1 program step, and a corresponding memory cell is programmed to a program state according to data required to be stored.
In general, when reading data, a read voltage is applied to a word line and a bit line of a memory cell, a read current of the memory cell is supplied to a read circuit through the bit line, and the read circuit compares the magnitude of the memory cell current with a reference current generated separately, and determines the state of the memory cell based on the magnitude of the current. For example, the memory cell current is greater than the reference current, the memory cell is in an erased state, and the corresponding stored data is 1; the memory cell current is less than the reference current, the memory cell is in a programmed state, and the stored data is 0.
The extent to which a memory cell holds data can be affected by various factors. For example: operating voltage, temperature, erase times, data retention time, etc. Due to these factors, the difference between the current of the two states of the memory cell and the reference current may be reduced, and the margin for reading data may be reduced. When the difference between the memory cell current and the reference current is small, a read error risk may occur.
For the anti-aging problem inside the non-volatile memory chip, the existing technologies are as follows:
1) optimized design for bidirectional interlocking storage units (DICE);
2)4, designing a storage unit of the node and the like;
3) various new structures have been proposed for bidirectional interlocked memory units (DICE) to mitigate read disturb and half-select disturb suffered by bidirectional interlocked memory units (DICE).
Disclosure of Invention
The technical problem to be solved by the invention is to provide a nonvolatile memory chip, which can effectively prolong the data storage life of the nonvolatile memory chip, improve the data security and save the chip cost.
In order to solve the above technical problem, the nonvolatile memory chip provided by the present invention comprises a timing circuit, a read-write control circuit, and a memory array;
the storage array comprises a primary storage area;
the main storage area is used for storing conventional data;
the timing circuit starts timing when the nonvolatile memory chip leaves a factory, and outputs a chip service life expiration signal to the read-write control circuit when the timing time reaches a set time;
and when the read-write control circuit receives a chip life expiration signal sent by the timing circuit, the read-write control circuit reads and stores the data in the main storage area, then erases the main storage area, and then rewrites the data read and stored from the main storage area into the main storage area.
Preferably, the memory array further comprises a register area;
the register storage area is a readable and writable storage area and is used as a register for writing the service life extension flag bit, and the initial value of the service life extension flag bit in the register storage area is '1';
the timing circuit starts timing when the nonvolatile memory chip leaves a factory, when the timing time reaches a set time, a chip service life expiration signal is output to the read-write control circuit, the allowed timing times are reduced by 1(n is n-1), the initial value of the allowed timing times (n) is a positive integer, the set time is shortened, and timing is restarted; if the number of times of the allowed timing is greater than 0, making the life extension mark position "1", if the number of times of the allowed timing is equal to 0, making the life extension mark position "0";
the read-write control circuit reads and stores the data in the main storage area if the life extension flag bit read from the register storage area is '1' when receiving a chip life expiration signal sent by the timing circuit, then erases the main storage area, and then rewrites the data read and stored from the main storage area into the main storage area; if the service life extension flag bit read from the register storage area is '0', outputting an alarm trigger signal to an alarm pin of the nonvolatile memory chip;
the alarm pin is used for being externally connected with an alarm circuit;
and the alarm circuit sends alarm information when receiving the alarm trigger signal.
Preferably, the initial set time is 10 years;
the timing circuit outputs a chip life expiration signal every time, and reduces the set duration by half a year;
the initial value of the allowable counting time (n) is 8, 9 or 10.
Preferably, the memory array further comprises a refresh memory area;
and when the read-write control circuit receives a chip life expiration signal sent by the timing circuit, the read-write control circuit reads and stores the data in the main storage area to the refresh storage area, then performs an erasing operation on the main storage area, and reads and writes the data read and stored from the main storage area from the refresh storage area into the main storage area.
Preferably, when the read-write control circuit receives a chip life expiration signal sent by the timing circuit, the read-write control circuit performs an erase operation on the refresh storage area, reads and stores data in the main storage area into the refresh storage area, performs an erase operation on the main storage area, and then reads and writes the data read and stored from the main storage area into the main storage area.
Preferably, the nonvolatile memory is a flash memory.
According to the nonvolatile memory chip, the data in the main storage area of the nonvolatile memory chip is read and stored after the nonvolatile memory chip is set for a set time, then the main storage area of the nonvolatile memory chip is erased, the data read from the main storage area and stored in the main storage area of the nonvolatile memory chip is rewritten in the main storage area of the nonvolatile memory chip, and the data is collected again by rewriting the main storage area of the nonvolatile memory chip, so that the data storage life of the nonvolatile memory chip can be effectively prolonged, the data safety is improved, and the chip cost is saved.
Drawings
In order to more clearly illustrate the technical solution of the present invention, the drawings needed to be used in the present invention are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic structural diagram of a nonvolatile memory chip according to an embodiment of the present invention.
Detailed Description
The technical solutions in the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example one
As shown in fig. 1, the nonvolatile memory chip includes a timing circuit, a read/write control circuit, and a memory array;
the storage array comprises a primary storage area;
the main storage area is used for storing conventional data;
the timing circuit starts timing when the nonvolatile memory chip leaves a factory, and outputs a chip service life expiration signal to the read-write control circuit when the timing time reaches a set time;
and when the read-write control circuit receives a chip life expiration signal sent by the timing circuit, the read-write control circuit reads and stores the data in the main storage area, then erases the main storage area, and then rewrites the data read and stored from the main storage area into the main storage area.
In the nonvolatile memory chip of the first embodiment, after a set time, the nonvolatile memory chip reads and stores the data in the main storage area, erases the main storage area, and then rewrites the data read and stored from the main storage area into the main storage area, so as to recollect the data by rewriting the main storage area, thereby effectively prolonging the data storage life of the nonvolatile memory chip, improving data security, and saving chip cost.
Example two
The nonvolatile memory chip according to the first embodiment, the memory array further includes a register storage area;
the register storage area is a readable and writable storage area and is used as a register for writing the service life extension flag bit, and the initial value of the service life extension flag bit in the register storage area is '1';
the timing circuit starts timing when the nonvolatile memory chip leaves a factory, when the timing time reaches a set time, a chip service life expiration signal is output to the read-write control circuit, the allowed timing times are reduced by 1(n is n-1), the initial value of the allowed timing times (n) is a positive integer, the set time is shortened, and timing is restarted; if the number of times of the allowed timing is greater than 0, making the life extension mark position "1", if the number of times of the allowed timing is equal to 0, making the life extension mark position "0";
the read-write control circuit reads and stores the data in the main storage area if the service life extension flag bit is '1' when receiving a chip service life expiration signal sent by the timing circuit, then erases the main storage area, and then rewrites the data read and stored from the main storage area into the main storage area; if the service life extension flag bit is '0', outputting an alarm trigger signal to an alarm pin of the nonvolatile memory chip;
the alarm pin is used for being externally connected with an alarm circuit;
and the alarm circuit sends alarm information when receiving the alarm trigger signal.
Preferably, the initial set time is 10 years;
the timing circuit outputs a chip life expiration signal every time, and reduces the set duration by half a year;
the initial value of the allowable counting time (n) is 8, 9 or 10.
The nonvolatile memory chip of the second embodiment can automatically perform multiple rounds of reading and writing on stored data in the main storage area of the nonvolatile memory chip, so that the purpose of prolonging the service life of the memory chip is achieved; the read-write control circuit determines whether to carry out a new round of read-write on the stored data in the main storage area according to the state of the service life extension zone bit in the register storage area so as to prolong the service life of the memory chip; if the state of the service life prolonging flag bit in the register storage area is '0', the service life of the memory chip does not need to be prolonged (the service life of the memory chip is expired), an alarm trigger signal is output to an external alarm circuit, the alarm circuit is triggered to send out alarm information, and the alarm is continued until human intervention.
EXAMPLE III
The nonvolatile memory chip according to the first embodiment, wherein the memory array further includes a refresh memory area;
and when the read-write control circuit receives a chip life expiration signal sent by the timing circuit, the read-write control circuit reads and stores the data in the main storage area to the refresh storage area, then performs an erasing operation on the main storage area, and reads and writes the data read and stored from the main storage area from the refresh storage area into the main storage area.
Preferably, when the read-write control circuit receives a chip life expiration signal sent by the timing circuit, the read-write control circuit performs an erase operation on the refresh storage area, reads and stores data in the main storage area into the refresh storage area, performs an erase operation on the main storage area, and then reads and writes the data read and stored from the main storage area into the main storage area.
Preferably, the nonvolatile memory is a flash memory.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (6)
1. A nonvolatile memory chip is characterized by comprising a timing circuit, a read-write control circuit and a memory array;
the storage array comprises a primary storage area;
the main storage area is used for storing conventional data;
the timing circuit starts timing when the nonvolatile memory chip leaves a factory, and outputs a chip service life expiration signal to the read-write control circuit when the timing time reaches a set time;
and when the read-write control circuit receives a chip life expiration signal sent by the timing circuit, the read-write control circuit reads and stores the data in the main storage area, then erases the main storage area, and then rewrites the data read and stored from the main storage area into the main storage area.
2. The non-volatile memory chip of claim 1,
the memory array further comprises a register store;
the register storage area is a readable and writable storage area and is used as a register for writing the service life extension flag bit, and the initial value of the service life extension flag bit in the register storage area is '1';
the timing circuit starts timing when the nonvolatile memory chip leaves a factory, when the timing time reaches the set time, a chip service life expiration signal is output to the read-write control circuit, the allowed timing times are reduced by 1, the initial value of the allowed timing times is a positive integer, the set time is reduced, and timing is restarted; if the number of times of the allowed timing is greater than 0, making the life extension mark position "1", if the number of times of the allowed timing is equal to 0, making the life extension mark position "0";
the read-write control circuit reads and stores the data in the main storage area if the service life extension flag bit is '1' when receiving a chip service life expiration signal sent by the timing circuit, then erases the main storage area, and then rewrites the data read and stored from the main storage area into the main storage area; if the service life extension flag bit is '0', outputting an alarm trigger signal to an alarm pin of the nonvolatile memory chip;
the alarm pin is used for being externally connected with an alarm circuit;
and the alarm circuit sends alarm information when receiving the alarm trigger signal.
3. The non-volatile memory chip of claim 1,
the initial setting time is 10 years;
the timing circuit outputs a chip life expiration signal every time, and reduces the set duration by half a year;
the initial value of the allowable counting time is 8, 9 or 10.
4. The non-volatile memory chip of claim 1,
the memory array further comprises a refresh storage area;
and when the read-write control circuit receives a chip life expiration signal sent by the timing circuit, the read-write control circuit reads and stores the data in the main storage area to the refresh storage area, then performs an erasing operation on the main storage area, and reads and writes the data read and stored from the main storage area from the refresh storage area into the main storage area.
5. The non-volatile memory chip of claim 4,
when the read-write control circuit receives a chip life expiration signal sent by the timing circuit, the read-write control circuit firstly carries out erasing operation on the refreshing storage area, then reads out and stores the data in the main storage area to the refreshing storage area, then carries out erasing operation on the main storage area, and then reads out and writes the data read out from the main storage area into the main storage area.
6. The nonvolatile memory chip according to any one of claims 1 to 5, wherein the nonvolatile memory is a flash memory.
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| CN202110578244.8A CN113220240A (en) | 2021-05-26 | 2021-05-26 | Non-volatile memory chip |
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| CN202110578244.8A CN113220240A (en) | 2021-05-26 | 2021-05-26 | Non-volatile memory chip |
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