CN113219323A - Device and method for testing connectivity of chip pins and readable storage medium - Google Patents
Device and method for testing connectivity of chip pins and readable storage medium Download PDFInfo
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- CN113219323A CN113219323A CN202110475666.2A CN202110475666A CN113219323A CN 113219323 A CN113219323 A CN 113219323A CN 202110475666 A CN202110475666 A CN 202110475666A CN 113219323 A CN113219323 A CN 113219323A
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- G01R31/2851—Testing of integrated circuits [IC]
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Abstract
The application relates to a device and a method for testing chip pin connectivity and a readable storage medium. The device comprises: the system comprises a chip seat, a chip, a target input and output circuit and a level detection module; the chip holder is used for being connected with the chip through pins; the pins comprise pins to be tested; the chip comprises a protection diode, and the protection diode is connected with the target input and output circuit through the pin to be tested; the level detection module is connected with the pin to be detected and used for detecting the output level value of the pin to be detected under the condition that the target input and output circuit is in the impedance adjusting mode. The device can ensure that the cost of the testing device is low.
Description
Technical Field
The present invention relates to the field of chip technologies, and in particular, to a device and a method for testing connectivity of chip pins, a computer device, and a computer-readable storage medium.
Background
A pin connectivity Test scheme on a programmer generally refers to a Test scheme of Automated Test Equipment (ATE), a 100uA (microampere) constant current source is implemented on a circuit, the constant current source is connected to a burning seat pin through a switching matrix, and voltage is acquired through an Analog to digital converter (ADC) to realize detection of a diode. However, the conventional method uses a large amount of circuits for testing, which results in a significant increase in circuit cost.
Disclosure of Invention
Based on this, the present invention provides a device and a method for testing chip pin connectivity, and a readable storage medium.
A testing device for the connectivity of chip pins comprises a chip holder, a chip, a target input/output circuit and a level detection module;
the chip holder is used for being connected with the chip through pins; the pins comprise pins to be tested;
the chip comprises a protection diode, and the protection diode is connected with the target input and output circuit through the pin to be tested;
the level detection module is connected with the pin to be detected and used for detecting the output level value of the pin to be detected under the condition that the target input and output circuit is in the impedance adjusting mode.
A method of testing pin connectivity of a chip, the method comprising:
configuring a target input/output circuit connected with a pin to be tested into an impedance adjusting mode; the chip is connected with the chip base through the pin to be tested; the chip comprises a protection diode, and the protection diode is connected with the target input and output circuit through the pin to be tested; one end of the pin to be tested is connected with the protection diode, and the other end of the pin to be tested is connected with the target input and output circuit;
detecting the output level value of the pin to be detected in the impedance adjusting mode;
and determining the connectivity between the pin to be tested and the chip holder based on the output level value and the connectivity judgment mode corresponding to the impedance adjusting mode.
A computer device comprising a memory storing a computer program and a processor implementing the steps in the various embodiments of the method of testing chip pin connectivity when the computer program is executed.
A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the steps of the respective embodiments of the method of testing pin connectivity of a chip.
According to the device and the method for testing the connectivity of the chip pins and the readable storage medium, the chip holder is connected with the chip through the pins, the protection diode is connected with the target input and output circuit through the pins to be tested, the level detection module is connected with the pins to be tested and is used for detecting the output level value of the target input and output circuit under the condition that the target input and output circuit is in the impedance adjustment mode, so that the connectivity of the pins to be tested can be detected, and particularly the connectivity between the chip holder and the pins to be tested; in addition, the chip holder, the chip, the target input and output circuit and the level detection module are adopted, so that the chip pin connectivity testing device is simple and convenient to control, and the constant current source in the traditional mode is replaced by different impedance adjusting modes of the input and output circuit, so that the testing device is low in cost.
Drawings
FIG. 1 is a schematic diagram of an apparatus for testing pin connectivity of a chip according to one embodiment;
FIG. 2 is a schematic diagram of a chip pin connectivity test apparatus in a weak pull-up mode in one embodiment;
FIG. 3 is a circuit diagram of a conventional protection diode in one embodiment;
FIG. 4 is a schematic diagram of a chip pin connectivity test apparatus in a weak pull-down mode in one embodiment;
FIG. 5 is a circuit diagram of a conventional protection diode according to another embodiment;
FIG. 6 is a circuit schematic of a target input-output circuit in one embodiment;
FIG. 7 is a schematic structural diagram of an apparatus for testing pin connectivity of a chip according to another embodiment;
FIG. 8 is a flow diagram illustrating a method for testing connectivity of chip pins in one embodiment;
FIG. 9 is a diagram illustrating an internal structure of a computer device according to an embodiment.
Detailed Description
It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without inventive effort based on the embodiments of the present invention, are within the scope of the present invention.
It should be noted that all directional indicators (such as upper, lower, left, right, front and rear … …) in the embodiment of the present invention are only used to explain the relative position relationship between the components, the movement situation, etc. in a specific posture (as shown in the drawings), and if the specific posture is changed, the directional indicator is changed accordingly, and the connection may be a direct connection or an indirect connection.
In addition, the descriptions related to "first", "second", etc. in the present invention are only for descriptive purposes and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present invention.
In one embodiment, as shown in fig. 1, the apparatus for testing pin connectivity of a chip in one embodiment includes a chip holder 110, a chip 120, a target input/output circuit 130, and a level detection module 140. The chip includes pins, including the pin under test 1202. The die pad 110 is used to connect with the die 120 via pins, including the pin under test 1202. The chip 120 includes a protection diode 1204, and the protection diode 1204 is connected to the target input/output circuit 130 through the pin 1202 to be tested. The level detection module 140 is connected to the pin 1202 to be tested, and is configured to detect the output level value of the pin 1202 to be tested when the target input/output circuit 130 is in the impedance adjustment mode.
In particular, the chip holder may be in particular a chip holder of a programmer. The chip may be placed on the chip holder. The chip base is used for being connected with the chip through pins, and the pins comprise pins to be tested. The pins may also include other types of pins, such as clock pins, etc., and are not limited herein.
The chip comprises a protection diode which is positioned in the chip and is connected with the target input and output circuit in series through a pin to be tested. The protection diode is used for preventing abnormal voltage of the pin from damaging an internal circuit of the integrated chip, so that the integrated chip is protected. The cathode and anode connections of the protection diode may have different connections in different chips. The protection diode is connected with the target input and output circuit through the pin to be tested to form a loop. The target input and output circuit can be connected with a power supply end or used as a power supply end and protects the cathode grounding end of the diode; or the anode of the protection diode is connected with the power supply end and the target input and output circuit is grounded.
The level detection module is connected with the pin to be detected, and the power supply detection module is used for detecting the output level value of the pin to be detected so as to determine the connectivity of the pin to be detected and the chip holder. The output level value is used for determining whether the output level of the pin to be tested is at a high level or a low level according to a certain judgment mode so as to determine the connectivity between the pin to be tested and the chip holder. The level detection module may be, but is not limited to, a voltmeter, a multimeter, a micro control unit, and the like.
The impedance adjustment mode refers to being in a pull-up resistance mode or being in a pull-down resistance mode. Specifically, the level detection module may be configured to detect the output level value of the pin to be tested when the target input/output circuit is in the impedance adjustment mode corresponding to the connection relationship with the protection diode.
In the device for testing connectivity of chip pins in this embodiment, the chip holder is connected to the chip through pins, the protection diode is connected to the target input/output circuit through the pins to be tested, and the level detection module is connected to the pins to be tested and is configured to detect an output level value of the target input/output circuit when the target input/output circuit is in an impedance adjustment mode, so as to be able to detect connectivity of the pins to be tested, particularly connectivity between the chip holder and the pins to be tested; in addition, the chip holder, the chip, the target input and output circuit and the level detection module are adopted, so that the chip pin connectivity testing device is simple and convenient to control, and the constant current source in the traditional mode is replaced by different impedance adjusting modes of the input and output circuit, so that the testing device is low in cost.
In one embodiment, as shown in fig. 2, a schematic diagram of a chip pin connectivity test apparatus in a weak pull-up mode in one embodiment is shown. The cathode of the protection diode 1204 is connected to ground and the anode of the protection diode 1204 is connected to the pin 1202 to be tested. The impedance adjusting mode includes a weak pull-up mode, in which the target input/output circuit 130 includes a pull-up resistor 1302, one end of the pull-up resistor 1302 is connected to the pin 1202 to be tested, and the other end of the pull-up resistor 1302 is connected to the power supply.
The protection diode is positioned in the chip, the cathode of the protection diode is connected with the ground, and the anode of the protection diode is connected with the pin to be tested in the chip. The impedance adjustment mode includes a weak pull-up mode. The weak pull-up means that the resistance value of the pull-up is large, so that the current is small, the forward current loaded on the protection diode is small, and the risk of burning chip pins is reduced.
In the weak pull-up mode, the target input/output circuit serves as a power supply end, one end of the pull-up resistor is connected with the pin to be tested, and the other end of the pull-up resistor is connected with the power supply. Therefore, the input end of the pull-up resistor is connected with the power supply, the output end of the pull-up resistor is connected with the pin to be tested, the pin to be tested is connected with the anode of the protection diode, and the cathode of the protection diode is connected with the ground to form a loop. The level detection module is used for detecting the output level value of the pin to be detected. When the output level value is detected to be smaller than the first preset level value, the connection between the pin to be tested and the chip holder is determined; and when the output level value is detected to be larger than the first preset level value, determining that the pin to be tested is not communicated with the chip holder.
The resistance value of the pull-up resistor in the embodiment of the application is about 28k omega (kilo ohm), the range is 27 k omega-30 k omega, and the forward voltage loaded on the protection diode can be limited within 100 uA-150 uA. The pull-up resistance value in the embodiment of the application is compared with the traditional mode that the forward current of the protection diode is possibly larger than 1mA (milliampere) through the resistance of 2k omega-3.3 k omega, and the chip pin can be prevented from being damaged due to the fact that the current is too large, so that the circuit is safer.
In this embodiment, a loop is formed by the pull-up resistor, the protection diode, the pin to be tested, and the like in the target input/output circuit to perform electrical signal transmission, so that whether the connectivity between the programmer and the chip pin is good or not can be judged, and the pin which is not well connected between the chip holder and the integrated chip can be indicated.
In one embodiment, the pins of the chip except the pin to be tested are respectively connected with the output circuits. And the level detection module is also used for configuring the input and output circuits corresponding to other pins except the pin to be detected in the chip into a grounding mode.
Specifically, the chip has other pins besides the pin to be tested, and the other pins are respectively connected with the input/output circuits. I.e. one pin for each input-output circuit. For example, a chip has 8 pins, and the 8 pins each correspond to an input/output circuit, and thus, the total number of the pins corresponds to 8 input/output circuits. Moreover, the circuit structures of the input and output circuits corresponding to all the pins of the same chip may be the same.
The level detection module is connected with each input/output circuit. That is, one level detection module may correspond to a plurality of input/output circuits. The level detection module is used for configuring the input and output circuits corresponding to other pins except the pin to be tested in the chip into a grounding mode.
Fig. 3 is a schematic circuit diagram of a conventional protection diode in one embodiment. Including VDD, pin 310, and protection diode 320, the anode of protection diode 320 is connected to pin 310, and the cathode of protection diode 320 is connected to VDD. Then, when the voltage of the pin is greater than the VDD voltage, the protection diode between the pin and the VDD is conducted, and the current flows to the VDD from the pin, so that the abnormal voltage of the pin can be prevented from damaging the internal circuit of the chip. The pin corresponding to GND in fig. 2 is originally a VDD pin, and is configured in a ground mode, and becomes a ground terminal. Then fig. 2 can be used to detect the protection diode between the chip VDD and the pin.
In this embodiment, each pin except the pin to be tested in the chip is connected to each input/output circuit, and the level detection module is further configured to configure the input/output circuits corresponding to the other pins except the pin to be tested in the chip in a ground mode, so that a loop can be formed and detection of the pin to be tested is not affected; and the corresponding impedance adjusting mode is configured based on the connection relation of the protection diode, so that the test of the connectivity of the chip pin can be realized, the control is convenient, and the cost is lower.
In one embodiment, as shown in fig. 4, a schematic diagram of a chip pin connectivity test apparatus in a weak pull-down mode in one embodiment is shown. The cathode of the protection diode 1204 is connected to the pin 1202 to be tested, and the anode of the protection diode 1204 is connected to the power supply. The impedance adjustment mode comprises a weak pull-down mode; in the weak pull-down mode, the target i/o circuit 130 includes a pull-down resistor 1304, one end of the pull-down resistor 1304 is connected to the pin 1202 to be tested, and the other end of the pull-down resistor 1304 is connected to ground.
The protection diode is positioned in the chip, the cathode of the protection diode is connected with the pin to be tested, and the anode of the protection diode is connected with the power supply. The impedance adjustment mode includes a weak pull-down mode. The weak pull-down means that the resistance value of the pull-down is large, so that the current is small, the forward current loaded on the protection diode is small, and the risk of burning the chip pins is reduced.
In the weak pull-down mode, the anode of the protection diode is connected with the power supply through any pin of the chip except the pin to be tested, and the cathode of the protection diode is connected with the pin to be tested. Therefore, the anode of the protection diode is connected with the power supply, the cathode of the protection diode is connected with the pull-down resistor through the pin to be tested, and the other end of the pull-down resistor is connected with the ground to form a loop. The level detection module 140 is used for detecting the output level value of the pin to be tested. Determining the connection between the pin to be tested and the chip holder under the condition that the output level value is detected to be larger than a second preset level value; and under the condition that the output level value is detected to be smaller than a second preset level value, determining that the pin to be tested is not communicated with the chip holder.
In the embodiment, a loop is formed by the pull-down resistor, the protection diode, the pin to be detected and the like in the target input and output circuit to carry out electric signal transmission, so that whether the connectivity between the programmer and the chip pin is good or not can be judged, the pin which is not well connected between the chip holder and the integrated chip can be indicated, the control is convenient, and the switching cost of using the pull-up resistor and the pull-down resistor to replace a constant current source is low.
In one embodiment, the pins of the chip other than the pin under test 1202 are connected to input/output circuits, respectively. The level detection module 140 is further configured to configure the input/output circuits corresponding to the other pins in the chip except the pin 1202 to be tested into a power mode.
Specifically, the level detection module is configured to configure the input/output circuits corresponding to the pins of the chip except the pin to be tested into a ground mode. Fig. 5 is a schematic circuit diagram of a conventional protection diode in another embodiment. The protection diode 520 is connected with the pin 510, and the anode of the protection diode 520 is connected with the pin 510. Then, when the voltage of the pin 510 is less than VSS, the diode between the pin 510 and VSS is turned on, and current flows from VSS to the pin 510, so as to prevent the abnormal voltage of the pin 510 from damaging the internal circuit of the ic, thereby protecting the ic. The pin 510 corresponding to VCC in fig. 4 is originally the VSS pin 510, and is configured in the power mode to be VCC. Then fig. 4 may be used to detect the protection diode 520 between the chip VSS and the pin 510.
In this embodiment, the pins except the pin to be tested in the chip are respectively connected to the input and output circuits, the level detection module is further configured to configure the input and output circuits corresponding to the pins except the pin to be tested in the chip in a power mode, so that a loop can be formed without affecting the detection of the pin connectivity, and the corresponding impedance adjustment mode is configured based on the connection relationship of the protection diode, so that the test of the pin connectivity of the chip is realized, and the chip is convenient to control and low in cost.
In one embodiment, level detection module 140 includes a micro-control unit; the micro control unit is used for controlling the target input/output circuit 130 to switch to the impedance adjusting mode.
The micro control Unit is an MCU (micro controller Unit), also called a single chip microcomputer or a single chip microcomputer, and is a chip-level computer formed by appropriately reducing the frequency and specification of a central processing Unit, and is used for different controls for different applications. The micro control unit can be used for controlling the target input and output circuit to be switched to an impedance adjusting mode and detecting the output level value of the pin to be detected through a specific interface of the target input and output circuit.
In this embodiment, the level detection module includes a micro control unit, and the micro control unit is used to control the target input/output circuit to switch to the impedance adjustment mode, and can automatically switch the circuit during testing without human intervention, thereby improving the testing efficiency.
In one embodiment, the target terminal of the target input/output circuit 130 is connected to the pin to be tested, and the other terminals of the target input/output circuit 130 except the target terminal are accessed to the micro control unit;
the micro control unit is used for outputting an electrical signal to the other terminals of the target input and output circuit 130 except the target terminal, so that the target input and output circuit 130 is switched to different modes, including an impedance adjusting mode.
Specifically, the target input-output circuit includes a plurality of terminals therein. The target end of the target input and output circuit is connected with the pin to be tested, and the other ends except the target end of the target input and output circuit are connected to the micro control unit. The number of the other terminals is not limited, and all the terminals except for the target terminal in the target input-output circuit may be specifically used.
The micro control unit outputs incompletely identical electric signals to the output end of the target input and output circuit, and can control the target input and output circuit to be switched to different modes. The mode can be switched to a power mode, a ground mode, or the like, in addition to the impedance adjusting mode.
Fig. 6 is a circuit diagram of a target input/output circuit in one embodiment. The drawing includes a pull-up resistor 1302, a pin to be tested 1202, a pull-down resistor 1304, and the pin to be tested 1202 connected to a target terminal. Terminals T1, T2, T3, T4 and T5 are connected to the MCU. The micro control unit makes the target input and output circuit in different modes by outputting the electric signals to the terminals T2, T3, T4 and T5. The terminal T1 of the target input/output circuit is used to detect the output level value of the pin 1202 under test. The T2, T3, T4 and T5 terminals of the target input-output circuit correspond to a field effect transistor respectively. It is to be understood that the fets in fig. 6 may be replaced with switches or the like for switching the various modes. When the corresponding field effect transistor at the T2 end is in a connected state and the field effect transistors of T3, T4 and T5 are in an open state, the target input and output circuit is in a power mode. When the corresponding field effect transistor at the T3 terminal is in a connected state and the field effect transistors of T2, T4 and T5 are in an open state, the target input and output circuit is in a grounding mode. When the corresponding field effect transistor at the T4 end is in a connected state and the field effect transistors of T2, T3 and T5 are in an open state, the target input and output circuit is in a weak pull-up mode. When the corresponding field effect transistor at the T5 end is in a connected state, and the field effect transistors of T2, T3 and T4 are in an open state, the target input and output circuit is in a weak pull-down mode.
In this embodiment, a target end of the target input/output circuit is connected to a pin to be tested, other ends of the target input/output circuit except the target end are connected to the micro control unit, and the micro control unit is configured to output an electrical signal to other ends of the target input/output circuit except the target end, so that the target input/output circuit is switched to different modes, where the modes include an impedance adjustment mode, different test functions can be realized through the target input/output circuit, and a circuit does not need to be manually re-established, thereby improving test efficiency.
In one embodiment, as shown in fig. 7, a schematic structural diagram of a device for testing chip pin connectivity in another embodiment is shown. The device for testing the pin connectivity of the chip is applied to a programmer. A programmer is a means of writing data to a programmable integrated circuit. The programmer is mainly used for programming chips such as a single chip microcomputer and a memory. The programmer mainly modifies the program in the read-only memory, and the programmer is usually connected with a computer and then used in cooperation with software programming. The programmer may modify the program in the level detection module such that the level detection module switches to the impedance adjustment mode. The programmer comprises a chip holder, and the chip holder is connected with the chip through pins of the chip. One pin of the chip corresponds to one input/output circuit (i.e., IO circuit). The chip pin is connected with the target end of the input and output circuit. The micro control unit is connected with the other ends of the input and output circuit except the target end. The input-output circuit is used for switching to different modes, such as an impedance adjusting mode, a power supply mode, a grounding mode and the like.
In one embodiment, as shown in fig. 8, a flowchart of a chip pin connectivity test method in one embodiment is shown. A method for testing the connectivity of chip pins is applied to computer equipment and comprises the following steps 802 to 806:
Specifically, the computer device configures a target input-output circuit connected with a pin to be tested into an impedance adjusting mode through a programmer.
And step 804, detecting the output level value of the pin to be detected in the impedance adjusting mode.
Specifically, in the impedance adjusting mode, the computer device detects the output level value of the pin to be tested through the micro control unit on the programmer.
And 806, determining the connectivity between the pin to be tested and the chip holder based on the output level value and the connectivity judgment mode corresponding to the impedance adjustment mode.
And the connectivity judging modes are different for different impedance adjusting modes. For example, when in the weak pull-up mode, the corresponding connectivity determination manner may be whether the connectivity determination manner is smaller than a first preset level value or not; when the weak pull-down mode is used, the corresponding connectivity judgment mode may be whether the connectivity judgment mode is smaller than a second preset level value.
Specifically, the computer device determines connectivity between the pin to be tested and the die pad based on the output level value and the connectivity determination mode corresponding to the impedance adjustment mode.
In this embodiment, the target input/output circuit connected to the pin to be tested is configured to be in an impedance adjusting mode, the output level value of the pin to be tested is detected in the impedance adjusting mode, the connectivity between the pin to be tested and the chip holder is determined based on the output level value and a connectivity determining mode corresponding to the impedance adjusting mode, the chip holder, the chip, the target input/output circuit and the level detecting module are adopted, so that the chip pin connectivity testing device is simple and convenient to control, the constant current source in the traditional mode is replaced by different impedance adjusting modes of the input/output circuit, and the cost of the detecting method is low.
In one embodiment, the cathode of the protection diode is connected with the ground and the anode of the protection diode is connected with the pin to be tested;
the impedance adjustment mode comprises a weak pull-up mode; in the weak pull-up mode, the target input/output circuit comprises a pull-up resistor, one end of the pull-up resistor is connected with the pin to be tested, and the other end of the pull-up resistor is connected with the power supply.
Determining the connectivity between the pin to be tested and the chip holder based on the output level value and the connectivity judgment mode corresponding to the impedance adjustment mode, comprising:
determining that the pin to be tested is communicated with the chip holder under the condition that the output level value is detected to be less than or equal to the first preset level value;
and under the condition that the output level value is detected to be larger than the first preset level value, determining that the pin to be tested is not communicated with the chip holder.
Specifically, the connectivity determination manner corresponding to the weak pull-up mode is whether the connectivity determination manner is smaller than the first preset level value or larger than the first preset level value. Under the condition that the output level value is detected to be smaller than or equal to a first preset level value, the computer equipment determines that the pin to be tested is communicated with the chip base; and under the condition that the output level value is detected to be larger than the first preset level value, the computer equipment determines that the pin to be tested is not communicated with the chip holder.
In this embodiment, the impedance adjusting mode includes a weak pull-up mode, in the weak pull-up mode, the input/output circuit includes a pull-up resistor, one end of the pull-up resistor is connected to the pin to be tested, and the other end of the pull-up circuit is connected to the power supply, and when the output level value is detected to be less than or equal to the first preset level value, it is determined that the output level value is a low level, and it is determined that the pin to be tested is communicated with the die pad; under the condition that the output level value is detected to be larger than the first preset level value, the output level value is indicated to be high level, the fact that the pin to be tested is not communicated with the chip base is determined, whether the connectivity between the programmer and the chip pin is good or not can be judged, the fact that no pin which is well connected between the chip base and the integrated chip is not connected can also be indicated, control is convenient, and switching cost is low due to the fact that a pull-up resistor is used for replacing a constant current source.
In one embodiment, the output terminals of the pins except the pin to be tested in the chip are respectively connected with the input and output circuits.
The method for testing the connectivity of the chip pins further comprises the following steps: and configuring the input and output circuits corresponding to the pins except the pin to be tested in the chip into a grounding mode.
In this embodiment, each pin except the pin to be tested in the chip is connected to each input/output circuit, and the level detection module is further configured to configure the input/output circuits corresponding to the other pins except the pin to be tested in the chip in a ground mode, so that a loop can be formed and detection of the pin to be tested is not affected; and the corresponding impedance adjusting mode is configured based on the connection relation of the protection diode, so that the test of the connectivity of the chip pin can be realized, the control is convenient, and the cost is lower.
In one embodiment, the cathode of the protection diode is connected with the pin to be tested and the anode of the protection diode is connected with the power supply; the impedance adjustment mode comprises a weak pull-down mode; under the weak pull-down mode, the input and output circuit comprises a pull-down resistor, one end of the pull-down resistor is connected with the pin to be tested, and the other end of the pull-down resistor is connected with the ground.
Determining the connectivity between the pin to be tested and the chip holder based on the output level value and the connectivity judgment mode corresponding to the impedance adjustment mode, comprising:
determining the connection between the pin to be tested and the chip holder under the condition that the output level value is detected to be larger than a second preset level value;
and under the condition that the output level value is detected to be less than or equal to a second preset level value, determining that the pin to be tested is not communicated with the chip holder.
Wherein the second preset level value can be set as desired. The second preset level value may be the same as the first preset level value or may be different from the first preset level value.
Specifically, the computer device determines that the pin to be tested is communicated with the chip holder when detecting that the output level value is greater than a second preset level value. And under the condition that the output level value is detected to be smaller than a second preset level value, the computer equipment determines that the pin to be tested is not communicated with the chip holder.
In the embodiment, a loop is formed by the pull-down resistor, the protection diode, the pin to be detected and the like in the target input and output circuit to carry out electric signal transmission, so that whether the connectivity between the programmer and the chip pin is good or not can be judged, the pin which is not well connected between the chip holder and the integrated chip can be indicated, the control is convenient, and the switching cost of using the pull-up resistor and the pull-down resistor to replace a constant current source is low.
In one embodiment, the output terminals of the pins except the pin to be tested in the chip are respectively connected with the input and output circuits.
The detection method of the chip pin connectivity further comprises the following steps: and configuring the input and output circuits corresponding to the pins except the pin to be tested in the chip into a power mode.
In this embodiment, the pins except the pin to be tested in the chip are respectively connected to the input and output circuits, the level detection module is further configured to configure the input and output circuits corresponding to the pins except the pin to be tested in the chip in a power mode, so that a loop can be formed without affecting the detection of the pin connectivity, and the corresponding impedance adjustment mode is configured based on the connection relationship of the protection diode, so that the test of the pin connectivity of the chip is realized, and the chip is convenient to control and low in cost.
In one embodiment, configuring a target input-output circuit connected to a pin under test in an impedance adjustment mode includes: and outputting the electric signals to a plurality of output ends of a target input and output circuit connected with the pin to be tested, so that the target input and output circuit is switched to different modes, wherein the modes comprise an impedance adjusting mode.
Specifically, the computer device outputs electrical signals to a plurality of output terminals of a target input-output circuit connected to a pin under test, so that the target input-output circuit is switched to different modes, including an impedance adjustment mode. The mode may also include a ground mode, a power mode, etc., without being limited thereto.
In this embodiment, the electric signals are output to other terminals of the target input/output circuit except the target terminal, so that the target input/output circuit is switched to different modes, the modes include an impedance adjusting mode, different test functions can be realized through the target input/output circuit, a circuit does not need to be manually re-built, and the test efficiency is improved.
In one embodiment, the programmer and chip pin connectivity test is essentially whether the programmer can measure a protection diode of a chip pin, and if the programmer can measure a diode on the chip pin, the programmer and the chip pin are normally connected; the method for testing the connectivity of the programmer and the integrated chip pin comprises the following steps:
s0, putting the integrated chip into the IC seat on the programmer;
s1 protection diode between VDD and pin of detection integrated chip
S11: except the pins to be tested, all IO circuits of other pins of the programmer IC seat are configured to be in a GND mode.
S12: the IO circuit of the pin to be tested of the programmer IC seat is configured to input a weak pull-up mode.
S13: the MCU measures the level of the pin to be measured, the low level indicates that the protection diode between the VDD and the pin is detected, and the high level indicates that the protection diode between the VDD and the pin is not detected.
And S2, detecting a protection diode between the integrated chip VSS and the pin.
S21: except the pin to be tested, all IO circuits of other pins of the programmer IC seat are configured to be in a VCC mode.
S22: the IO circuit of the pin to be tested of the programmer IC seat is configured to input a weak pull-down mode.
S23: the MCU measures the level of the pin to be detected, wherein the high level indicates that the protection diode between the VSS and the pin is detected, and the low level indicates that the protection diode between the VSS and the pin is not detected.
S3, some IC pins only have a protection diode, and in order to increase the universality, through the two operations S1 and S2, the pin of the programming chip seat can be considered to be communicated with the pin of the IC as long as one protection diode is detected. Even if there are two protection diodes on the ic pin, there are only one protection diode on a small part of the ic, so that detection of one protection diode can be regarded as connection.
S4: after the programming chip seat pins needing to be detected are sequentially subjected to the operations of S1, S2 and S3, whether the connectivity between the programmer and the chip pins is good or not can be judged, and pins which are not well connected between the programmer and the integrated chip can also be indicated.
In the embodiment, the forward current loaded on the protection diode can be limited within 100 uA-150 uA by adding the pull-up and pull-down impedance adjusting circuit, so that the problem of damaging chip pins is avoided. The circuit only needs to add little cost to realize the function.
In one embodiment, a computer device is provided, which may be a terminal device, and its internal structure diagram may be as shown in fig. 9. The computer device includes a processor, a memory, a communication interface, a display screen, and an input device connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device comprises a nonvolatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of an operating system and computer programs in the non-volatile storage medium. The communication interface of the computer device is used for carrying out wired or wireless communication with an external terminal, and the wireless communication can be realized through WIFI, an operator network, NFC (near field communication) or other technologies. The computer program is executed by a processor to implement a method for testing pin connectivity of a chip. The display screen of the computer equipment can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer equipment can be a touch layer covered on the display screen, a key, a track ball or a touch pad arranged on the shell of the computer equipment, an external keyboard, a touch pad or a mouse and the like.
Those skilled in the art will appreciate that the architecture shown in fig. 9 is merely a block diagram of some of the structures associated with the disclosed aspects and is not intended to limit the computing devices to which the disclosed aspects apply, as particular computing devices may include more or less components than those shown, or may combine certain components, or have a different arrangement of components.
In one embodiment, a computer device is provided, which includes a memory and a processor, where the memory stores a computer program, and the processor implements the steps of the above embodiments of the testing method for pin connectivity of each chip when executing the computer program.
In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored, which, when executed by a processor, implements the steps of the above-described embodiments of the testing method for pin connectivity of each chip.
It will be understood by those skilled in the art that all or part of the processes of the methods of the above embodiments may be implemented by hardware related to instructions of a computer program, which may be stored in a non-volatile computer readable storage medium, and when executed, may include the processes of the above embodiments of the methods. Any reference to memory, storage, database or other medium used in the embodiments provided herein can include at least one of non-volatile and volatile memory. Non-volatile Memory may include Read-Only Memory (ROM), magnetic tape, floppy disk, flash Memory, optical storage, or the like. Volatile asperities may include Random Access Memory (RAM) or external cache Memory. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM), among others.
The above description is only a preferred embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes, which are made by using the contents of the present specification and the accompanying drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (15)
1. A testing device for the connectivity of chip pins is characterized by comprising a chip holder, a chip, a target input and output circuit and a level detection module;
the chip holder is used for being connected with the chip through pins; the pins comprise pins to be tested;
the chip comprises a protection diode, and the protection diode is connected with the target input and output circuit through the pin to be tested;
the level detection module is connected with the pin to be detected and used for detecting the output level value of the pin to be detected under the condition that the target input and output circuit is in the impedance adjusting mode.
2. The device according to claim 1, wherein the cathode of the protection diode is connected to ground and the anode of the protection diode is connected to the pin under test;
the impedance adjustment mode comprises a weak pull-up mode; in the weak pull-up mode, the target input/output circuit comprises a pull-up resistor, one end of the pull-up resistor is connected with the pin to be tested, and the other end of the pull-up resistor is connected with a power supply.
3. The device according to claim 2, wherein the pins of the chip except the pin to be tested are respectively connected with input and output circuits;
the level detection module is further configured to configure the input/output circuits corresponding to the pins of the chip except the pin to be tested into a ground mode.
4. The device according to claim 1, wherein the cathode of the protection diode is connected with the pin to be tested and the anode of the protection diode is connected with a power supply;
the impedance adjustment mode comprises a weak pull-down mode; in the weak pull-down mode, the target input/output circuit comprises a pull-down resistor, one end of the pull-down resistor is connected with the pin to be tested, and the other end of the pull-down resistor is connected with the ground.
5. The device according to claim 4, wherein the pins of the chip except the pin to be tested are respectively connected with input and output circuits;
the level detection module is further configured to configure the input/output circuits corresponding to the pins of the chip except the pin to be tested into a power mode.
6. The apparatus according to any one of claims 1 to 5, wherein the level detection module comprises a micro control unit; the micro control unit is used for controlling the target input and output circuit to be switched to different modes, and the modes comprise an impedance adjusting mode.
7. The device according to claim 6, wherein a target terminal of the target input/output circuit is connected to the pin to be tested, and other terminals of the target input/output circuit except the target terminal are connected to the micro control unit;
the micro control unit is used for outputting electric signals to other ends of the target input and output circuit except for the target end, so that the target input and output circuit is switched to different modes, wherein the modes comprise an impedance adjusting mode.
8. A method for testing the connectivity of chip pins, the method comprising:
configuring a target input/output circuit connected with a pin to be tested into an impedance adjusting mode; the chip is connected with the chip base through the pin to be tested; the chip comprises a protection diode, and the protection diode is connected with the target input and output circuit through the pin to be tested; one end of the pin to be tested is connected with the protection diode, and the other end of the pin to be tested is connected with the target input and output circuit;
detecting the output level value of the pin to be detected in the impedance adjusting mode;
and determining the connectivity between the pin to be tested and the chip holder based on the output level value and the connectivity judgment mode corresponding to the impedance adjusting mode.
9. The method according to claim 8, wherein the cathode of the protection diode is connected to ground and the anode of the protection diode is connected to the pin under test;
the impedance adjustment mode comprises a weak pull-up mode; in the weak pull-up mode, the target input/output circuit comprises a pull-up resistor, one end of the pull-up resistor is connected with the pin to be tested, and the other end of the pull-up resistor is connected with a power supply;
the determining connectivity between the pin to be tested and the chip holder based on the output level value and the connectivity judgment mode corresponding to the impedance adjustment mode includes:
determining that the pin to be tested is communicated with the chip base under the condition that the output level value is detected to be less than or equal to a first preset level value;
and under the condition that the output level value is detected to be greater than a first preset level value, determining that the pin to be tested is not communicated with the chip holder.
10. The method according to claim 9, wherein the output terminals of the pins of the chip except the pin to be tested are respectively connected with input and output circuits;
the method further comprises the following steps:
and configuring the input and output circuits corresponding to the pins except the pin to be tested in the chip into a grounding mode.
11. The method according to claim 8, wherein the cathode of the protection diode is connected to the pin under test and the anode of the protection diode is connected to a power supply;
the impedance adjustment mode comprises a weak pull-down mode; in the weak pull-down mode, the input/output circuit comprises a pull-down resistor, one end of the pull-down resistor is connected with the pin to be tested, and the other end of the pull-down resistor is connected with the ground;
the determining connectivity between the pin to be tested and the chip holder based on the output level value and the connectivity judgment mode corresponding to the impedance adjustment mode includes:
determining that the pin to be tested is communicated with the chip holder under the condition that the output level value is detected to be larger than a second preset level value;
and under the condition that the output level value is detected to be less than or equal to a second preset level value, determining that the pin to be tested is not communicated with the chip holder.
12. The method according to claim 11, wherein the output terminals of the pins of the chip except the pin under test are respectively connected to input and output circuits;
the method further comprises the following steps:
and configuring the input and output circuits corresponding to other pins except the pin to be tested in the chip into a power mode.
13. The method according to any one of claims 8 to 12, wherein the configuring the target input-output circuit connected to the pin under test into the impedance adjusting mode comprises:
and outputting electric signals to a plurality of output ends of a target input and output circuit connected with the pin to be tested, so that the target input and output circuit is switched to different modes, wherein the modes comprise an impedance adjusting mode.
14. A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor realizes the steps of the method of any one of claims 8 to 13 when executing the computer program.
15. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method of any one of claims 8 to 13.
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| CN202110475666.2A CN113219323A (en) | 2021-04-29 | 2021-04-29 | Device and method for testing connectivity of chip pins and readable storage medium |
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