CN113177018B - Server using double-slot CPU - Google Patents
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- CN113177018B CN113177018B CN202110449133.7A CN202110449133A CN113177018B CN 113177018 B CN113177018 B CN 113177018B CN 202110449133 A CN202110449133 A CN 202110449133A CN 113177018 B CN113177018 B CN 113177018B
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7803—System on board, i.e. computer system on one or more PCB, e.g. motherboards, daughterboards or blades
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- G06F1/183—Internal mounting support structures, e.g. for printed circuit boards, internal connecting means
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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Abstract
The invention discloses a server using double-slot CPU, comprising: a plurality of dual-slot CPUs, each dual-slot CPU having at least two PCIE x8 slots; the PCIE switcher is provided with a plurality of PCIE x8 slots and is respectively connected to two PCIE x8 slots of the dual-slot CPUs through different PCIE x8 channels; the first PCIE pinboard is connected to the PCIE switcher through two PCIE x8 channels; the first intelligent network card is connected to the first PCIE pinboard through two PCIE x8 channels and is connected to an external network through an external interface; and the baseboard management controller is connected to the PCIE switcher and the first PCIE pinboard, and the baseboard management controller is configured to control the PCIE switcher to conduct the PCIE x8 channels from the two different dual-slot CPUs to the first PCIE pinboard in response to detecting that the first intelligent network card is in place. The invention can improve the adaptation capability and the usability of the Socket Direct topology in practical application, and simultaneously reduces the maintenance cost and the waste of equipment resources.
Description
Technical Field
The present invention relates to the field of computers, and more particularly, to a server using a dual-slot CPU.
Background
As the exponential growth of data, enterprises and cloud providers demand higher performance from servers and computing resources in order to analyze large amounts of data in real-time. The intelligent network card supporting the Multi-Host technology can realize the performance improvement. For example, if a PCIE (peripheral component interconnect express) interface of an intelligent network card is two x8 slots, and the two x8 slots are from different CPUs (central processing units), this enables it to balance the performance of network communication among cores of multiple CPU processors and reduce the overhead.
In the prior art, a common configuration of a data center server is a Multi-Socket (Multi-slot CPU) motherboard and a high-speed network card. The intelligent network card generally adopts a PCIE x16 slot and Socket Direct (Direct Socket topology) server topology to realize Direct access of each CPU in the server to the network, thereby improving the performance of a Dual-Socket (double-slot CPU) server. But the problems of the prior art are as follows:
(1) The scheme is rigid and the adaptation is not flexible. The Dual-Socket has 2 CPUs, each CPU has a plurality of PCIE x16 slots, and each x16 slot can theoretically have 2 x8 slots, and dozens of allocation combinations may be derived. Uplink PCIE x8 cannot be flexibly configured according to design requirements, and only which two x8 slots are used can be fixed at the beginning of design, and cannot be changed at the later stage. It is somewhat flexible if the gating of different x8 slots can be achieved by cables, but with the attendant difficulty of multiplying cable varieties and routing.
(2) Maintenance is difficult. On the basis of the existing scheme, if the cable can be adjusted to other schemes, maintenance personnel are required to stop and reconfigure the wiring.
(3) The configuration resources are wasted. The Multi-Host intelligent network card occupies a PCIE slot of x16, and if other x16 external-plug devices which do not support the Multi-Host are accessed, the external-plug devices may work abnormally. This would clearly be a large configuration waste if the slot were discarded. This waste of configuration is further exacerbated when multiple intelligent network cards need to be supported in the server.
(4) The serial path has low reliability. If the server in the key field is matched with an intelligent network card, when a certain x8 link is abnormal, the whole link cannot be used continuously, and the replacement probability of the whole machine is improved.
Aiming at the problems of the Socket Direct server in the prior art such as dead adaptation, difficult maintenance, resource waste and low robustness, no effective solution is available at present.
Disclosure of Invention
In view of this, an object of the embodiments of the present invention is to provide a server using a dual-slot CPU and a server using a dual-slot CPU, which can improve adaptation capability and availability of a Socket Direct topology in practical applications, and reduce maintenance cost and waste of device resources.
In view of the above object, a first aspect of embodiments of the present invention provides a server using a dual-slot CPU, including:
a plurality of dual-slot CPUs, each dual-slot CPU having at least two PCIE x8 slots;
the PCIE switcher is provided with a plurality of PCIE x8 slots and is respectively connected to two PCIE x8 slots of the dual-slot CPUs through different PCIE x8 channels;
the first PCIE pinboard is connected to the PCIE switcher through two PCIE x8 channels;
the first intelligent network card is connected to the first PCIE pinboard through two PCIE x8 channels and is connected to an external network through an external interface;
and the baseboard management controller is connected to the PCIE switcher and the first PCIE pinboard, and the baseboard management controller is configured to control the PCIE switcher to conduct the PCIE x8 channels from the two different dual-slot CPUs to the first PCIE pinboard in response to detecting that the first intelligent network card is in place.
In some embodiments, the multiple dual-slot CPUs are interconnected via an inter-processor communication bus.
In some embodiments, a PCIE switch is also connected to another server through two PCIE x8 lanes.
In some embodiments, the baseboard management controller is connected to the PCIE switch and the first PCIE patch panel through an I2C bus and/or a GPIO bus.
In some embodiments, the baseboard management controller is configured to confirm that the first intelligent network card is in place if an in-place signal that the first intelligent network card has been plugged into is received from the first PCIE patch board, where the first intelligent network card is compatible with a direct socket topology.
In some embodiments, the PCIE switch has firmware stored therein, and the baseboard management controller is configured to send the first firmware configuration to the PCIE switch so that the firmware of the PCIE switch controls the PCIE switch to conduct PCIE x8 lanes from two different dual-slot CPUs to the first PCIE patch board.
A second aspect of an embodiment of the present invention provides a server using a dual-slot CPU, including:
a plurality of dual-slot CPUs, each dual-slot CPU having at least two PCIE x8 slots;
the PCIE switcher is provided with a plurality of PCIE x8 slots and is respectively connected to two PCIE x8 slots of the double-slot CPUs through different PCIE x8 channels;
the first PCIE pinboard is connected to the PCIE switcher through two PCIE x8 channels;
the second PCIE pinboard is connected to the PCIE switcher through two PCIE x8 channels;
the first intelligent network card is connected to the first PCIE pinboard through two PCIE x8 channels and is connected to an external network through an external interface;
the second intelligent network card is connected to the second PCIE pinboard through two PCIE x8 channels and is connected to an external network through an external interface;
the baseboard management controller is connected to the PCIE switcher, the first PCIE pinboard and the second PCIE pinboard, and the baseboard management controller is configured to control the PCIE switcher to conduct the PCIE x8 channels from the two different double-slot CPUs to the first PCIE pinboard and the second PCIE pinboard in response to detecting that the first intelligent network card and the second intelligent network card are in place.
In some embodiments, the baseboard management controller is configured to confirm that the second intelligent network card is in place if an in-place signal into which the second intelligent network card is plugged is received from the second PCIE patch board, where the second intelligent network card is compatible with a direct socket topology; the PCIE switcher stores firmware, and the baseboard management controller is configured to send first firmware configuration to the PCIE switcher so that the firmware of the PCIE switcher controls the PCIE switches to conduct the PCIE x8 channels from two different dual-slot CPUs to the second PCIE pinboard.
A third aspect of an embodiment of the present invention provides a server using a dual-slot CPU, including:
a plurality of dual-slot CPUs, each dual-slot CPU having at least two PCIE x8 slots;
the PCIE switcher is provided with a plurality of PCIE x8 slots and is respectively connected to two PCIE x8 slots of the dual-slot CPUs through different PCIE x8 channels;
the first PCIE pinboard is connected to the PCIE switcher through two PCIE x8 channels;
the second PCIE pinboard is connected to the PCIE switcher through two PCIE x8 channels;
the first intelligent network card is connected to the first PCIE pinboard through two PCIE x8 channels and is connected to an external network through an external interface;
the second external device is connected to the second PCIE pinboard through a PCIE x16 channel and is connected to an external network through an external interface;
the baseboard management controller is connected to the PCIE switcher, the first PCIE pinboard and the second PCIE pinboard, and the baseboard management controller is configured to respond to the detection that the first intelligent network card and the second external equipment are in place, control the PCIE switcher to conduct the PCIE x8 channels from two different double-slot CPUs to the first PCIE pinboard, and simultaneously control the PCIE switcher to combine the two PCIE x8 channels from the same double-slot CPU to serve as a PCIE x16 channel to conduct to the second PCIE pinboard.
In some embodiments, the baseboard management controller is configured to confirm that the second external device is in place if an in-place signal that the second external device has been plugged in is received from the second PCIE plug board, where the second external device is not compatible with a direct socket topology; the PCIE switcher stores firmware, and the baseboard management controller is configured to send second firmware configuration to the PCIE switcher so that the firmware of the PCIE switcher controls the PCIE switcher to combine two PCIE x8 channels from the same double-slot CPU to serve as one PCIE x16 channel to be conducted to a second PCIE pinboard.
The invention has the following beneficial technical effects: in the server using the dual-slot CPU provided in the embodiment of the present invention, a plurality of dual-slot CPUs are used, and each dual-slot CPU has at least two PCIE x8 slots; the PCIE switcher is provided with a plurality of PCIE x8 slots and is respectively connected to two PCIE x8 slots of the dual-slot CPUs through different PCIE x8 channels; the first PCIE pinboard is connected to the PCIE switcher through two PCIE x8 channels; the first intelligent network card is connected to the first PCIE pinboard through two PCIE x8 channels and is connected to an external network through an external interface; the base plate management controller is connected to the PCIE switcher and the first PCIE pinboard, and the base plate management controller is configured to respond to the technical scheme that the first intelligent network card is detected to be in place and control the PCIE switcher to conduct the PCIE x8 channels from the two different double-slot CPUs to the first PCIE pinboard, so that the adaptation capability and the usability of the Socket Direct topology in practical application can be improved, and meanwhile, the maintenance cost and the equipment resource waste are reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a schematic circuit diagram of one embodiment of a server using a dual-slot CPU according to the present invention;
FIG. 2 is a schematic circuit diagram of another embodiment of a server using a dual-slot CPU according to the present invention;
fig. 3 is a schematic circuit diagram of a server using a dual-slot CPU according to another embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.
It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are merely for convenience of description and should not be construed as limitations of the embodiments of the present invention, and they are not described in any more detail in the following embodiments.
Based on the above purpose, a first aspect of the embodiments of the present invention provides an embodiment of a server using a dual-slot CPU, which improves adaptation capability and availability of a Socket Direct topology in practical applications, and reduces maintenance cost and device resource waste. Fig. 1 is a schematic circuit diagram of a server using a dual-slot CPU according to the present invention.
The server using the dual-slot CPU includes, as shown in fig. 1:
a plurality of dual-slot CPUs, each dual-slot CPU having at least two PCIE x8 slots;
the PCIE switcher is provided with a plurality of PCIE x8 slots and is respectively connected to two PCIE x8 slots of the double-slot CPUs through different PCIE x8 channels;
the first PCIE pinboard is connected to the PCIE switcher through two PCIE x8 channels;
the first intelligent network card is connected to the first PCIE pinboard through two PCIE x8 channels and is connected to an external network through an external interface;
and the baseboard management controller is connected to the PCIE switcher and the first PCIE pinboard, and is configured to control the PCIE switcher to conduct the PCIE x8 channels from the two different double-slot CPUs to the first PCIE pinboard in response to detecting that the first intelligent network card is in place.
In some embodiments, the multiple dual-slot CPUs are interconnected via an inter-processor communication bus.
In some embodiments, a PCIE switch is also connected to another server through two PCIE x8 lanes.
In some embodiments, the baseboard management controller is connected to the PCIE switch and the first PCIE patch panel through an I2C bus and/or a GPIO bus.
In some embodiments, the baseboard management controller detecting that the first intelligent network card is in place includes: the baseboard management controller is configured to confirm that the first intelligent network card is in place if an in-place signal of the first intelligent network card which is plugged in is received from the first PCIE pinboard, wherein the first intelligent network card is compatible with a direct socket topology.
In some embodiments, the controlling the PCIE switch to conduct the PCIE x8 lanes from the two different dual-slot CPUs to the first PCIE patch panel by the baseboard management controller includes: the PCIE switcher is stored with firmware, and the baseboard management controller is configured to send first firmware configuration to the PCIE switcher so that the firmware of the PCIE switcher controls the PCIE x8 channels from two different dual-slot CPUs to be conducted to the first PCIE pinboard.
The following further illustrates embodiments of the invention in accordance with the specific example shown in fig. 1.
The core of the intelligent network card is to assist the CPU to process the network load through FPGA (field programmable gate array) and program the network interface function. The intelligent network card can support the customization of functions of a data plane and a control plane through the FPGA localized programming and assist a CPU in processing network load. The intelligent network card typically includes multiple ports and internal switches, forwards data quickly and maps intelligently to related applications based on network packets, application sockets, etc., while also detecting and managing network traffic.
The intelligent network card can also improve the application program and virtualization performance, realize the advantages of Software Defined Networking (SDN) and Network Function Virtualization (NFV), remove network virtualization, load balancing and other low-level functions from a server CPU, and ensure that the maximum processing capacity is provided for the application. Meanwhile, the intelligent network card can also provide distributed computing resources, so that a user can develop own software or provide access service, and specific application programs are accelerated.
For the intelligent network card, in the traditional Dual-Socket server, only the PCIE slot of the local CPU is connected. If the remote CPU needs to access the network, the remote CPU must pass through the inter-processor communication bus, enter the local CPU and then reach the intelligent network card, and then continue to access the external network. This topology may present a performance bottleneck when data intensive applications compete on different CPUs for access to a single network device.
On the contrary, the remote CPUs in the Dual-Socket server do not need to pass through the interconnection bus among the CPUs, and can be directly interconnected with the intelligent network card through the PCIE bus. In this topology, each PCIE x8 channel can be directly connected to a CPU in the server, and the direct connection of each CPU to the network means that the interconnection can bypass the inter-CPU interconnection bus and another CPU, thereby optimizing performance and improving latency. The Socket Direct topology brings lower delay, so that the utilization rate of the CPUs is improved, and each CPU only processes own flow and does not process the flow from another CPU, so that the advantage of the intelligent network card is exerted, and the investment return of the data center is improved to the maximum extent.
In the implementation mode adopting the Socket Direct topology, two uplink PCIE x8 are respectively from two different CPUs of the Dual-Socket server, and each CPU of the Dual-Socket server has a plurality of PCIE slots. This requires the developer to reserve PCIE x8 lines from different CPUs for the same PCIE patch board at the beginning of the design. The reserved mode can be achieved by routing fixed PCIE slots to the PCIE pinboard through the mainboard, or selectively reserving some PCIE slots to the connectors and then connecting cables to the PCIE pinboard. The intelligent network card is connected to the PCIE pinboard through a PCIE golden finger, so that interaction with two PCIE x8 slots of different CPUs is achieved. The PCIE patch board is only a patch card on the structure, and it may be connected to the server motherboard directly or through a cable, and transmit the PCIE signal to the intelligent network card through the PCIE x16 slot. If the intelligent network card supports cable access to PCIE in the upstream, the intelligent network card can be replaced by a cable in the form.
There is also a Socket Direct system scheme of Dual-Socket server with Adapter. The implementation mode of Socket Direct topology is adopted, and two PCIE x8 uplinks are respectively from two different CPUs of a Dual-Socket server. One of the CPUs is directly interconnected with the PCIE patch board, and the other CPU is connected to another path of PCIE x8 interface of the PCIE patch board through a Direct-connection CPU Adapter (Socket Direct Adapter). The intelligent network card is connected to the PCIE pinboard through a PCIE golden finger, so that interaction with two PCIE x8 slots of different CPUs is achieved. Because the direct-connected CPU adapter card can occupy a universal PCIE slot position on the server, the compatibility of the topology is greatly improved. The direct-connected CPU adapter card is provided with an NIC (intelligent network card), the uplink is connected with the CPU through a PCIE x8 slot position, the downlink is connected with the intelligent network card through a connector and a cable, and the direct-connected CPU adapter card can be used as signal bridging between the CPU and the intelligent network card. One key benefit that it may bring to the Multi-Socket server is the elimination of network traffic through the internal bus of the Multi-CPU, thereby significantly reducing CPU overhead and latency.
However, the above two solutions have the following problems:
(1) The scheme is rigid and the adaptation is not flexible. The Dual-Socket has 2 CPUs, each CPU has a plurality of PCIE x16 slots, and each x16 slot can theoretically have 2 x8 slots, and dozens of allocation combinations may be derived. Uplink PCIE x8 cannot be configured flexibly according to design requirements, and only which two x8 slots are used can be fixed at the beginning of design, and cannot be changed at the later stage. It is somewhat flexible if the gating of different x8 slots can be achieved by cables, but with the attendant difficulty of multiplying cable varieties and routing.
(2) Maintenance is difficult. On the basis of the existing scheme, if the cable can be adjusted to other schemes, maintenance personnel are required to stop and reconfigure the wiring.
(3) The configuration resources are wasted. The Multi-Host intelligent network card occupies a PCIE slot of x16, and if other x16 external-plug devices which do not support the Multi-Host are accessed, the external-plug devices may work abnormally. This is clearly a large configuration waste if the slot is discarded. This waste of configuration is further exacerbated when multiple intelligent network cards need to be supported in the server.
(4) The serial path has low reliability. If the server in the key field is matched with an intelligent network card, when a certain x8 link is abnormal, the whole link cannot be used continuously, and the replacement probability of the whole machine is improved.
On the contrary, the invention further provides a server topology of the self-adaptive multi-master intelligent network card on the basis of the Socket Direct topology. The Multi-Host technology is compatible with two topologies, namely a traditional topology and a Socket Direct topology, after the BMC is adopted to identify the on-site and the type of the intelligent network card, the PCIE Switch (PCIE switcher) is used for flexibly switching the uplink and downlink PCIE channels, so that the self-adaptive intelligent network card adapting Multi-Host technology has the advantages of flexible scheme, convenience in maintenance, easiness in expansion and the like, and is a good choice between performance and investment cost.
Referring to fig. 1, in the embodiment of the present invention, a Socket Direct topology implementation manner is adopted, and a plurality of PCIE x8 uplinks are respectively from two CPUs of a Dual-Socket server (for example, each CPU outputs 2 PCIE x 8). Two PCIE x8 access PCIE Switch (may be collocated on the motherboard or a PCIE add-in card). The PCIE Switch may flexibly configure downstream PCIE according to a defined firmware configuration. For example, 2 PCIE x8 may be from two different CPUs or may be from the same two CPUs. The constituent PCIE x8x8 is given to the PCIE pinboard. If the Multi-Host intelligent network card is connected to the PCIE pinboard through the PCIE golden finger, interaction with two PCIE x8 slots of different CPUs is achieved; if the extrapolation device which does not support the Multi-Host is connected to another set of PCIE slots through the PCIE golden finger, the interaction of PCIE x16 can be realized. According to the number of PCIE channels opened by the PCIE Switch uplink, a plurality of Multi-Host intelligent network card devices can be compatible, and the requirements of various server topology configurations can be met flexibly. In the topology, the BMC is connected to the PCIE pinboard through I2C or GPIO, and identifies whether the Multi-Host intelligent network card is satisfied or not by identifying the in-place and the type of the access equipment; if yes, the BMC informs the PCIE Switch through the I2C bus, and the PCIE Switch configuration register identifies which two x8 slots in the downlink have access to the intelligent network card, and loads the corresponding firmware configuration, thereby automatically enabling 2 x8 pciees of two different CPUs to be connected to the downlink. If necessary, the PCIE Switch may also connect two PCIE x8 slots to the PCIE Switch of another server, so as to implement larger cross-domain Fabric interconnection and access more CPUs or intelligent network card devices.
In the working process, the BMC is connected to the PCIE pinboard through I2C or GPIO, and whether the requirement that the Multi-Host intelligent network card BMC reads the network card type is PCIE x8x8 is identified by identifying the in-place and the type of the access equipment; (PCIE protocol defines that the level of the B82 pin on the X16 slot is used for indicating that the current intelligent network card needs to work at PCIE X8X8 and support Multi-Host; the A32/A33 pin is used for providing a clock signal of the PCIE lane 15-8; and the A50 pin is used for providing a reset signal of the PCIE lane 15-8). If yes, the BMC informs the PCIE Switch through the I2C bus, and the PCIE Switch configuration register identifies which two x8 slots in the downlink have access to the intelligent network card, and loads the corresponding firmware configuration, thereby automatically enabling 2 x8 pciees of two different CPUs to be connected to the downlink. If not, BMC informs PCIE Switch as non-Direct Socket, and allocates two x8 slots of the same CPU to downlink 2 x8 PCIE links. Therefore, the intelligent network card completes PCIE link initialization.
It can be seen from the foregoing embodiments that, in the server using dual-slot CPUs provided in the embodiments of the present invention, multiple dual-slot CPUs are used, and each dual-slot CPU has at least two PCIE x8 slots; the PCIE switcher is provided with a plurality of PCIE x8 slots and is respectively connected to two PCIE x8 slots of the dual-slot CPUs through different PCIE x8 channels; the first PCIE pinboard is connected to the PCIE switcher through two PCIE x8 channels; the first intelligent network card is connected to the first PCIE pinboard through two PCIE x8 channels and is connected to an external network through an external interface; the base plate management controller is connected to the PCIE switcher and the first PCIE pinboard, and the base plate management controller is configured to respond to the technical scheme that the first intelligent network card is detected to be in place and control the PCIE switcher to conduct the PCIE x8 channels from the two different double-slot CPUs to the first PCIE pinboard, so that the adaptation capability and the usability of the Socket Direct topology in practical application can be improved, and meanwhile, the maintenance cost and the equipment resource waste are reduced.
Based on the above purpose, a second aspect of the embodiments of the present invention provides an embodiment of a server using a dual-slot CPU, which improves adaptation capability and availability of a Socket Direct topology in practical applications, and reduces maintenance cost and device resource waste.
The server using the dual-slot CPU includes, as shown in fig. 2:
a plurality of dual-slot CPUs, each dual-slot CPU having at least two PCIE x8 slots;
the PCIE switcher is provided with a plurality of PCIE x8 slots and is respectively connected to two PCIE x8 slots of the dual-slot CPUs through different PCIE x8 channels;
the first PCIE pinboard is connected to the PCIE switcher through two PCIE x8 channels;
the second PCIE pinboard is connected to the PCIE switcher through two PCIE x8 channels;
the first intelligent network card is connected to the first PCIE pinboard through two PCIE x8 channels and is connected to an external network through an external interface;
the second intelligent network card is connected to the second PCIE pinboard through two PCIE x8 channels and is connected to an external network through an external interface;
the baseboard management controller is connected to the PCIE switcher, the first PCIE pinboard and the second PCIE pinboard, and the baseboard management controller is configured to respond to the detection that the first intelligent network card and the second intelligent network card are in place and control the PCIE switcher to conduct the PCIE x8 channels from the two different double-slot CPUs to the first PCIE pinboard and the second PCIE pinboard.
In some embodiments, the detecting, by the baseboard management controller, that the second smart network card is in place includes: the baseboard management controller is configured to confirm that the second intelligent network card is in place if an in-place signal of the second intelligent network card which is plugged in is received from the second PCIE plug board, wherein the second intelligent network card is compatible with direct socket topology; the PCIE x8 channel that baseboard management controller control PCIE switch comes from two different double-slot CPUs switches on to the second PCIE pinboard includes: the PCIE switcher stores firmware, and the baseboard management controller is configured to send first firmware configuration to the PCIE switcher so that the firmware of the PCIE switcher controls the PCIE switches to conduct the PCIE x8 channels from two different dual-slot CPUs to the second PCIE pinboard.
It can be seen from the foregoing embodiment that, in the server using dual-slot CPUs provided in the embodiments of the present invention, multiple dual-slot CPUs are used, where each dual-slot CPU has at least two PCIE x8 slots; the PCIE switcher is provided with a plurality of PCIE x8 slots and is respectively connected to two PCIE x8 slots of the dual-slot CPUs through different PCIE x8 channels; the first PCIE pinboard is connected to the PCIE switcher through two PCIE x8 channels; the first intelligent network card is connected to the first PCIE pinboard through two PCIE x8 channels and is connected to an external network through an external interface; the base plate management controller is connected to the PCIE switcher and the first PCIE pinboard, and the base plate management controller is configured to respond to the technical scheme that the first intelligent network card is detected to be in place and control the PCIE switcher to conduct the PCIE x8 channels from the two different double-slot CPUs to the first PCIE pinboard, so that the adaptation capability and the usability of the Socket Direct topology in practical application can be improved, and meanwhile, the maintenance cost and the equipment resource waste are reduced.
Based on the above purpose, a third aspect of the embodiments of the present invention provides an embodiment of a server using a dual-slot CPU, which improves adaptation capability and availability of a Socket Direct topology in practical applications, and reduces maintenance cost and device resource waste.
The server using the dual-slot CPU includes, as shown in fig. 3:
a plurality of dual-slot CPUs, each dual-slot CPU having at least two PCIE x8 slots;
the PCIE switcher is provided with a plurality of PCIE x8 slots and is respectively connected to two PCIE x8 slots of the dual-slot CPUs through different PCIE x8 channels;
the first PCIE pinboard is connected to the PCIE switcher through two PCIE x8 channels;
the second PCIE pinboard is connected to the PCIE switcher through two PCIE x8 channels;
the first intelligent network card is connected to the first PCIE pinboard through two PCIE x8 channels and is connected to an external network through an external interface;
the second external device is connected to the second PCIE pinboard through a PCIE x16 channel and is connected to an external network through an external interface;
the baseboard management controller is connected to the PCIE switcher, the first PCIE pinboard and the second PCIE pinboard, and is configured to respond to the fact that the first intelligent network card and the second external device are detected to be in place, control the PCIE switcher to conduct the PCIE x8 channels from the two different double-slot CPUs to the first PCIE pinboard, and simultaneously control the PCIE switcher to combine the two PCIE x8 channels from the same double-slot CPU to serve as a PCIE x16 channel to conduct to the second PCIE pinboard.
In some embodiments, the baseboard management controller detecting that the second external device is in place comprises: the baseboard management controller is configured to confirm that the second external device is in place if an in-place signal of the plugged second external device is received from the second PCIE pinboard, wherein the second external device is not compatible with a direct socket topology; the substrate management controller controls the PCIE switcher to merge two PCIE x8 channels from the same double-slot CPU as a PCIE x16 channel to be conducted to a second PCIE pinboard, and the method comprises the following steps: the PCIE switcher stores firmware, and the baseboard management controller is configured to send second firmware configuration to the PCIE switcher so that the firmware of the PCIE switcher controls the PCIE switcher to combine two PCIE x8 channels from the same double-slot CPU to serve as one PCIE x16 channel to be conducted to a second PCIE pinboard.
It can be seen from the foregoing embodiments that, in the server using dual-slot CPUs provided in the embodiments of the present invention, multiple dual-slot CPUs are used, and each dual-slot CPU has at least two PCIE x8 slots; the PCIE switcher is provided with a plurality of PCIE x8 slots and is respectively connected to two PCIE x8 slots of the dual-slot CPUs through different PCIE x8 channels; the first PCIE pinboard is connected to the PCIE switcher through two PCIE x8 channels; the first intelligent network card is connected to the first PCIE pinboard through two PCIE x8 channels and is connected to an external network through an external interface; the base plate management controller is connected to the PCIE switcher and the first PCIE pinboard, and the base plate management controller is configured to respond to the technical scheme that the first intelligent network card is detected to be in place and control the PCIE switcher to conduct the PCIE x8 channels from the two different double-slot CPUs to the first PCIE pinboard, so that the adaptation capability and the usability of the Socket Direct topology in practical application can be improved, and meanwhile, the maintenance cost and the equipment resource waste are reduced.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant only to be exemplary, and is not intended to intimate that the scope of the disclosure, including the claims, is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of an embodiment of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements and the like that may be made without departing from the spirit or scope of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.
Claims (10)
1. A server using a dual-slot CPU, comprising:
a plurality of dual-slot CPUs, each of the dual-slot CPUs having at least two PCIE x8 slots;
a PCIE switch having a plurality of PCIE x8 slots, the PCIE switch being connected to two PCIE x8 slots of the plurality of dual-slot CPUs through different PCIE x8 channels, respectively;
the first PCIE pinboard is connected to the PCIE switcher through two PCIE x8 channels;
the first intelligent network card is connected to the first PCIE pinboard through two PCIE x8 channels and is connected to an external network through an external interface;
the baseboard management controller is connected to the PCIE switcher and the first PCIE pinboard, and the baseboard management controller is configured to respond to the detection that the first intelligent network card is in place and control the PCIE switcher to conduct a PCIE x8 channel from two different double-slot CPUs to the first PCIE pinboard, and the first PCIE pinboard and the intelligent network card are used for conducting communication of a PCIE x16 channel.
2. The server according to claim 1, wherein a plurality of the double-slot CPUs are connected to each other via an inter-processor communication bus.
3. The server of claim 1, wherein the PCIE switches are further coupled to another server through two PCIE x8 lanes.
4. The server of claim 1, wherein the baseboard management controller is connected to the PCIE switch and the first PCIE board by an I2C bus and/or a GPIO bus.
5. The server of claim 1, wherein the baseboard management controller is configured to confirm that the first intelligent network card is in place if an in-place signal that the first intelligent network card is plugged into is received from the first PCIE patch board, wherein the first intelligent network card is compatible with a direct socket topology.
6. The server of claim 5, wherein the PCIE switches have firmware stored therein, the baseboard management controller configured to send a first firmware configuration to the PCIE switches such that the firmware of the PCIE switches controls the PCIE switches to conduct a PCIE x8 channel from two different dual-slot CPUs to the first PCIE pinboard.
7. A server using a dual-slot CPU, comprising:
a plurality of dual-slot CPUs, each of the dual-slot CPUs having at least two PCIE x8 slots;
a PCIE switch having a plurality of PCIE x8 slots, the PCIE switch being connected to two PCIE x8 slots of the plurality of dual-slot CPUs through different PCIE x8 channels, respectively;
the first PCIE pinboard is connected to the PCIE switcher through two PCIE x8 channels;
a second PCIE pinboard connected to the PCIE switcher through two PCIE x8 channels;
the first intelligent network card is connected to the first PCIE pinboard through two PCIE x8 channels and is connected to an external network through an external interface;
the second intelligent network card is connected to the second PCIE pinboard through two PCIE x8 channels and is connected to an external network through an external interface;
the baseboard management controller is connected to the PCIE switcher, the first PCIE pinboard and the second PCIE pinboard, the baseboard management controller is configured to respond to the fact that the first intelligent network card and the second intelligent network card are detected to be in place and control the PCIE switcher to conduct PCIE x8 channels from two different double-slot CPUs to the first PCIE pinboard and the second PCIE pinboard, the first PCIE pinboard and the first intelligent network card are used for conducting communication of PCIE x16 channels, and the second PCIE pinboard and the second intelligent network card are used for conducting communication of PCIE x16 channels.
8. The server according to claim 7, wherein the baseboard management controller is configured to confirm that the second intelligent network card is in place if an in-place signal that the second intelligent network card is plugged into is received from the second PCIE patch board, wherein the second intelligent network card is compatible with a direct socket topology; the PCIE switcher stores firmware, and the baseboard management controller is configured to send first firmware configuration to the PCIE switcher so that the firmware of the PCIE switcher controls the PCIE switches to conduct PCIE x8 channels from two different double-slot CPUs to the second PCIE pinboard.
9. A server using a dual-slot CPU, comprising:
a plurality of dual-slot CPUs, each of the dual-slot CPUs having at least two PCIE x8 slots;
the PCIE switcher is provided with a plurality of PCIE x8 slots and is respectively connected to two PCIE x8 slots of the double-slot CPUs through different PCIE x8 channels;
the first PCIE pinboard is connected to the PCIE switcher through two PCIE x8 channels;
a second PCIE pinboard connected to the PCIE switcher through two PCIE x8 channels;
the first intelligent network card is connected to the first PCIE pinboard through two PCIE x8 channels and is connected to an external network through an external interface;
a second external device connected to the second PCIE patch board through one PCIE x16 channel, and connected to an external network through an external interface;
the baseboard management controller is configured to control the PCIE switch to conduct PCIE x8 channels from two different dual-slot CPUs to the first PCIE pinboard in response to detecting that the first intelligent network card and the second external device are in place, and simultaneously control the PCIE switch to combine the two PCIE x8 channels from the same dual-slot CPU to serve as a PCIE x16 channel to be conducted to the second PCIE pinboard, the first PCIE pinboard and the first intelligent network card perform PCIE x16 channel communication, and the second PCIE pinboard and the second external device perform PCIE x16 channel communication.
10. The server of claim 9, wherein the baseboard management controller is configured to confirm that the second external device is in place if a signal is received from the second PCIE patch panel that the second external device is plugged in, wherein the second external device is not compatible with a direct socket topology; the PCIE switch is stored with firmware, and the baseboard management controller is configured to send a second firmware configuration to the PCIE switch so that the firmware of the PCIE switch controls the PCIE switch to merge two PCIE x8 channels from the same dual-slot CPU as one PCIE x16 channel to be conducted to the second PCIE pinboard.
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| WO2023044725A1 (en) * | 2021-09-24 | 2023-03-30 | Intel Corporation | Methods and apparatus for runtime recovery of processor links |
| CN113886317B (en) * | 2021-09-28 | 2023-07-18 | 苏州浪潮智能科技有限公司 | Method and device for BMC to adapt to multi-platform CPU and storage medium |
| CN116737641A (en) * | 2023-06-26 | 2023-09-12 | 合芯科技有限公司 | Connection device, four-way server, and initialization method and device of four-way server |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110046129A (en) * | 2019-04-17 | 2019-07-23 | 山东超越数控电子股份有限公司 | A kind of two-way server mainboard based on Godson 3B3000 processor |
| CN110515723A (en) * | 2019-08-09 | 2019-11-29 | 苏州浪潮智能科技有限公司 | A kind of two-way server and its equal balance system of cpu load |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102520768B (en) * | 2011-12-29 | 2014-11-26 | 曙光信息产业股份有限公司 | Blade server motherboard and system |
| CN102708034B (en) * | 2012-05-14 | 2015-04-15 | 江苏中科梦兰电子科技有限公司 | Computer remote and local monitoring system based on CPU (central processing unit) with serial port function |
| US9280504B2 (en) * | 2012-08-24 | 2016-03-08 | Intel Corporation | Methods and apparatus for sharing a network interface controller |
| CN204009695U (en) * | 2014-08-21 | 2014-12-10 | 刘文君 | A kind of Loongson server mainboard that has high performance chips group |
| CN110162502A (en) * | 2019-04-15 | 2019-08-23 | 深圳市同泰怡信息技术有限公司 | A kind of server for realizing various configurations based on central processing unit |
| CN211628241U (en) * | 2019-10-12 | 2020-10-02 | 苏州浪潮智能科技有限公司 | PCIE bus structure switching topology through software |
| CN111258667A (en) * | 2020-02-05 | 2020-06-09 | 苏州浪潮智能科技有限公司 | Self-adaptive configuration method, device, equipment and storage medium of server |
| CN111654404B (en) * | 2020-06-28 | 2022-07-12 | 新华三信息技术有限公司 | Intelligent network card management and control method and device |
| CN112134713A (en) * | 2020-08-26 | 2020-12-25 | 苏州浪潮智能科技有限公司 | Method and device for connecting intelligent network card and server |
| CN112181888A (en) * | 2020-08-28 | 2021-01-05 | 苏州浪潮智能科技有限公司 | CPU topology device, electronic equipment and topology switching method |
| CN112181125A (en) * | 2020-08-28 | 2021-01-05 | 苏州浪潮智能科技有限公司 | Data processing method and device based on server and server |
| CN112306952A (en) * | 2020-11-25 | 2021-02-02 | 海光信息技术股份有限公司 | Mainboard and server |
-
2021
- 2021-04-25 CN CN202110449133.7A patent/CN113177018B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110046129A (en) * | 2019-04-17 | 2019-07-23 | 山东超越数控电子股份有限公司 | A kind of two-way server mainboard based on Godson 3B3000 processor |
| CN110515723A (en) * | 2019-08-09 | 2019-11-29 | 苏州浪潮智能科技有限公司 | A kind of two-way server and its equal balance system of cpu load |
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