CN113160726A - Power-on self-detection method and power-on self-detection device - Google Patents
Power-on self-detection method and power-on self-detection device Download PDFInfo
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Abstract
The embodiment of the invention discloses a power-on self-detection method and a power-on self-detection device suitable for a display controller. The power-on self-detection method comprises the following steps: after the power-on, the programmable logic device or the microcontroller detects the self state and judges whether the self state is abnormal or not to obtain a detection result, the detection result is recorded, and the programmable logic device and the microcontroller perform processing operation according to the detection result in response to the abnormality of the detection result. The embodiment of the invention can realize self-detection and record the detection result after the display controller is electrified, so that the display controller can be used for searching, analyzing and troubleshooting fault causes and reduce the difficulty of searching, analyzing and troubleshooting fault causes.
Description
Technical Field
The invention relates to the technical field of equipment detection, in particular to a power-on self-detection method and a power-on self-detection device.
Background
In the LED display screen control system industry, a display controller generally decodes a video source, outputs the video source through a network cable as a medium or through an optical fiber, and then converts an optical fiber interface into a network port through a photoelectric conversion device to connect a display control card, the display control card and the display control card are connected through the network cable and all transmit the video source in a serial connection manner, and a user can perform screen matching operation on a plurality of display control cards carried by the network cable of the display controller on a software interface to realize one-to-one correspondence between the display control cards and video source display pictures, as shown in fig. 1, the connection manner of the display controller controlling the plurality of display control cards carried by the network cable to build an LED display screen is shown.
However, with the development of LED display screens, LED display screens are applied to various places, the applied scenes are more and more complex, the use environments are more and more diverse, the requirements on the stability of the devices are more and more high, whether the hardware of the devices is stable, and whether the devices work in a normal state are also more and more urgent for users to know.
Generally, after a display controller is powered on, a microcontroller directly loads a main program of a programmable logic device, then the programmable logic device is started to finish system power-on of the display controller, then corresponding software can configure the display controller and display the display controller through an LED display screen, however, after the display controller is powered on, a user cannot know whether the display controller works in a normal state, and only can judge whether the working state of the display controller is normal by checking whether a picture is displayed normally after the LED display screen is lightened. When a problem occurs, it is impossible to know whether the problem is caused by abnormality of a hardware circuit or a program bug, and therefore, the difficulty in finding, analyzing and troubleshooting the cause of the fault is high.
Disclosure of Invention
The embodiment of the invention provides a power-on self-detection method and a power-on self-detection device suitable for a display controller, so that the display controller can realize self-detection and record detection results after being powered on, and the power-on self-detection method and the power-on self-detection device are used for searching, analyzing and troubleshooting fault reasons and reduce the difficulty of searching, analyzing and troubleshooting the fault reasons.
In one aspect, a power-on self-detection method provided in an embodiment of the present invention is applicable to a display controller, and includes: after the power-on, the programmable logic device or the microcontroller detects the self state and judges whether the self state is abnormal or not to obtain a detection result, the detection result is recorded, and the programmable logic device and the microcontroller perform processing operation according to the detection result in response to the abnormality of the detection result.
According to the embodiment of the invention, after the display controller is powered on, the programmable logic device or the microcontroller detects the self state to judge whether the self state is abnormal or not so as to obtain the detection result, and the detection result is recorded and stored. And determining the working state of hardware equipment in the display controller for fault reason searching, analyzing and troubleshooting, and reducing the difficulty of fault reason searching, analyzing and troubleshooting.
In one embodiment of the present invention, the self-status detection includes: the method comprises the following steps of video source interface decoding state detection, communication interface state detection, volatile memory initialization state detection, internal communication state detection between a programmable logic device and a microcontroller, and working clock state detection required by the programmable logic device.
In an embodiment of the present invention, when the self-state detection is the volatile memory initialization state detection or the internal communication state detection between the programmable logic device and the microcontroller, the performing the processing operation according to the detection result includes: in response to the detection result is abnormal, reloading a programmable logic device program and then carrying out initialization state detection on the volatile memory or internal communication state detection between the programmable logic device and the microcontroller to obtain a new detection result; and responding to the new detection result abnormity and the reloading times of the programmable logic device program reach the preset loading times, and outputting abnormity prompt information according to the new detection result.
In one embodiment of the invention, the video source interface decoding state detection comprises; reading a field signal, a line signal and an image data effective signal of a current video frame of an input video source; determining the resolution and frame frequency of the current video frame according to the field signal, the line signal and the image data effective signal; and judging whether the resolution and the frame frequency of the current video frame are the same as those of a specified video frame of the input video source or not and obtaining a first judgment result, wherein the result comprises the first judgment result.
In one embodiment of the invention, a display controller includes a communication interface, the communication interface being an ethernet communication interface; the communication interface state detection comprises; reading a first connection state value and a first working state value of the Ethernet communication interface from a PHY chip of the Ethernet communication interface, judging whether the Ethernet communication interface is in a connection state according to the first connection state value, judging whether the Ethernet communication interface is in a working state according to the first working state value in response to the Ethernet communication interface being in the connection state, and analyzing a data packet transmitted by the Ethernet communication interface to obtain a first transmission rate value in response to the Ethernet communication interface being in the working state; analyzing the data packet to obtain first analyzed data, judging whether a communication protocol of the display controller is met or not according to the first analyzed data, and responding to the communication protocol meeting the display controller to obtain a second connection state value, a second working state value and a second transmission rate value according to the first analyzed data; reading an Ethernet communication interface IP core register of the programmable logic device to obtain a third connection state value, a third working state value and a third transmission rate value of the Ethernet communication interface; and judging whether the first connection state value, the second connection state value and the third connection state value are consistent, judging whether the first working state value, the second working state value and the third working state value are consistent, judging whether the first transmission rate value, the second transmission rate value and the third transmission rate value are consistent, and obtaining a second judgment result, wherein the detection result comprises the second judgment result.
In one embodiment of the invention, the display controller comprises a communication interface, the communication interface being a fiber optic communication interface; the communication interface state detection comprises: analyzing a data packet transmitted through the optical fiber communication interface to obtain second analyzed data, judging whether a communication protocol of the display controller is met according to the second analyzed data, and responding to the communication protocol meeting the display controller to obtain a fourth connection state value, a fourth working state value and a fourth transmission rate value according to the second analyzed data; reading an optical fiber communication interface IP core register of the programmable logic device to obtain a fifth connection state value, a fifth working state value and a fifth transmission rate value of the optical fiber communication interface; and comparing whether the fourth connection state value is consistent with the fifth connection state value, whether the fourth working state value is consistent with the fifth working state value, and whether the fourth transmission rate value is consistent with the fifth transmission rate value to obtain a third judgment result, wherein the detection result comprises the third judgment result.
In one embodiment of the invention, the volatile memory initialization state detection comprises: reading an initialization state value of a volatile memory; and judging whether the initialization state value of the volatile memory is abnormal or not to obtain a fourth judgment result, wherein the detection result comprises the fourth judgment result.
In one embodiment of the invention, the internal communication state detection between the programmable logic device and the microcontroller comprises: sending test data to the programmable logic device to be written into the programmable logic device; reading read-back data from the programmable logic device; and judging whether the test data and the read-back data are the same to obtain a fifth judgment result, wherein the detection result comprises the fifth judgment result.
In one embodiment of the present invention, the detecting of the required operating clock state of the programmable logic device comprises: sampling a working clock required by the programmable logic device based on a reference clock to obtain a working clock sampling result; and judging whether the sampling result of the working clock is the same as the preset working clock to obtain a sixth judgment result, wherein the detection result comprises the sixth judgment result.
In another aspect, an embodiment of the present invention provides a power-on self-detection apparatus for executing the power-on self-detection method, including: a self-state detection module, configured to perform self-state detection through the programmable logic device or the microcontroller after power-on, and determine whether the self-state is abnormal to obtain a detection result, where the self-state detection includes: detecting a decoding state of the video source interface, detecting a state of the communication interface, detecting an initialization state of the volatile memory, detecting an internal communication state between the programmable logic device and the microcontroller, and detecting a state of a working clock required by the programmable logic device; the detection result recording module is used for recording the detection result; and the exception handling module is used for carrying out handling operation on the programmable logic device and the microcontroller according to the detection result.
One or more of the above technical solutions may have the following advantages or beneficial effects: according to the embodiment of the invention, the decoding state detection of the video source interface, the state detection of the communication interface, the initialization state detection of the volatile memory, the internal communication state detection between the programmable logic device and the microcontroller, the detection of the working clock state required by the programmable logic device are carried out after the display controller is powered on so as to judge whether the self state is abnormal or not, obtain the detection result and record and store the detection result, so that the working state of the hardware equipment in the display controller is determined, and the method is used for searching, analyzing and troubleshooting the fault reason, and the difficulty of searching, analyzing and troubleshooting the fault reason is reduced. When the detection result shows that the display controller has a problem, the display controller can know whether the problem in the circuit is caused by hardware circuit abnormality or program bug according to the current detection result record, so that the difficulty of troubleshooting the problem is reduced. When the power-on loading of the display controller is in problem, the programmable logic device and the microcontroller can perform related processing according to the error type, so that the working abnormity of the display controller caused by the power-on loading is reduced, and the display controller can work in a stable state.
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In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of an LED display system in the prior art.
Fig. 2 is a flowchart illustrating a power-on self-detection method applied to a display controller according to a first embodiment of the present invention.
Fig. 3 is a schematic structural diagram of the display controller.
Fig. 4 is a block diagram of a power-on self-detection apparatus according to a second embodiment of the present invention.
Fig. 5 is a further block diagram of fig. 4.
Fig. 6 is a schematic structural diagram of a power-on self-detection system according to a third embodiment of the present invention.
Fig. 7 is a schematic structural diagram of a computer-readable storage medium according to a fourth embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
[ first embodiment ] A method for manufacturing a semiconductor device
As shown in fig. 2, a first embodiment of the present invention provides a power-on self-detection method, which is suitable for a display controller. Specifically, the power-on self-detection method provided by the embodiment of the present invention includes, for example, the steps of:
s11: after being electrified, the programmable logic device or the microcontroller detects the self state and judges whether the self state is abnormal or not to obtain a detection result;
s12: and recording the detection result.
S13: and responding to the abnormity of the detection result, and processing operation is carried out through a programmable logic device and a microcontroller according to the detection result.
The power-on detection method provided by the embodiment of the invention is suitable for the display controller. As shown in fig. 3, the display controller 300 includes: a video input interface 310, a microcontroller 320, a programmable logic device 330, a volatile memory 350, a clock chip 360, and a communication interface 370. The video input Interface 310 is connected to the programmable logic device 330, the microcontroller 320 is connected to the programmable logic device 330 through a part or all of an FSMC (flexible static Memory Controller) bus, an SPI (Serial Peripheral Interface) bus, a QSPI (Queued Serial Peripheral Interface) bus, and the like, the volatile Memory 350 is connected to the programmable logic device 330, the clock chip 360 is connected to the programmable logic device 330, and the communication Interface 370 is connected to the programmable logic device 330.
The video input Interface 310 is, for example, an HDMI (High Definition Multimedia Interface) Interface, a DP (display Interface) Interface, a DVI (Digital Visual Interface) Interface, an SDI (serial Digital Interface) Interface, or another video Interface capable of providing a video signal or a virtual video signal.
The Microcontroller 320, such as an MCU (Microcontroller Unit) or an ARM, is used for loading a programmable logic device program, transceiving related control instructions for interaction and communication.
The Programmable logic device 330 is, for example, an FPGA (Field-Programmable Gate Array), and is configured to process input video data and output the processed data to a subsequent device, such as a display control card.
The volatile memory 350 is, for example, a Synchronous Dynamic Random Access Memory (SDRAM), and is used for caching various data (such as original image data and correction data) during operation.
The clock chip 360 provides the reference clock to the programmable logic device 330, and the internal operating clock of the programmable logic device 330 can be obtained through frequency multiplication processing.
A communication interface 370 for transmitting data from the display controller to the display control card. Communication interface 370 may be an ethernet interface such as an RJ45 port or may be a fiber optic communication interface. When the communication interface 370 is an optical fiber communication interface, the display controller may further include a photoelectric conversion module or the display controller is connected to a photoelectric conversion device through the optical fiber communication interface to convert the image data into a data packet recognizable by the display control card.
In addition, the power-on self-detection method of the embodiment of the invention is completed by the mutual cooperation of the microcontroller and the programmable logic device on the display controller, and the specific process is as follows.
Firstly, after the display controller is powered on, carrying out self-state detection and judging whether the self-state is abnormal or not to obtain a detection result, wherein the self-state detection comprises the following steps: the method comprises the following steps of video source interface decoding state detection, communication interface state detection, volatile memory initialization state detection, internal communication state detection between a programmable logic device and a microcontroller, and working clock state detection required by the programmable logic device.
And finally, recording the detection results, wherein the detection results comprise judgment results of detection such as video source interface decoding state detection, communication interface state detection, volatile memory initialization state detection, internal communication state detection between the programmable logic device and a microcontroller, working clock state detection required by the programmable logic device and the like. Of course, the display controller may also save the detection results for troubleshooting, analysis, and troubleshooting.
Further, when the detection result is abnormal, processing operation is performed according to the detection result, for example, abnormal prompt information is output.
Specifically, the video source interface decoding state detection specifically includes: after the display controller is accessed to a video input interface (such as an HDMI interface, a DP interface, a DVI interface, an SDI interface and the like), the FPGA reads a field signal, a line signal and an image data effective signal of a current video frame of an input video source; obtaining the resolution and the frame frequency of the current video frame according to the field signal, the line signal and the effective image data signal; and judging whether the resolution and the frame frequency of the current video frame are the same as those of a specified video frame of the input video source. The specified video frame may be, for example, a frame or several frames before the current video frame, or may be other specified video frames, which is not limited in this disclosure. If the resolution and the frame frequency are the same, the current video source works normally, the display controller transmits the correspondingly detected resolution and frame frequency to the microcontroller and records the resolution and frame frequency, otherwise, the current video source works abnormally, which may cause a problem in decoding of a video source interface, and then transmits the corresponding resolution abnormal information and frame frequency abnormal information to the microcontroller and records the abnormal information. Further, the microcontroller outputs an abnormal prompt message to prompt a user to detect whether the input of the current video source is stable, for example, the user can perform processing such as video source inspection, interface plugging and unplugging, or wire replacement test according to the abnormal prompt message until the video input source is stable. The output abnormal prompt information here may be, for example, the abnormal prompt information is displayed on a display screen of the display controller itself, or the abnormal prompt information may be prompted to a user through an indicator light or the like, or even prompted on screen configuration software installed on an upper computer connected to the display controller, or the like, which is not limited to this.
When the display controller is connected with a display control card of the LED display screen through the Ethernet communication interface, the detection of the state of the communication interface comprises the following steps:
the method comprises the steps that a microcontroller reads a first connection state value and a first working state value of an Ethernet communication interface from a PHY chip of the Ethernet communication interface through a programmable logic device, whether the Ethernet communication interface is in a connection state is judged according to the first connection state value, when the Ethernet communication interface is in the connection state, whether the Ethernet communication interface is in the working state is judged according to the first working state value, when the Ethernet communication interface is in the working state, an FPGA detects a data packet transmitted by the Ethernet communication interface and coming from a display control card, for example, analyzes the data packet to obtain a first transmission rate value, and transmits the first connection state value, the first working state value and the first transmission rate value to the microcontroller;
in addition, the FPGA analyzes the data packet returned by the display control card to obtain first analyzed data, and judges whether the communication protocol of the display controller and the display control card is met or not according to the first analyzed data; when the communication protocol is not satisfied, indicating that the data in the data packet received by the Ethernet communication interface is random data, and if a correct data packet is not received for a long time (the time is far longer than the time for the display control card to transmit the data packet to the display controller at regular time), indicating that the Ethernet communication interface is not in work; when the communication protocol of the display controller and the display control card is met, the FPGA obtains a second connection state value, a second working state value and a second transmission rate value according to the first analyzed data, and transmits the second connection state value, the second working state value and the second transmission rate value to the microcontroller;
furthermore, the FPGA also reads an Ethernet communication interface IP core register of the FPGA to obtain a third connection state value, a third working state value and a third transmission speed value of the Ethernet communication interface, and transmits the third connection state value, the third working state value and the third transmission speed value to the microcontroller;
finally, the microcontroller judges whether the first connection state value, the second connection state value and the third connection state value are consistent, judges whether the first working state value, the second working state value and the third working state value are consistent, judges whether the first transmission speed value, the second transmission speed value and the third transmission speed value are consistent, and obtains a second judgment result. If the second determination result is that the first connection state value, the second connection state value, and the third connection state value are consistent, and the first working state value, the second working state value, and the third working state value are consistent, and the first transmission rate value, the second transmission rate value, and the third transmission rate value are consistent, that is, the data detected by the three methods are completely consistent and matched, it is indicated that the working state of the current communication interface is normal, and data transmission can be performed normally, otherwise, it is indicated that the working state of the current communication interface is abnormal, and abnormal information is recorded. Further, when the current communication interface is in an abnormal working state, the microcontroller outputs an abnormal prompt message to prompt a user to perform corresponding processing, for example, whether the current ethernet communication interface is connected normally, whether the working state is normal, and whether the transmission rate is matched with the rate at which the display controller and the display control card can process data are detected. When the connection state of the Ethernet communication interface is abnormal, a user can perform plugging and unplugging of the Ethernet communication interface or wire replacement test according to the prompt information of the abnormal connection state until the Ethernet communication interface is normally connected; when the working state of the Ethernet communication interface is abnormal, a user can inquire the display controller of the Ethernet communication interface end or check a chip according to the abnormal working state prompt information; when the transmission rate is not matched with the data rate which can be processed by the display controller and the display control card, the user can prompt to replace the display control card or the display controller according to the rate mismatching abnormity until the rate is matched. In addition, the manner of outputting the exception notification information here may be the same as the foregoing manner, and is not described here again.
When the display controller is connected with a display control card through an optical fiber communication interface and a photoelectric conversion device, the state detection of the communication interface comprises the following steps:
the FPGA analyzes a data packet returned by the display control card through the optical fiber communication interface to obtain second analyzed data, and judges whether the communication protocol of the display controller is met or not according to the second analyzed data; when the communication protocol is not satisfied, the data in the data packet received by the optical fiber communication interface is random data, and if the correct data packet is not received for a long time (the time is far longer than the time for the display control card to transmit the data packet to the display controller at fixed time), the optical fiber communication interface is not in work; when the communication protocol of the display controller is met, the FPGA acquires a fourth connection state value, a fourth working state value and a fourth transmission rate value from the second analyzed data, and transmits the fourth connection state value, the fourth working state value and the fourth transmission rate value to the microcontroller;
meanwhile, the FPGA reads an IP core register of an optical fiber communication interface of the programmable logic device to obtain a fifth connection state value, a fifth working state value and a fifth transmission rate value of the optical fiber communication interface, and transmits the fifth connection state value, the fifth working state value and the fifth transmission rate value to the microcontroller;
then, the microcontroller compares whether the fourth connection state value is consistent with the fifth connection state value, whether the fourth working state value is consistent with the fifth working state value, and whether the fourth transmission rate value is consistent with the fifth transmission rate value to obtain a third judgment result. If the third judgment result shows that the fourth connection state value is consistent with the fifth connection state value, the fourth working state value is consistent with the fifth working state value, the fourth transmission rate value is consistent with the fifth transmission rate value, and the data detected by the two methods are completely consistent and matched, it is indicated that the current optical fiber communication interface is normal in working state and can normally transmit data, otherwise, it is indicated that the current optical fiber communication interface is abnormal in working state, and abnormal information is recorded. Further, when the working state of the current communication interface is abnormal, the microcontroller outputs an abnormal prompt message to prompt the user to perform corresponding processing, for example, prompt the user to detect whether the connection of the current optical fiber communication interface is normal, whether the working state is normal, and whether the transmission rate is matched with the rate at which the display controller and the display control card can process data. When the connection state of the optical fiber communication interface is abnormal, a user can perform the test of plugging and unplugging the optical fiber communication interface or replacing an optical fiber wire according to the prompt information of the abnormal connection state until the optical fiber communication interface is normally connected; when the working state of the optical fiber communication interface is abnormal, a user can inquire and check the optical fiber communication interface and the chip of the display controller end or check the Ethernet PHY chip of the display control card end according to the working state abnormity prompt information, or inquire and check the optical fiber communication interface and the Ethernet PHY chip of the photoelectric conversion equipment end; when the transmission rate is not matched with the data rate which can be processed by the display controller and the display control card, the user can replace the display control card or the display controller according to the rate mismatch prompt until the prompt rate is matched. In addition, the manner of outputting the exception notification information here may be the same as the foregoing manner, and is not described here again.
In addition, the volatile memory initialization state detection includes: and the FPGA reads the initialized state value of the volatile memory and sends the initialized state value to the microcontroller for recording, and the microcontroller judges whether the initialized state value of the volatile memory is abnormal or not to obtain a fourth judgment result. If the fourth judgment result is that the volatile memory initialization state value is normal, the volatile memory initialization is successful, otherwise, the volatile memory initialization is failed. Furthermore, the microcontroller reloads the program of the programmable logic device, and the volatile memory initialization state detection is carried out again after the program is loaded; if the new judgment result obtained after reloading and re-detecting still has abnormity, the microcontroller reloads the programmable logic device program again, detects again and repeats the steps; and when the loading times reach the preset loading times and the initialization still cannot be successful, outputting abnormal prompt information according to the latest detection result, for example, prompting a user that the initialization of the volatile memory fails so that the user can check the volatile memory. The manner of outputting the abnormal prompt message may be the same as the foregoing manner, and is not described herein again.
In summary, the detecting the internal communication state between the programmable logic device and the microcontroller includes: the microcontroller sends a data write request and test data to the programmable logic device through a communication bus such as an FSMC bus, an SPI bus, a QSPI bus and the like so that the programmable logic device can write the test data into a corresponding register of the programmable logic device; then the microcontroller sends a data reading request to the programmable logic device again so as to read the data in the corresponding register from the programmable logic device to obtain read-back data; and judging whether the test data and the read-back data are the same to obtain a fifth judgment result. And if the fifth judgment result is that the test data and the read-back data are the same, indicating that the internal communication working state between the programmable logic device and the microcontroller is normal, otherwise indicating that the internal communication working state between the programmable logic device and the microcontroller is abnormal, and recording abnormal information. Further, in response to the detection result being abnormal, the microcontroller reloads the program of the programmable logic device, and internal communication state detection between the programmable logic device and the microcontroller is carried out again after the program is loaded; if the new judgment result obtained after reloading and re-detecting still has abnormity, the microcontroller reloads the programmable logic device program again, detects again and repeats the steps; and when the loading times reach the preset loading times and the initialization still cannot be successful, outputting exception prompt information according to the latest detection result, for example, prompting the user that the internal communication state between the programmable logic device and the microcontroller is abnormal, so that the user can check the internal communication interface between the programmable logic device and the microcontroller. The manner of outputting the abnormal prompt message may be the same as the foregoing manner, and is not described herein again.
In addition, the detection of the required operating clock state of the programmable logic device comprises: sampling a working clock required by the programmable logic device based on a reference clock to obtain a working clock sampling result; and judging whether the sampling result of the working clock is the same as the preset working clock or not to obtain a sixth judgment result. And if the sixth judgment result is that the sampling result of the working clock is the same as the preset working clock, indicating that the working state of the working clock required by the programmable logic device is normal, otherwise indicating that the working state of the working clock required by the programmable logic device is abnormal. Further, in response to the detection result being abnormal, the microcontroller outputs an abnormal prompt message to prompt a user to check the programmable logic device.
In summary, in the embodiments of the present invention, after the display controller is powered on, the video source interface decoding state detection, the communication interface state detection, the volatile memory initialization state detection, the internal communication state detection between the programmable logic device and the microcontroller, and the working clock state detection required by the programmable logic device are performed to determine whether the self state is abnormal, obtain the detection result, record the detection result, and obtain the relevant hardware information affecting the working state of the display controller in advance, so that the user can determine whether the display controller needs to be repaired or related problems are handled, which is beneficial to analyzing and troubleshooting a fault, reduces the difficulty of analyzing and troubleshooting a fault, and improves the efficiency of fault handling. When the detection result shows that the display controller has a problem, the display controller can know whether the problem in the circuit is caused by hardware circuit abnormality or program bug according to the current detection result record, so that the difficulty of troubleshooting the problem is reduced. When the power-on loading of the display controller is in problem, the microcontroller can perform relevant processing according to the error type, so that the abnormal work of the display controller caused by the power-on loading is reduced, and the display controller can work in a stable state.
[ second embodiment ]
As shown in fig. 4, a second embodiment of the present invention provides a power-on self-test apparatus 500. The power-on self-detection apparatus 500 includes, for example, a self-state detection module 510, a detection result recording module 520, and an exception handling module 530.
A self-state detection module 510, configured to perform self-state detection after being powered on, and determine whether the self-state is abnormal to obtain a detection result, where the self-state detection includes: the method comprises the following steps of video source interface decoding state detection, communication interface state detection, volatile memory initialization state detection, internal communication state detection between a programmable logic device and a microcontroller, and working clock state detection required by the programmable logic device.
Specifically, as shown in fig. 5, the self-state detection module 510 includes:
a video source interface decoding state detection unit 511, configured to perform video source interface decoding state detection;
a communication interface state detection unit 512, configured to perform communication interface state detection;
a volatile memory initialization state detection unit 513 configured to perform volatile memory initialization state detection;
an internal communication state detection unit 514 between the programmable logic device and the microcontroller, configured to perform internal communication state detection between the programmable logic device and the microcontroller;
the working clock state detection unit 515 required by the programmable logic device is used for detecting the working clock state required by the programmable logic device.
And a detection result recording module 520, configured to record the detection result.
An exception handling module 530, configured to, in response to the detection result being abnormal, perform a handling operation according to the detection result, where the handling operation includes: and outputting abnormal prompt information.
For the specific working process and technical effects among the modules in the power-on self-detection apparatus 500 in this embodiment, reference is made to the description of the first embodiment, and details are not repeated here.
[ third embodiment ]
As shown in fig. 6, a third embodiment of the present invention provides a power-on self-test system 600. Typically, the power-on self-detection system 600 may be, for example, a video processor, a video splicer, a video switcher, and the like having video and image processing functions such as image and layer movement, and the like. Power-on self-detection system 600 includes, for example, a memory 610 and a processor 630 coupled to memory 610. The memory 610 may be, for example, a non-volatile memory having stored thereon a computer program 611. The processor 630 may be, for example, an embedded processor. The processor 630, when running the computer program 611, performs the power-on self-test method of the first embodiment described above.
The specific working process and technical effects of the power-on self-detection system 600 in this embodiment are described in the foregoing first embodiment.
[ fourth example ] A
As shown in fig. 7, a fourth embodiment of the present invention provides a storage medium, such as a computer-readable storage medium 700. The computer-readable storage medium 700 is, for example, a nonvolatile memory, which is, for example: magnetic media (e.g., hard disks, floppy disks, and magnetic tape), optical media (e.g., CDROM disks and DVDs), magneto-optical media (e.g., optical disks), and hardware devices specially constructed for storing and executing computer-executable instructions (e.g., Read Only Memories (ROMs), Random Access Memories (RAMs), flash memories, etc.). Computer-readable storage medium 700 has stored thereon computer-executable instructions 710. The computer-readable storage medium 700 may execute the computer-executable instructions 710 by one or more processors or processing devices to implement the power-on self-detection method in the foregoing first embodiment.
In addition, it should be understood that the foregoing embodiments are merely exemplary illustrations of the present invention, and the technical solutions of the embodiments can be arbitrarily combined and collocated without conflict between technical features and structural contradictions, which do not violate the purpose of the present invention.
In the embodiments provided in the present invention, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described embodiments of the apparatus are merely illustrative, and for example, a division of a unit is merely a division of one logic function, and an actual implementation may have another division, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may also be distributed on multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. A power-on self-detection method is suitable for a display controller and is characterized by comprising the following steps:
after being electrified, the programmable logic device or the microcontroller detects the self state and judges whether the self state is abnormal or not to obtain a detection result;
recording the detection result;
and responding to the abnormity of the detection result, and performing processing operation with the microcontroller through the programmable logic device according to the detection result.
2. The power-on self-detection method of claim 1, wherein the self-state detection comprises: video source interface decoding state detection, communication interface state detection, volatile memory initialization state detection, internal communication state detection between the programmable logic device and the microcontroller, and working clock state detection required by the programmable logic device.
3. The power-on self-test method according to claim 2, wherein when the self-state test is the volatile memory initialization state test or the internal communication state test between the programmable logic device and the microcontroller, the performing the processing operation according to the test result comprises:
in response to the detection result is abnormal, reloading a programmable logic device program and then carrying out initialization state detection on the volatile memory or internal communication state detection between the programmable logic device and the microcontroller to obtain a new detection result; and
and responding to the new detection result abnormity and the reloading times of the programmable logic device program reaching the preset loading times, and outputting abnormity prompt information according to the new detection result.
4. The power-on self-detection method of claim 2, wherein the video source interface decoding state detection comprises:
reading a field signal, a line signal and an image data effective signal of a current video frame of an input video source;
determining the resolution and frame frequency of the current video frame according to the field signal, the line signal and the image data effective signal; and
and judging whether the resolution and the frame frequency of the current video frame are the same as those of a specified video frame of the input video source or not, and obtaining a first judgment result, wherein the result comprises the first judgment result.
5. The power-on self-test method according to claim 2, wherein the display controller includes a communication interface, the communication interface being an ethernet communication interface; the communication interface state detection comprises:
reading a first connection state value and a first working state value of the Ethernet communication interface from a PHY chip of the Ethernet communication interface, judging whether the Ethernet communication interface is in a connection state according to the first connection state value, judging whether the Ethernet communication interface is in a working state according to the first working state value in response to the Ethernet communication interface being in the connection state, and analyzing a data packet transmitted by the Ethernet communication interface to obtain a first transmission rate value in response to the Ethernet communication interface being in the working state;
analyzing the data packet to obtain first analyzed data, judging whether a communication protocol of the display controller is met or not according to the first analyzed data, and responding to the communication protocol meeting the display controller to obtain a second connection state value, a second working state value and a second transmission rate value according to the first analyzed data;
reading an Ethernet communication interface IP core register of the programmable logic device to obtain a third connection state value, a third working state value and a third transmission rate value of the Ethernet communication interface; and
and judging whether the first connection state value, the second connection state value and the third connection state value are consistent, judging whether the first working state value, the second working state value and the third working state value are consistent, judging whether the first transmission rate value, the second transmission rate value and the third transmission rate value are consistent, and obtaining a second judgment result, wherein the detection result comprises the second judgment result.
6. The power-on self-test method of claim 2, wherein the display controller includes a communication interface, the communication interface being an optical fiber communication interface; the communication interface state detection comprises:
analyzing a data packet transmitted through the optical fiber communication interface to obtain second analyzed data, judging whether a communication protocol of the display controller is met according to the second analyzed data, and responding to the communication protocol meeting the display controller to obtain a fourth connection state value, a fourth working state value and a fourth transmission rate value according to the second analyzed data;
reading an optical fiber communication interface IP core register of the programmable logic device to obtain a fifth connection state value, a fifth working state value and a fifth transmission rate value of the optical fiber communication interface; and
and comparing whether the fourth connection state value is consistent with the fifth connection state value, whether the fourth working state value is consistent with the fifth working state value, and whether the fourth transmission rate value is consistent with the fifth transmission rate value to obtain a third judgment result, wherein the detection result comprises the third judgment result.
7. The power-on self-test method of claim 2, wherein the volatile memory initialization state detection comprises:
reading an initialization state value of a volatile memory; and
and judging whether the initialization state value of the volatile memory is abnormal or not to obtain a fourth judgment result, wherein the detection result comprises the fourth judgment result.
8. The power-on self-test method of claim 2, wherein the internal communication state detection between the programmable logic device and the microcontroller comprises:
sending test data to the programmable logic device to be written into the programmable logic device;
reading read-back data from the programmable logic device; and
and judging whether the test data and the read-back data are the same to obtain a fifth judgment result, wherein the detection result comprises the fifth judgment result.
9. The power-on self-test method of claim 2, wherein the programmable logic device required operational clock state detection comprises:
sampling a working clock required by the programmable logic device based on a reference clock to obtain a working clock sampling result; and
and judging whether the sampling result of the working clock is the same as the preset working clock to obtain a sixth judgment result, wherein the detection result comprises the sixth judgment result.
10. A power-on self-test apparatus for performing the method of claims 1-9, comprising:
a self-state detection module, configured to perform self-state detection through the programmable logic device or the microcontroller after power-on, and determine whether the self-state is abnormal to obtain the detection result, where the self-state detection includes: detecting a decoding state of the video source interface, detecting a state of the communication interface, detecting an initialization state of the volatile memory, detecting an internal communication state between the programmable logic device and the microcontroller, and detecting a state of a working clock required by the programmable logic device; and
the detection result recording module is used for recording the detection result;
and the exception handling module is used for carrying out processing operation on the detection result through the programmable logic device and the microcontroller.
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